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[/] [sd_mmc_emulator/] [trunk/] [rtl/] [ucrc_pack.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------
-- Package
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package ucrc_pack is
 
  component ucrc_ser
    generic (
      POLYNOMIAL : unsigned; -- 4 to 32 bits
      INIT_VALUE : unsigned
    );
    port (
      -- System clock and asynchronous reset
      sys_clk    : in  std_logic; -- clock
      sys_rst_n  : in  std_logic; -- asynchronous reset
      sys_clk_en : in  std_logic; -- clock enable
 
      -- Input and Control
      clear_i : in  std_logic;    -- synchronous reset
      data_i  : in  std_logic;    -- data input
      flush_i : in  std_logic;    -- flush crc
 
      -- Output
      match_o : out std_logic;    -- CRC match flag
      crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
    );
  end component;
 
  component ucrc_par
    generic (
      POLYNOMIAL : unsigned;
      INIT_VALUE : unsigned;
      DATA_WIDTH : integer range 2 to 256
    );
    port (
      -- System clock and asynchronous reset
      sys_clk    : in  std_logic;       -- clock
      sys_rst_n  : in  std_logic;       -- asynchronous reset
      sys_clk_en : in  std_logic;       -- clock enable
 
      -- Input and Control
      clear_i : in  std_logic;    -- synchronous reset
      data_i  : in  unsigned(DATA_WIDTH - 1 downto 0);  -- data input
 
      -- Output
      match_o : out std_logic;       -- CRC match flag
      crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
    );
  end component;
 
end ucrc_pack;
 
-------------------------------------------------------------------------------
-- Serial CRC module
-------------------------------------------------------------------------------
--
-- Author: John Clayton
-- Date  : Jan.  8, 2014 Wrote description and began coding.
--                       Added separate asynchronous and synchronous
--                       reset inputs.  Changed signal names to resemble
--                       other packages within the project, and modified
--                       format to match my own personal coding style.
--
-- Description
-------------------------------------------------------------------------------
-- This is a CRC calculator.
-- It was obtained from http://www.opencores.org.
----------------------------------------------------------------------
----                                                              ----
---- Ultimate CRC.                                                ----
----                                                              ----
---- This file is part of the ultimate CRC project                ----
---- http://www.opencores.org/cores/ultimate_crc/                 ----
----                                                              ----
---- Description                                                  ----
---- CRC generator/checker, serial implementation.                ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2  2005/05/09 19:26:58  gedra
-- Moved match signal into clock enable
--
-- Revision 1.1  2005/05/07 12:47:47  gedra
-- Serial implementation.
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ucrc_ser is
  generic (
    POLYNOMIAL : unsigned := "0001000000100001"; -- 4 to 32 bits
    INIT_VALUE : unsigned := "1111111111111111"
  );
  port (
    -- System clock and asynchronous reset
    sys_clk    : in  std_logic; -- clock
    sys_rst_n  : in  std_logic; -- asynchronous reset
    sys_clk_en : in  std_logic; -- clock enable
 
    -- Input and Control
    clear_i : in  std_logic;    -- synchronous reset
    data_i  : in  std_logic;    -- data input
    flush_i : in  std_logic;    -- flush crc
 
    -- Output
    match_o : out std_logic;    -- CRC match flag
    crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
  );
end ucrc_ser;
 
architecture rtl of ucrc_ser is
 
  constant msb         : integer                        := POLYNOMIAL'length - 1;
  constant init_msb    : integer                        := INIT_VALUE'length - 1;
  constant p           : unsigned(msb downto 0) := POLYNOMIAL;
 
  signal din, crc_msb  : unsigned(msb downto 1);
  signal crc, zero, fb : unsigned(msb downto 0);
 
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
  PCHK : if msb /= init_msb generate
    process
    begin
      report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
        severity failure;
      wait;
    end process;
  end generate PCHK;
 
  PCHK2 : if (msb < 3) or (msb > 31) generate
    process
    begin
      report "POLYNOMIAL must be of order 4 to 32!"
        severity failure;
      wait;
    end process;
  end generate PCHK2;
 
  PCHK3 : if p(0) /= '1' generate      -- LSB must be 1
    process
    begin
      report "POLYNOMIAL must have lsb set to 1!"
        severity failure;
      wait;
    end process;
  end generate PCHK3;
 
   zero  <= (others => '0');
   crc_o <= crc;
 
-- Create vectors of data input and MSB of CRC
   DI : for i in 1 to msb generate
     din(i)     <= data_i;
     crc_msb(i) <= crc(msb);
   end generate DI;
 
-- Feedback signals
   fb(0)            <= data_i xor crc(msb);
   fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));
 
-- CRC process
  CRCP : process (sys_clk, sys_rst_n)
  begin
    if sys_rst_n='0' then -- async. reset
      crc     <= INIT_VALUE;
      match_o <= '0';
    elsif rising_edge(sys_clk) then
      if clear_i='1' then -- sync. reset
        crc     <= INIT_VALUE;
        match_o <= '0';
      else
        if sys_clk_en = '1' then
          -- CRC generation
          if flush_i = '1' then
            crc(0)            <= '0';
            crc(msb downto 1) <= crc(msb - 1 downto 0);
          else
            crc <= fb;
          end if;
          -- CRC match checker (if data plus CRC is clocked in without errors,
          -- the CRC register ends up with all zeroes)
          if fb = zero then
            match_o <= '1';
          else
            match_o <= '0';
          end if;
        end if;
      end if;
    end if;
  end process;
 
end rtl;
 
-------------------------------------------------------------------------------
-- Parallel CRC module
-------------------------------------------------------------------------------
--
-- Author: John Clayton
-- Date  : Jan.  8, 2014 Wrote description and began coding.
--                       Added separate asynchronous and synchronous
--                       reset inputs.  Changed signal names to resemble
--                       other packages within the project, and modified
--                       format to match my own personal coding style.
--
-- Description
-------------------------------------------------------------------------------
-- This is a CRC calculator.
-- It was obtained from http://www.opencores.org.
----------------------------------------------------------------------
----                                                              ----
---- Ultimate CRC.                                                ----
----                                                              ----
---- This file is part of the ultimate CRC projectt               ----
---- http://www.opencores.org/cores/ultimate_crc/                 ----
----                                                              ----
---- Description                                                  ----
---- CRC generator/checker, parallel implementation.              ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1  2005/05/09 15:58:38  gedra
-- Parallel implementation
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ucrc_par is
  generic (
    POLYNOMIAL : unsigned := "0001000000100001";
    INIT_VALUE : unsigned := "1111111111111111";
    DATA_WIDTH : integer range 2 to 256 := 8
  );
  port (
    -- System clock and asynchronous reset
    sys_clk    : in  std_logic;       -- clock
    sys_rst_n  : in  std_logic;       -- asynchronous reset
    sys_clk_en : in  std_logic;       -- clock enable
 
    -- Input and Control
    clear_i : in  std_logic; -- synchronous reset
    data_i  : in  unsigned(DATA_WIDTH - 1 downto 0);  -- data input
 
    -- Output
    match_o : out std_logic;       -- CRC match flag
    crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
  );
end ucrc_par;
 
architecture rtl of ucrc_par is
 
  constant msb      : integer                := POLYNOMIAL'length - 1;
  constant init_msb : integer                := INIT_VALUE'length - 1;
  constant p        : unsigned(msb downto 0) := POLYNOMIAL;
  constant dw       : integer                := DATA_WIDTH;
  constant pw       : integer                := POLYNOMIAL'length;
  type fb_array is array (dw downto 1) of unsigned(msb downto 0);
  type dmsb_array is array (dw downto 1) of unsigned(msb downto 1);
  signal crca       : fb_array;
  signal da, ma     : dmsb_array;
  signal crc, zero  : unsigned(msb downto 0);
 
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
  PCHK1 : if msb /= init_msb generate
    process
    begin
      report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
        severity failure;
      wait;
    end process;
  end generate PCHK1;
 
  PCHK2 : if (msb < 3) or (msb > 31) generate
    process
    begin
      report "POLYNOMIAL must be of order 4 to 32!"
        severity failure;
      wait;
    end process;
  end generate PCHK2;
 
  PCHK3 : if p(0) /= '1' generate      -- LSB must be 1
    process
    begin
      report "POLYNOMIAL must have lsb set to 1!"
        severity failure;
      wait;
    end process;
  end generate PCHK3;
 
-- Generate vector of each data bit
  CA : for i in 1 to dw generate       -- data bits
    DAT : for j in 1 to msb generate
      da(i)(j) <= data_i(i - 1);
    end generate DAT;
  end generate CA;
 
-- Generate vector of each CRC MSB
   MS0 : for i in 1 to msb generate
     ma(1)(i) <= crc(msb);
   end generate MS0;
   MSP : for i in 2 to dw generate
     MSU : for j in 1 to msb generate
       ma(i)(j) <= crca(i - 1)(msb);
     end generate MSU;
   end generate MSP;
 
-- Generate feedback matrix
   crca(1)(0)            <= da(1)(1) xor crc(msb);
   crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
   FB : for i in 2 to dw generate
     crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
     crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
                              ((da(i) xor ma(i)) and p(msb downto 1));
   end generate FB;
 
-- CRC process
  crc_o <= crc;
  zero  <= (others => '0');
 
  CRCP : process (sys_clk, sys_rst_n)
  begin
    if sys_rst_n='0' then -- async. reset
      crc     <= INIT_VALUE;
      match_o <= '0';
    elsif rising_edge(sys_clk) then
      if clear_i='1' then -- sync. reset
        crc     <= INIT_VALUE;
        match_o <= '0';
      elsif sys_clk_en = '1' then
        crc <= crca(dw);
        if crca(dw) = zero then
          match_o <= '1';
        else
          match_o <= '0';
        end if;
      end if;
    end if;
  end process;
 
end rtl;
 
 

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Subversion Repositories sd_mmc_emulator

[/] [sd_mmc_emulator/] [trunk/] [rtl/] [ucrc_pack.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jclaytons	`--------------------------------------------------------------------------`
2			`-- Package`
3			`--`
4
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.numeric_std.all;`
8
9			`package ucrc_pack is`
10
11			`component ucrc_ser`
12			`generic (`
13			`POLYNOMIAL : unsigned; -- 4 to 32 bits`
14			`INIT_VALUE : unsigned`
15			`);`
16			`port (`
17			`-- System clock and asynchronous reset`
18			`sys_clk : in std_logic; -- clock`
19			`sys_rst_n : in std_logic; -- asynchronous reset`
20			`sys_clk_en : in std_logic; -- clock enable`
21
22			`-- Input and Control`
23			`clear_i : in std_logic; -- synchronous reset`
24			`data_i : in std_logic; -- data input`
25			`flush_i : in std_logic; -- flush crc`
26
27			`-- Output`
28			`match_o : out std_logic; -- CRC match flag`
29			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
30			`);`
31			`end component;`
32
33			`component ucrc_par`
34			`generic (`
35			`POLYNOMIAL : unsigned;`
36			`INIT_VALUE : unsigned;`
37			`DATA_WIDTH : integer range 2 to 256`
38			`);`
39			`port (`
40			`-- System clock and asynchronous reset`
41			`sys_clk : in std_logic; -- clock`
42			`sys_rst_n : in std_logic; -- asynchronous reset`
43			`sys_clk_en : in std_logic; -- clock enable`
44
45			`-- Input and Control`
46			`clear_i : in std_logic; -- synchronous reset`
47			`data_i : in unsigned(DATA_WIDTH - 1 downto 0); -- data input`
48
49			`-- Output`
50			`match_o : out std_logic; -- CRC match flag`
51			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
52			`);`
53			`end component;`
54
55			`end ucrc_pack;`
56
57			`-------------------------------------------------------------------------------`
58			`-- Serial CRC module`
59			`-------------------------------------------------------------------------------`
60			`--`
61			`-- Author: John Clayton`
62			`-- Date : Jan. 8, 2014 Wrote description and began coding.`
63			`-- Added separate asynchronous and synchronous`
64			`-- reset inputs. Changed signal names to resemble`
65			`-- other packages within the project, and modified`
66			`-- format to match my own personal coding style.`
67			`--`
68			`-- Description`
69			`-------------------------------------------------------------------------------`
70			`-- This is a CRC calculator.`
71			`-- It was obtained from http://www.opencores.org.`
72			`----------------------------------------------------------------------`
73			`---- ----`
74			`---- Ultimate CRC. ----`
75			`---- ----`
76			`---- This file is part of the ultimate CRC project ----`
77			`---- http://www.opencores.org/cores/ultimate_crc/ ----`
78			`---- ----`
79			`---- Description ----`
80			`---- CRC generator/checker, serial implementation. ----`
81			`---- ----`
82			`---- ----`
83			`---- To Do: ----`
84			`---- - ----`
85			`---- ----`
86			`---- Author(s): ----`
87			`---- - Geir Drange, gedra@opencores.org ----`
88			`---- ----`
89			`----------------------------------------------------------------------`
90			`---- ----`
91			`---- Copyright (C) 2005 Authors and OPENCORES.ORG ----`
92			`---- ----`
93			`---- This source file may be used and distributed without ----`
94			`---- restriction provided that this copyright statement is not ----`
95			`---- removed from the file and that any derivative work contains ----`
96			`---- the original copyright notice and the associated disclaimer. ----`
97			`---- ----`
98			`---- This source file is free software; you can redistribute it ----`
99			`---- and/or modify it under the terms of the GNU General ----`
100			`---- Public License as published by the Free Software Foundation; ----`
101			`---- either version 2.0 of the License, or (at your option) any ----`
102			`---- later version. ----`
103			`---- ----`
104			`---- This source is distributed in the hope that it will be ----`
105			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
106			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
107			`---- PURPOSE. See the GNU General Public License for more details.----`
108			`---- ----`
109			`---- You should have received a copy of the GNU General ----`
110			`---- Public License along with this source; if not, download it ----`
111			`---- from http://www.gnu.org/licenses/gpl.txt ----`
112			`---- ----`
113			`----------------------------------------------------------------------`
114			`--`
115			`-- CVS Revision History`
116			`--`
117			`-- $Log: not supported by cvs2svn $`
118			`-- Revision 1.2 2005/05/09 19:26:58 gedra`
119			`-- Moved match signal into clock enable`
120			`--`
121			`-- Revision 1.1 2005/05/07 12:47:47 gedra`
122			`-- Serial implementation.`
123			`--`
124			`--`
125			`--`
126
127			`library ieee;`
128			`use ieee.std_logic_1164.all;`
129			`use ieee.numeric_std.all;`
130
131			`entity ucrc_ser is`
132			`generic (`
133			`POLYNOMIAL : unsigned := "0001000000100001"; -- 4 to 32 bits`
134			`INIT_VALUE : unsigned := "1111111111111111"`
135			`);`
136			`port (`
137			`-- System clock and asynchronous reset`
138			`sys_clk : in std_logic; -- clock`
139			`sys_rst_n : in std_logic; -- asynchronous reset`
140			`sys_clk_en : in std_logic; -- clock enable`
141
142			`-- Input and Control`
143			`clear_i : in std_logic; -- synchronous reset`
144			`data_i : in std_logic; -- data input`
145			`flush_i : in std_logic; -- flush crc`
146
147			`-- Output`
148			`match_o : out std_logic; -- CRC match flag`
149			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
150			`);`
151			`end ucrc_ser;`
152
153			`architecture rtl of ucrc_ser is`
154
155			`constant msb : integer := POLYNOMIAL'length - 1;`
156			`constant init_msb : integer := INIT_VALUE'length - 1;`
157			`constant p : unsigned(msb downto 0) := POLYNOMIAL;`
158
159			`signal din, crc_msb : unsigned(msb downto 1);`
160			`signal crc, zero, fb : unsigned(msb downto 0);`
161
162			`begin`
163
164			`-- Parameter checking: Invalid generics will abort simulation/synthesis`
165			`PCHK : if msb /= init_msb generate`
166			`process`
167			`begin`
168			`report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"`
169			`severity failure;`
170			`wait;`
171			`end process;`
172			`end generate PCHK;`
173
174			`PCHK2 : if (msb < 3) or (msb > 31) generate`
175			`process`
176			`begin`
177			`report "POLYNOMIAL must be of order 4 to 32!"`
178			`severity failure;`
179			`wait;`
180			`end process;`
181			`end generate PCHK2;`
182
183			`PCHK3 : if p(0) /= '1' generate -- LSB must be 1`
184			`process`
185			`begin`
186			`report "POLYNOMIAL must have lsb set to 1!"`
187			`severity failure;`
188			`wait;`
189			`end process;`
190			`end generate PCHK3;`
191
192			`zero <= (others => '0');`
193			`crc_o <= crc;`
194
195			`-- Create vectors of data input and MSB of CRC`
196			`DI : for i in 1 to msb generate`
197			`din(i) <= data_i;`
198			`crc_msb(i) <= crc(msb);`
199			`end generate DI;`
200
201			`-- Feedback signals`
202			`fb(0) <= data_i xor crc(msb);`
203			`fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));`
204
205			`-- CRC process`
206			`CRCP : process (sys_clk, sys_rst_n)`
207			`begin`
208			`if sys_rst_n='0' then -- async. reset`
209			`crc <= INIT_VALUE;`
210			`match_o <= '0';`
211			`elsif rising_edge(sys_clk) then`
212			`if clear_i='1' then -- sync. reset`
213			`crc <= INIT_VALUE;`
214			`match_o <= '0';`
215			`else`
216			`if sys_clk_en = '1' then`
217			`-- CRC generation`
218			`if flush_i = '1' then`
219			`crc(0) <= '0';`
220			`crc(msb downto 1) <= crc(msb - 1 downto 0);`
221			`else`
222			`crc <= fb;`
223			`end if;`
224			`-- CRC match checker (if data plus CRC is clocked in without errors,`
225			`-- the CRC register ends up with all zeroes)`
226			`if fb = zero then`
227			`match_o <= '1';`
228			`else`
229			`match_o <= '0';`
230			`end if;`
231			`end if;`
232			`end if;`
233			`end if;`
234			`end process;`
235
236			`end rtl;`
237
238			`-------------------------------------------------------------------------------`
239			`-- Parallel CRC module`
240			`-------------------------------------------------------------------------------`
241			`--`
242			`-- Author: John Clayton`
243			`-- Date : Jan. 8, 2014 Wrote description and began coding.`
244			`-- Added separate asynchronous and synchronous`
245			`-- reset inputs. Changed signal names to resemble`
246			`-- other packages within the project, and modified`
247			`-- format to match my own personal coding style.`
248			`--`
249			`-- Description`
250			`-------------------------------------------------------------------------------`
251			`-- This is a CRC calculator.`
252			`-- It was obtained from http://www.opencores.org.`
253			`----------------------------------------------------------------------`
254			`---- ----`
255			`---- Ultimate CRC. ----`
256			`---- ----`
257			`---- This file is part of the ultimate CRC projectt ----`
258			`---- http://www.opencores.org/cores/ultimate_crc/ ----`
259			`---- ----`
260			`---- Description ----`
261			`---- CRC generator/checker, parallel implementation. ----`
262			`---- ----`
263			`---- ----`
264			`---- To Do: ----`
265			`---- - ----`
266			`---- ----`
267			`---- Author(s): ----`
268			`---- - Geir Drange, gedra@opencores.org ----`
269			`---- ----`
270			`----------------------------------------------------------------------`
271			`---- ----`
272			`---- Copyright (C) 2005 Authors and OPENCORES.ORG ----`
273			`---- ----`
274			`---- This source file may be used and distributed without ----`
275			`---- restriction provided that this copyright statement is not ----`
276			`---- removed from the file and that any derivative work contains ----`
277			`---- the original copyright notice and the associated disclaimer. ----`
278			`---- ----`
279			`---- This source file is free software; you can redistribute it ----`
280			`---- and/or modify it under the terms of the GNU General ----`
281			`---- Public License as published by the Free Software Foundation; ----`
282			`---- either version 2.0 of the License, or (at your option) any ----`
283			`---- later version. ----`
284			`---- ----`
285			`---- This source is distributed in the hope that it will be ----`
286			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
287			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
288			`---- PURPOSE. See the GNU General Public License for more details.----`
289			`---- ----`
290			`---- You should have received a copy of the GNU General ----`
291			`---- Public License along with this source; if not, download it ----`
292			`---- from http://www.gnu.org/licenses/gpl.txt ----`
293			`---- ----`
294			`----------------------------------------------------------------------`
295			`--`
296			`-- CVS Revision History`
297			`--`
298			`-- $Log: not supported by cvs2svn $`
299			`-- Revision 1.1 2005/05/09 15:58:38 gedra`
300			`-- Parallel implementation`
301			`--`
302			`--`
303			`--`
304
305			`library ieee;`
306			`use ieee.std_logic_1164.all;`
307			`use ieee.numeric_std.all;`
308
309			`entity ucrc_par is`
310			`generic (`
311			`POLYNOMIAL : unsigned := "0001000000100001";`
312			`INIT_VALUE : unsigned := "1111111111111111";`
313			`DATA_WIDTH : integer range 2 to 256 := 8`
314			`);`
315			`port (`
316			`-- System clock and asynchronous reset`
317			`sys_clk : in std_logic; -- clock`
318			`sys_rst_n : in std_logic; -- asynchronous reset`
319			`sys_clk_en : in std_logic; -- clock enable`
320
321			`-- Input and Control`
322			`clear_i : in std_logic; -- synchronous reset`
323			`data_i : in unsigned(DATA_WIDTH - 1 downto 0); -- data input`
324
325			`-- Output`
326			`match_o : out std_logic; -- CRC match flag`
327			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
328			`);`
329			`end ucrc_par;`
330
331			`architecture rtl of ucrc_par is`
332
333			`constant msb : integer := POLYNOMIAL'length - 1;`
334			`constant init_msb : integer := INIT_VALUE'length - 1;`
335			`constant p : unsigned(msb downto 0) := POLYNOMIAL;`
336			`constant dw : integer := DATA_WIDTH;`
337			`constant pw : integer := POLYNOMIAL'length;`
338			`type fb_array is array (dw downto 1) of unsigned(msb downto 0);`
339			`type dmsb_array is array (dw downto 1) of unsigned(msb downto 1);`
340			`signal crca : fb_array;`
341			`signal da, ma : dmsb_array;`
342			`signal crc, zero : unsigned(msb downto 0);`
343
344			`begin`
345
346			`-- Parameter checking: Invalid generics will abort simulation/synthesis`
347			`PCHK1 : if msb /= init_msb generate`
348			`process`
349			`begin`
350			`report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"`
351			`severity failure;`
352			`wait;`
353			`end process;`
354			`end generate PCHK1;`
355
356			`PCHK2 : if (msb < 3) or (msb > 31) generate`
357			`process`
358			`begin`
359			`report "POLYNOMIAL must be of order 4 to 32!"`
360			`severity failure;`
361			`wait;`
362			`end process;`
363			`end generate PCHK2;`
364
365			`PCHK3 : if p(0) /= '1' generate -- LSB must be 1`
366			`process`
367			`begin`
368			`report "POLYNOMIAL must have lsb set to 1!"`
369			`severity failure;`
370			`wait;`
371			`end process;`
372			`end generate PCHK3;`
373
374			`-- Generate vector of each data bit`
375			`CA : for i in 1 to dw generate -- data bits`
376			`DAT : for j in 1 to msb generate`
377			`da(i)(j) <= data_i(i - 1);`
378			`end generate DAT;`
379			`end generate CA;`
380
381			`-- Generate vector of each CRC MSB`
382			`MS0 : for i in 1 to msb generate`
383			`ma(1)(i) <= crc(msb);`
384			`end generate MS0;`
385			`MSP : for i in 2 to dw generate`
386			`MSU : for j in 1 to msb generate`
387			`ma(i)(j) <= crca(i - 1)(msb);`
388			`end generate MSU;`
389			`end generate MSP;`
390
391			`-- Generate feedback matrix`
392			`crca(1)(0) <= da(1)(1) xor crc(msb);`
393			`crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));`
394			`FB : for i in 2 to dw generate`
395			`crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);`
396			`crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor`
397			`((da(i) xor ma(i)) and p(msb downto 1));`
398			`end generate FB;`
399
400			`-- CRC process`
401			`crc_o <= crc;`
402			`zero <= (others => '0');`
403
404			`CRCP : process (sys_clk, sys_rst_n)`
405			`begin`
406			`if sys_rst_n='0' then -- async. reset`
407			`crc <= INIT_VALUE;`
408			`match_o <= '0';`
409			`elsif rising_edge(sys_clk) then`
410			`if clear_i='1' then -- sync. reset`
411			`crc <= INIT_VALUE;`
412			`match_o <= '0';`
413			`elsif sys_clk_en = '1' then`
414			`crc <= crca(dw);`
415			`if crca(dw) = zero then`
416			`match_o <= '1';`
417			`else`
418			`match_o <= '0';`
419			`end if;`
420			`end if;`
421			`end if;`
422			`end process;`
423
424			`end rtl;`
425
426