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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 81

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//`include "timescale.v"
`define tTLH 10 //Clock rise time
`define tHL 10 //Clock fall time
`define tISU 6 //Input setup time
`define tIH 0 //Input hold time
`define tODL 14 //Output delay
 
`define BLOCKSIZE 512
`define MEMSIZE 1000
`define BLOCK_BUFFER_SIZE 1
`define TIME_BUSY 64
 
module sdModel(
  input sdClk,
  tri cmd,
  tri [3:0] dat
 
);
 
 
reg oeCmd;
reg oeDat;
reg cmdOut;
reg datOut;
 
reg [5:0] lastCMD;
reg cardIdentificationState;
 
assign cmd = oeCmd ? cmdOut : 1'bz;
assign dat = oeDat ? datOut : 4'bz;
 
 
reg [`MEMSIZE:0] FLASHmem [0:`BLOCKSIZE-1];
reg  [`BLOCK_BUFFER_SIZE-1:0] indatabuffer [0:`BLOCKSIZE-1];
 
reg [46:0]inCmd;
reg [5:0]cmdRead;
reg [7:0] cmdWrite;
reg crcIn;
reg crcEn;
reg crcRst;
reg [31:0] CardStatus;
reg [15:0] RCA;
reg [31:0] OCR;
reg [120:0] CID;
reg Busy; //0 when busy
wire [6:0] crcOut;
 
reg [3 :0]CurrentState;
 
`define RCASTART 16'h20
`define OCRSTART 32'hff8000
`define STATUSSTART 32'h0
`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999  //Just some random data not really usefull anyway 
 
`define outDelay 4
reg [2:0] outDelayCnt;
parameter SIZE = 10;
parameter CONTENT_SIZE = 40;
parameter
    IDLE   =  10'b0000_0000_01,
    READ_CMD   =  10'b0000_0000_10,
    ANALYZE_CMD     =  10'b0000_0001_00,
    SEND_CMD        =  10'b0000_0010_00;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
reg ValidCmd;
reg inValidCmd;
 
reg [7:0] response_S;
reg [135:0] response_CMD;
integer responseType;
CRC_7 CRC_7(
crcIn,
crcEn,
sdClk,
crcRst,
crcOut);
reg appendCrc;
reg [5:0] startUppCnt;
 
//Card initinCMd
initial $readmemh("FLASH.txt",FLASHmem);
 
integer k;
initial begin
        $display("Contents of Mem after reading data file:");
        for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
end
reg qCmd;
reg [2:0] crcCnt;
initial begin
  cardIdentificationState<=1;
  state<=IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
  datOut<=0;
  inCmd<=0;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
end
 
//CARD logic
 
always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
begin : FSM_COMBO
 next_state  = 0;
case(state)
IDLE: begin
   if (!cmd)
     next_state = READ_CMD;
  else
     next_state = IDLE;
end
READ_CMD: begin
  if (cmdRead>= 47)
     next_state = ANALYZE_CMD;
  else
     next_state =  READ_CMD;
 end
 ANALYZE_CMD: begin
  if ((ValidCmd  )   && (outDelayCnt >= `outDelay ))
     next_state = SEND_CMD;
  else if (inValidCmd)
     next_state =  IDLE;
 else
    next_state =  ANALYZE_CMD;
 end
 SEND_CMD: begin
    if (cmdWrite>= response_S)
     next_state = IDLE;
  else
     next_state =  SEND_CMD;
 
 end
 
 
 endcase
end
 
always @ (posedge sdClk  )
begin : FSM_SEQ
    state <= next_state;
 
end
 
 
always @ (posedge sdClk) begin
 startUppCnt<=startUppCnt+1;
 OCR[31]<=Busy;
 if (startUppCnt == `TIME_BUSY)
   Busy <=1;
end
 
 
always @ (posedge sdClk) begin
   qCmd<=cmd;
end
 
//read data and cmd on rising edge
always @ (posedge sdClk) begin
 case(state)
   IDLE: begin
 
      crcIn<=0;
      crcEn<=0;
      crcRst<=1;
      oeCmd<=0;
      oeDat<=0;
      cmdRead<=0;
      appendCrc<=0;
      ValidCmd<=0;
      inValidCmd=0;
      cmdWrite<=0;
      crcCnt<=0;
      response_CMD<=0;
      response_S<=0;
      outDelayCnt<=0;
      responseType=0;
    end
   READ_CMD: begin //read cmd
      crcEn<=1;
      crcRst<=0;
      crcIn <= #`tIH qCmd;
      inCmd[47-cmdRead]  <= #`tIH qCmd;
      cmdRead <= #1 cmdRead+1;
      if (cmdRead >= 40)
         crcEn<=0;
 
      if (cmdRead == 46) begin
          oeCmd<=1;
     cmdOut<=1;
      end
   end
 
   ANALYZE_CMD: begin//check for valid cmd
   //Wrong CRC go idle
    if (inCmd[46] == 0) //start
      inValidCmd=1;
    else if (inCmd[7:1] != crcOut) begin
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
    end
    else if  (inCmd[0] != 1)  begin//stop 
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
    end
    else begin
 
      case(inCmd[45:40])
 
        2 : response_S <= 136;
        3 : response_S <= 48;
        7 : response_S <= 48;
        8 : response_S <= 0;
        14 : response_S <= 0;
        17 : response_S <= 48;
        24 : response_S <= 48;
        33 : response_S <= 48;
        55 : response_S <= 48;
        41 : response_S <= 48;
    endcase
         case(inCmd[45:40])
 
            response_CMD <= 0;
            cardIdentificationState<=1;
            ResetCard;
        end
        2 : begin
         if (lastCMD != 41 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               $display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:8] <= CID;
        appendCrc<=0;
        CardStatus[12:9] <=2;
        end
        3 :  begin
           if (lastCMD != 3 && outDelayCnt==0 ) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               $display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:112] <= RCA[15:0] ;
        response_CMD[111:96] <= CardStatus[15:0] ;
        appendCrc<=1;
        CardStatus[12:9] <=3;
        cardIdentificationState<=0;
        end
        8 : response_CMD[127:96] <= 0; //V1.0 card
        17 : response_CMD[127:96]<= 48;
        24 : response_CMD[127:96] <= 48;
        33 : response_CMD[127:96] <= 48;
        55 :
        begin
          response_CMD[127:96] <= CardStatus ;
          CardStatus[5] <=1;      //Next CMD is AP specific CMD
          appendCrc<=1;
        end
        41 :
        begin
         if (cardIdentificationState) begin
            if (lastCMD != 55 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               $display(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               CardStatus[3]<=1;
            end
            else begin
             responseType=3;
             response_CMD[127:96] <= OCR;
             appendCrc<=0;
             CardStatus[5] <=0;
            if (Busy==1)
              CardStatus[12:9] <=1;
           end
        end
       end
 
    endcase
     ValidCmd<=1;
     crcIn<=0;
 
     outDelayCnt<=outDelayCnt+1;
     if (outDelayCnt==`outDelay)
       crcRst<=1;
     oeCmd<=1;
     cmdOut<=1;
     response_CMD[135:134] <=0;
 
    if (responseType != 3)
       response_CMD[133:128] <=inCmd[45:40];
    if (responseType == 3)
       response_CMD[133:128] <=6'b111111;
 
     lastCMD <=inCmd[45:40];
    end
   end
 
 
 
 endcase
end
 
always @ ( negedge sdClk) begin
 case(state)
 
SEND_CMD: begin
     crcRst<=0;
     crcEn<=1;
    cmdWrite<=cmdWrite+1;
    if (response_S!=0)
     cmdOut<=0;
   else
      cmdOut<=1;
 
    if ((cmdWrite>0) &&  (cmdWrite < response_S-8)) begin
      cmdOut<=response_CMD[135-cmdWrite];
      crcIn<=response_CMD[134-cmdWrite];
      if (cmdWrite >= response_S-9)
       crcEn<=0;
    end
   else if (cmdWrite!=0) begin
     crcEn<=0;
     cmdOut<=crcOut[6-crcCnt];
     crcCnt<=crcCnt+1;
      if (responseType == 3)
           cmdOut<=1;
   end
  if (cmdWrite == response_S-1)
    cmdOut<=1;
 
  end
 endcase
end
 
integer sdModel_file_desc;
initial
begin
  sdModel_file_desc = $fopen("log/sd_model.log");
  if (sdModel_file_desc < 2)
  begin
    $display("*E Could not open/create testbench log file in ../log/ directory!");
    $finish;
  end
end
 
task ResetCard; //  MAC registers
begin
  cardIdentificationState<=1;
  state<=IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
  datOut<=0;
  inCmd<=0;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
end
endtask
 
 
endmodule

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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 81

Line No.	Rev	Author	Line
1	79	tac2	//`include "timescale.v"
2			`define tTLH 10 //Clock rise time
3			`define tHL 10 //Clock fall time
4			`define tISU 6 //Input setup time
5			`define tIH 0 //Input hold time
6			`define tODL 14 //Output delay
7
8			`define BLOCKSIZE 512
9			`define MEMSIZE 1000
10			`define BLOCK_BUFFER_SIZE 1
11			`define TIME_BUSY 64
12
13			`module sdModel(`
14			`input sdClk,`
15			`tri cmd,`
16			`tri [3:0] dat`
17
18			`);`
19
20
21			`reg oeCmd;`
22			`reg oeDat;`
23			`reg cmdOut;`
24			`reg datOut;`
25
26			`reg [5:0] lastCMD;`
27			`reg cardIdentificationState;`
28
29			`assign cmd = oeCmd ? cmdOut : 1'bz;`
30			`assign dat = oeDat ? datOut : 4'bz;`
31
32
33			reg [`MEMSIZE:0] FLASHmem [0:`BLOCKSIZE-1];
34			reg [`BLOCK_BUFFER_SIZE-1:0] indatabuffer [0:`BLOCKSIZE-1];
35
36			`reg [46:0]inCmd;`
37			`reg [5:0]cmdRead;`
38			`reg [7:0] cmdWrite;`
39			`reg crcIn;`
40			`reg crcEn;`
41			`reg crcRst;`
42			`reg [31:0] CardStatus;`
43			`reg [15:0] RCA;`
44			`reg [31:0] OCR;`
45			`reg [120:0] CID;`
46			`reg Busy; //0 when busy`
47			`wire [6:0] crcOut;`
48
49			`reg [3 :0]CurrentState;`
50
51			`define RCASTART 16'h20
52			`define OCRSTART 32'hff8000
53			`define STATUSSTART 32'h0
54			`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
55
56			`define outDelay 4
57			`reg [2:0] outDelayCnt;`
58			`parameter SIZE = 10;`
59			`parameter CONTENT_SIZE = 40;`
60			`parameter`
61			`IDLE = 10'b0000_0000_01,`
62			`READ_CMD = 10'b0000_0000_10,`
63			`ANALYZE_CMD = 10'b0000_0001_00,`
64			`SEND_CMD = 10'b0000_0010_00;`
65			`reg [SIZE-1:0] state;`
66			`reg [SIZE-1:0] next_state;`
67
68			`reg ValidCmd;`
69			`reg inValidCmd;`
70
71			`reg [7:0] response_S;`
72			`reg [135:0] response_CMD;`
73			`integer responseType;`
74			`CRC_7 CRC_7(`
75			`crcIn,`
76			`crcEn,`
77			`sdClk,`
78			`crcRst,`
79			`crcOut);`
80			`reg appendCrc;`
81			`reg [5:0] startUppCnt;`
82
83			`//Card initinCMd`
84			`initial $readmemh("FLASH.txt",FLASHmem);`
85
86			`integer k;`
87			`initial begin`
88			`$display("Contents of Mem after reading data file:");`
89			`for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);`
90			`end`
91			`reg qCmd;`
92			`reg [2:0] crcCnt;`
93			`initial begin`
94			`cardIdentificationState<=1;`
95			`state<=IDLE;`
96			`Busy<=0;`
97			`oeCmd<=0;`
98			`crcCnt<=0;`
99			`qCmd<=1;`
100			`oeDat<=0;`
101			`cmdOut<=0;`
102			`cmdWrite<=0;`
103			`datOut<=0;`
104			`inCmd<=0;`
105			`responseType=0;`
106			`crcIn<=0;`
107			`response_S<=0;`
108			`crcEn<=0;`
109			`crcRst<=0;`
110			`cmdRead<=0;`
111			`ValidCmd<=0;`
112			`inValidCmd=0;`
113			`appendCrc<=0;`
114			RCA<= `RCASTART;
115			OCR<= `OCRSTART;
116			CardStatus <= `STATUSSTART;
117			CID<=`CIDSTART;
118			`response_CMD<=0;`
119			`outDelayCnt<=0;`
120			`end`
121
122			`//CARD logic`
123
124			`always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)`
125			`begin : FSM_COMBO`
126			`next_state = 0;`
127			`case(state)`
128			`IDLE: begin`
129			`if (!cmd)`
130			`next_state = READ_CMD;`
131			`else`
132			`next_state = IDLE;`
133			`end`
134			`READ_CMD: begin`
135			`if (cmdRead>= 47)`
136			`next_state = ANALYZE_CMD;`
137			`else`
138			`next_state = READ_CMD;`
139			`end`
140			`ANALYZE_CMD: begin`
141			if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
142			`next_state = SEND_CMD;`
143			`else if (inValidCmd)`
144			`next_state = IDLE;`
145			`else`
146			`next_state = ANALYZE_CMD;`
147			`end`
148			`SEND_CMD: begin`
149			`if (cmdWrite>= response_S)`
150			`next_state = IDLE;`
151			`else`
152			`next_state = SEND_CMD;`
153
154			`end`
155
156
157			`endcase`
158			`end`
159
160			`always @ (posedge sdClk )`
161			`begin : FSM_SEQ`
162			`state <= next_state;`
163
164			`end`
165
166
167			`always @ (posedge sdClk) begin`
168			`startUppCnt<=startUppCnt+1;`
169			`OCR[31]<=Busy;`
170			if (startUppCnt == `TIME_BUSY)
171			`Busy <=1;`
172			`end`
173
174
175			`always @ (posedge sdClk) begin`
176			`qCmd<=cmd;`
177			`end`
178
179			`//read data and cmd on rising edge`
180			`always @ (posedge sdClk) begin`
181			`case(state)`
182			`IDLE: begin`
183
184			`crcIn<=0;`
185			`crcEn<=0;`
186			`crcRst<=1;`
187			`oeCmd<=0;`
188			`oeDat<=0;`
189			`cmdRead<=0;`
190			`appendCrc<=0;`
191			`ValidCmd<=0;`
192			`inValidCmd=0;`
193			`cmdWrite<=0;`
194			`crcCnt<=0;`
195			`response_CMD<=0;`
196			`response_S<=0;`
197			`outDelayCnt<=0;`
198			`responseType=0;`
199			`end`
200			`READ_CMD: begin //read cmd`
201			`crcEn<=1;`
202			`crcRst<=0;`
203			crcIn <= #`tIH qCmd;
204			inCmd[47-cmdRead] <= #`tIH qCmd;
205			`cmdRead <= #1 cmdRead+1;`
206			`if (cmdRead >= 40)`
207			`crcEn<=0;`
208
209			`if (cmdRead == 46) begin`
210			`oeCmd<=1;`
211			`cmdOut<=1;`
212			`end`
213			`end`
214
215			`ANALYZE_CMD: begin//check for valid cmd`
216			`//Wrong CRC go idle`
217			`if (inCmd[46] == 0) //start`
218			`inValidCmd=1;`
219			`else if (inCmd[7:1] != crcOut) begin`
220			`inValidCmd=1;`
221			`$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
222			`$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
223			`end`
224			`else if (inCmd[0] != 1) begin//stop`
225			`inValidCmd=1;`
226			`$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
227			`$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
228			`end`
229			`else begin`
230
231			`case(inCmd[45:40])`
232
233			`2 : response_S <= 136;`
234			`3 : response_S <= 48;`
235			`7 : response_S <= 48;`
236			`8 : response_S <= 0;`
237			`14 : response_S <= 0;`
238			`17 : response_S <= 48;`
239			`24 : response_S <= 48;`
240			`33 : response_S <= 48;`
241			`55 : response_S <= 48;`
242			`41 : response_S <= 48;`
243			`endcase`
244			`case(inCmd[45:40])`
245
246			`response_CMD <= 0;`
247			`cardIdentificationState<=1;`
248			`ResetCard;`
249			`end`
250			`2 : begin`
251			`if (lastCMD != 41 && outDelayCnt==0) begin`
252			`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
253			`$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
254			`CardStatus[3]<=1;`
255			`end`
256			`response_CMD[127:8] <= CID;`
257			`appendCrc<=0;`
258			`CardStatus[12:9] <=2;`
259			`end`
260			`3 : begin`
261			`if (lastCMD != 3 && outDelayCnt==0 ) begin`
262			`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
263			`$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
264			`CardStatus[3]<=1;`
265			`end`
266			`response_CMD[127:112] <= RCA[15:0] ;`
267			`response_CMD[111:96] <= CardStatus[15:0] ;`
268			`appendCrc<=1;`
269			`CardStatus[12:9] <=3;`
270			`cardIdentificationState<=0;`
271			`end`
272			`8 : response_CMD[127:96] <= 0; //V1.0 card`
273			`17 : response_CMD[127:96]<= 48;`
274			`24 : response_CMD[127:96] <= 48;`
275			`33 : response_CMD[127:96] <= 48;`
276			`55 :`
277			`begin`
278			`response_CMD[127:96] <= CardStatus ;`
279			`CardStatus[5] <=1; //Next CMD is AP specific CMD`
280			`appendCrc<=1;`
281			`end`
282			`41 :`
283			`begin`
284			`if (cardIdentificationState) begin`
285			`if (lastCMD != 55 && outDelayCnt==0) begin`
286			`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;`
287			`$display(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;`
288			`CardStatus[3]<=1;`
289			`end`
290			`else begin`
291			`responseType=3;`
292			`response_CMD[127:96] <= OCR;`
293			`appendCrc<=0;`
294			`CardStatus[5] <=0;`
295			`if (Busy==1)`
296			`CardStatus[12:9] <=1;`
297			`end`
298			`end`
299			`end`
300
301			`endcase`
302			`ValidCmd<=1;`
303			`crcIn<=0;`
304
305			`outDelayCnt<=outDelayCnt+1;`
306			if (outDelayCnt==`outDelay)
307			`crcRst<=1;`
308			`oeCmd<=1;`
309			`cmdOut<=1;`
310			`response_CMD[135:134] <=0;`
311
312			`if (responseType != 3)`
313			`response_CMD[133:128] <=inCmd[45:40];`
314			`if (responseType == 3)`
315			`response_CMD[133:128] <=6'b111111;`
316
317			`lastCMD <=inCmd[45:40];`
318			`end`
319			`end`
320
321
322
323			`endcase`
324			`end`
325
326			`always @ ( negedge sdClk) begin`
327			`case(state)`
328
329			`SEND_CMD: begin`
330			`crcRst<=0;`
331			`crcEn<=1;`
332			`cmdWrite<=cmdWrite+1;`
333			`if (response_S!=0)`
334			`cmdOut<=0;`
335			`else`
336			`cmdOut<=1;`
337
338			`if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin`
339			`cmdOut<=response_CMD[135-cmdWrite];`
340			`crcIn<=response_CMD[134-cmdWrite];`
341			`if (cmdWrite >= response_S-9)`
342			`crcEn<=0;`
343			`end`
344			`else if (cmdWrite!=0) begin`
345			`crcEn<=0;`
346			`cmdOut<=crcOut[6-crcCnt];`
347			`crcCnt<=crcCnt+1;`
348			`if (responseType == 3)`
349			`cmdOut<=1;`
350			`end`
351			`if (cmdWrite == response_S-1)`
352			`cmdOut<=1;`
353
354			`end`
355			`endcase`
356			`end`
357
358			`integer sdModel_file_desc;`
359			`initial`
360			`begin`
361			`sdModel_file_desc = $fopen("log/sd_model.log");`
362			`if (sdModel_file_desc < 2)`
363			`begin`
364			`$display("*E Could not open/create testbench log file in ../log/ directory!");`
365			`$finish;`
366			`end`
367			`end`
368
369			`task ResetCard; // MAC registers`
370			`begin`
371			`cardIdentificationState<=1;`
372			`state<=IDLE;`
373			`Busy<=0;`
374			`oeCmd<=0;`
375			`crcCnt<=0;`
376			`qCmd<=1;`
377			`oeDat<=0;`
378			`cmdOut<=0;`
379			`cmdWrite<=0;`
380			`datOut<=0;`
381			`inCmd<=0;`
382			`responseType=0;`
383			`crcIn<=0;`
384			`response_S<=0;`
385			`crcEn<=0;`
386			`crcRst<=0;`
387			`cmdRead<=0;`
388			`ValidCmd<=0;`
389			`inValidCmd=0;`
390			`appendCrc<=0;`
391			RCA<= `RCASTART;
392			OCR<= `OCRSTART;
393			CardStatus <= `STATUSSTART;
394			CID<=`CIDSTART;
395			`response_CMD<=0;`
396			`outDelayCnt<=0;`
397			`end`
398			`endtask`
399
400
401			`endmodule`