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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Blame information for rev 97

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//`include "timescale.v"
`include "SD_defines.v"
`define tTLH 10 //Clock rise time
`define tHL 10 //Clock fall time
`define tISU 6 //Input setup time
`define tIH 0 //Input hold time
`define tODL 14 //Output delay
 
`define BLOCKSIZE 512
`define MEMSIZE 2048 // 4 block
`define BLOCK_BUFFER_SIZE 1
`define TIME_BUSY 64
 
`define PRG 7
`define RCV 6
`define DATAS 5
`define TRAN 4
module sdModel(
  input sdClk,
  tri cmd,
  tri [3:0] dat
 
);
 
 
reg oeCmd;
reg oeDat;
reg cmdOut;
reg [3:0] datOut;
reg [10:0] transf_cnt;
 
 
 
reg [5:0] lastCMD;
reg cardIdentificationState;
reg CardTransferActive;
reg [2:0] BusWidth;
 
assign cmd = oeCmd ? cmdOut : 1'bz;
assign dat = oeDat ? datOut : 4'bz;
 
reg InbuffStatus;
reg [31:0] BlockAddr;
reg [7:0] Inbuff [0:511];
reg [7:0] FLASHmem [0:`MEMSIZE];
 
 
reg [46:0]inCmd;
reg [5:0]cmdRead;
reg [7:0] cmdWrite;
reg crcIn;
reg crcEn;
reg crcRst;
reg [31:0] CardStatus;
reg [15:0] RCA;
reg [31:0] OCR;
reg [120:0] CID;
reg Busy; //0 when busy
wire [6:0] crcOut;
reg [3:0] crc_c;
 
reg [3:0] CurrentState;
reg [3:0] DataCurrentState;
`define RCASTART 16'h20
`define OCRSTART 32'hff8000
`define STATUSSTART 32'h0
`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999  //Just some random data not really usefull anyway 
 
`define outDelay 4
reg [2:0] outDelayCnt;
reg [9:0] flash_write_cnt;
reg [8:0] flash_blockwrite_cnt;
 
parameter SIZE = 10;
parameter CONTENT_SIZE = 40;
parameter
    IDLE   =  10'b0000_0000_01,
    READ_CMD   =  10'b0000_0000_10,
    ANALYZE_CMD     =  10'b0000_0001_00,
    SEND_CMD        =  10'b0000_0010_00;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
parameter
    DATA_IDLE   =10'b0000_0000_01,
    READ_WAITS  =10'b0000_0000_10,
    READ_DATA  = 10'b0000_0001_00,
    WRITE_FLASH =10'b0000_0010_00,
    WRITE_DATA  =10'b0000_0100_00;
parameter okcrctoken = 4'b0101;
parameter invalidcrctoken = 4'b1111;
reg [SIZE-1:0] dataState;
reg [SIZE-1:0] next_datastate;
 
reg ValidCmd;
reg inValidCmd;
 
reg [7:0] response_S;
reg [135:0] response_CMD;
integer responseType;
 
     reg [9:0] block_cnt;
     reg wptr;
     reg crc_ok;
     reg [3:0] last_din;
 
 
 
reg crcDat_rst;
reg crcDat_en;
reg [3:0] crcDat_in;
wire [15:0] crcDat_out [3:0];
 
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen
  SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
end
endgenerate
SD_CRC_7 CRC_7(
crcIn,
crcEn,
sdClk,
crcRst,
crcOut);
 
 
reg appendCrc;
reg [5:0] startUppCnt;
 
reg q_start_bit;
//Card initinCMd
initial $readmemh("FLASH.txt",FLASHmem);
 
integer k;
initial begin
        $display("Contents of Mem after reading data file:");
        for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
end
reg qCmd;
reg [2:0] crcCnt;
initial begin
  cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
 
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
     flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
 
//CARD logic
 
always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
begin : FSM_COMBO
 next_state  = 0;
case(state)
IDLE: begin
   if (!cmd)
     next_state = READ_CMD;
  else
     next_state = IDLE;
end
READ_CMD: begin
  if (cmdRead>= 47)
     next_state = ANALYZE_CMD;
  else
     next_state =  READ_CMD;
 end
 ANALYZE_CMD: begin
  if ((ValidCmd  )   && (outDelayCnt >= `outDelay ))
     next_state = SEND_CMD;
  else if (inValidCmd)
     next_state =  IDLE;
 else
    next_state =  ANALYZE_CMD;
 end
 SEND_CMD: begin
    if (cmdWrite>= response_S)
     next_state = IDLE;
  else
     next_state =  SEND_CMD;
 
 end
 
 
 endcase
end
 
always @ (dataState or CardStatus or crc_c or flash_write_cnt or q_start_bit)
begin : FSM_COMBODAT
 next_datastate  = 0;
case(dataState)
 DATA_IDLE: begin
   if (CardStatus[12:9]==`RCV )
     next_datastate = READ_WAITS;
   else if (CardStatus[12:9]==`DATAS )
     next_datastate = WRITE_DATA;
   else
     next_datastate = DATA_IDLE;
 end
 
 READ_WAITS: begin
   if (q_start_bit == 1'b0 )
     next_datastate =  READ_DATA;
   else
     next_datastate =  READ_WAITS;
 end
 
 READ_DATA : begin
  if (crc_c==0  )
     next_datastate =  WRITE_FLASH;
  else
     next_datastate =  READ_DATA;
 end
  WRITE_FLASH : begin
  if (flash_write_cnt>265 )
     next_datastate =  DATA_IDLE;
  else
     next_datastate =  WRITE_FLASH;
 
 
end
 
 
 
 
 
 endcase
end
 
always @ (posedge sdClk  )
 begin
 
    q_start_bit <= dat[0];
 end
 
always @ (posedge sdClk  )
begin : FSM_SEQ
    state <= next_state;
end
 
always @ (posedge sdClk  )
begin : FSM_SEQDAT
    dataState <= next_datastate;
end
 
 
 
always @ (posedge sdClk) begin
if (CardTransferActive) begin
 if (InbuffStatus==0) //empty
   CardStatus[8]<=1;
  else
   CardStatus[8]<=0;
  end
else
  CardStatus[8]<=0;
 
 startUppCnt<=startUppCnt+1;
 OCR[31]<=Busy;
 if (startUppCnt == `TIME_BUSY)
   Busy <=1;
end
 
 
always @ (posedge sdClk) begin
   qCmd<=cmd;
end
 
//read data and cmd on rising edge
always @ (posedge sdClk) begin
 case(state)
   IDLE: begin
 
      crcIn<=0;
      crcEn<=0;
      crcRst<=1;
      oeCmd<=0;
      oeDat<=0;
      cmdRead<=0;
      appendCrc<=0;
      ValidCmd<=0;
      inValidCmd=0;
      cmdWrite<=0;
      crcCnt<=0;
      response_CMD<=0;
      response_S<=0;
      outDelayCnt<=0;
      responseType=0;
    end
   READ_CMD: begin //read cmd
      crcEn<=1;
      crcRst<=0;
      crcIn <= #`tIH qCmd;
      inCmd[47-cmdRead]  <= #`tIH qCmd;
      cmdRead <= #1 cmdRead+1;
      if (cmdRead >= 40)
         crcEn<=0;
 
      if (cmdRead == 46) begin
          oeCmd<=1;
     cmdOut<=1;
      end
   end
 
   ANALYZE_CMD: begin//check for valid cmd
   //Wrong CRC go idle
    if (inCmd[46] == 0) //start
      inValidCmd=1;
    else if (inCmd[7:1] != crcOut) begin
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
    end
    else if  (inCmd[0] != 1)  begin//stop 
      inValidCmd=1;
      $fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
      $display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
    end
    else begin
      if(outDelayCnt ==0)
        CardStatus[3]<=0;
      case(inCmd[45:40])
 
        2 : response_S <= 136;
        3 : response_S <= 48;
        7 : response_S <= 48;
        8 : response_S <= 0;
        14 : response_S <= 0;
        16 : response_S <= 48;
        17 : response_S <= 48;
        24 : response_S <= 48;
        33 : response_S <= 48;
        55 : response_S <= 48;
        41 : response_S <= 48;
    endcase
         case(inCmd[45:40])
 
            response_CMD <= 0;
            cardIdentificationState<=1;
            ResetCard;
        end
        2 : begin
         if (lastCMD != 41 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               $display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:8] <= CID;
        appendCrc<=0;
        CardStatus[12:9] <=2;
        end
        3 :  begin
           if (lastCMD != 2 && outDelayCnt==0 ) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               $display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
               CardStatus[3]<=1;
            end
        response_CMD[127:112] <= RCA[15:0] ;
        response_CMD[111:96] <= CardStatus[15:0] ;
        appendCrc<=1;
        CardStatus[12:9] <=3;
        cardIdentificationState<=0;
       end
        6 : begin
           if (lastCMD == 55 && outDelayCnt==0) begin
              if (inCmd[9:8] == 2'b10) begin
               BusWidth <=4;
                    $display(sdModel_file_desc, "**BUS WIDTH 4 ") ;
               end
              else
               BusWidth <=1;
 
              response_S<=48;
              response_CMD[127:96] <= CardStatus;
           end
           else if (outDelayCnt==0)begin
             response_CMD <= 0;
             response_S<=0;
             $fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
             $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
            end
        end
        7: begin
         if (outDelayCnt==0) begin
          if (inCmd[39:24]== RCA[15:0]) begin
              CardTransferActive <= 1;
              response_CMD[127:96] <= CardStatus ;
              CardStatus[12:9] <=`TRAN;
          end
          else begin
               CardTransferActive <= 0;
               response_CMD[127:96] <= CardStatus ;
               CardStatus[12:9] <=3;
          end
         end
        end
        8 : response_CMD[127:96] <= 0; //V1.0 card
        16 : begin
          response_CMD[127:96] <= CardStatus ;
 
        end
        17 : response_CMD[127:96]<= 48;
        24 : begin
          if (outDelayCnt==0) begin
            if (CardStatus[12:9] == 4) begin //If card is in transferstate
              if (CardStatus[8]) begin //If Free write buffer           
                CardStatus[12:9] <=`RCV;//Put card in Rcv state
                response_CMD[127:96] <= CardStatus ;
                BlockAddr = inCmd[39:8];
                if (BlockAddr%512 !=0)
                  $display("**Block Misalign Error");
              end
              else begin
                response_CMD[127:96] <= CardStatus;
                 $fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
                 $display("**Error Try to blockwrite when No Free Writebuffer") ;
             end
           end
           else begin
             response_S <= 0;
             response_CMD[127:96] <= 0;
           end
         end
 
       end
        33 : response_CMD[127:96] <= 48;
        55 :
        begin
          response_CMD[127:96] <= CardStatus ;
          CardStatus[5] <=1;      //Next CMD is AP specific CMD
          appendCrc<=1;
        end
        41 :
        begin
         if (cardIdentificationState) begin
            if (lastCMD != 55 && outDelayCnt==0) begin
               $fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               $display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
               CardStatus[3]<=1;
            end
            else begin
             responseType=3;
             response_CMD[127:96] <= OCR;
             appendCrc<=0;
             CardStatus[5] <=0;
            if (Busy==1)
              CardStatus[12:9] <=1;
           end
        end
       end
 
    endcase
     ValidCmd<=1;
     crcIn<=0;
 
     outDelayCnt<=outDelayCnt+1;
     if (outDelayCnt==`outDelay)
       crcRst<=1;
     oeCmd<=1;
     cmdOut<=1;
     response_CMD[135:134] <=0;
 
    if (responseType != 3)
       response_CMD[133:128] <=inCmd[45:40];
    if (responseType == 3)
       response_CMD[133:128] <=6'b111111;
 
     lastCMD <=inCmd[45:40];
    end
   end
 
 
 
 endcase
end
 
always @ ( negedge sdClk) begin
 case(state)
 
SEND_CMD: begin
     crcRst<=0;
     crcEn<=1;
    cmdWrite<=cmdWrite+1;
    if (response_S!=0)
     cmdOut<=0;
   else
      cmdOut<=1;
 
    if ((cmdWrite>0) &&  (cmdWrite < response_S-8)) begin
      cmdOut<=response_CMD[135-cmdWrite];
      crcIn<=response_CMD[134-cmdWrite];
      if (cmdWrite >= response_S-9)
       crcEn<=0;
    end
   else if (cmdWrite!=0) begin
     crcEn<=0;
     cmdOut<=crcOut[6-crcCnt];
     crcCnt<=crcCnt+1;
      if (responseType == 3)
           cmdOut<=1;
   end
  if (cmdWrite == response_S-1)
    cmdOut<=1;
 
  end
 endcase
end
 
always @ (posedge sdClk) begin
 
  case (dataState)
  DATA_IDLE: begin
      oeDat<=0;
  end
 
  READ_WAITS: begin
      oeDat<=0;
      crcDat_rst<=0;
      crcDat_en<=1;
      crcDat_in<=0;
      crc_c<=15;//
      crc_ok<=1;
  end
  READ_DATA: begin
 
 
    InbuffStatus<=1;
    if (transf_cnt<`BIT_BLOCK_REC) begin
       if (wptr)
         Inbuff[block_cnt][7:4] <= dat;
       else
          Inbuff[block_cnt][3:0] <= dat;
 
       crcDat_in<=dat;
       crc_ok<=1;
       transf_cnt<=transf_cnt+1;
       if (wptr)
         block_cnt<=block_cnt+1;
       wptr<=~wptr;
    end
    else if  ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
       transf_cnt<=transf_cnt+1;
       crcDat_en<=0;
       last_din <=dat;
 
       if (transf_cnt> `BIT_BLOCK_REC) begin
        crc_c<=crc_c-1;
 
          if (crcDat_out[0][crc_c] != last_din[0])
           crc_ok<=0;
          if  (crcDat_out[1][crc_c] != last_din[1])
           crc_ok<=0;
          if  (crcDat_out[2][crc_c] != last_din[2])
           crc_ok<=0;
          if  (crcDat_out[3][crc_c] != last_din[3])
           crc_ok<=0;
      end
    end
  end
  WRITE_FLASH: begin
     oeDat<=1;
     block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
 
 
  end
 
  endcase
 
 
end
 
 
 
 
always @ (posedge sdClk) begin
 
  case (dataState)
  IDLE: begin
 
 
 
  end
  WRITE_FLASH: begin
    flash_write_cnt<=flash_write_cnt+1;
     CardStatus[12:9] <= `PRG;
    if (flash_write_cnt == 0)
      datOut<=1;
    else if(flash_write_cnt == 1)
     datOut[0]<=0;
 
    else if ((flash_write_cnt > 1) && (flash_write_cnt < 6)) begin
      if (crc_ok)
        datOut[0] <=okcrctoken[5-flash_write_cnt];
      else
        datOut[0] <= invalidcrctoken[5-flash_write_cnt];
    end
    else if  ((flash_write_cnt >= 6) && (flash_write_cnt < 263)) begin
       datOut[0]<=0;
       datOut[1]<=1;
       datOut[2]<=1;
       datOut[3]<=1;
      flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
       FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
       FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
    end
    else begin
      datOut<=1;
      InbuffStatus<=0;
      CardStatus[12:9] <= `TRAN;
    end
  end
endcase
end
 
integer sdModel_file_desc;
 
initial
begin
  sdModel_file_desc = $fopen("log/sd_model.log");
  if (sdModel_file_desc < 2)
  begin
    $display("*E Could not open/create testbench log file in /log/ directory!");
    $finish;
  end
end
 
task ResetCard; //  MAC registers
begin
 cardIdentificationState<=1;
  state<=IDLE;
  dataState<=DATA_IDLE;
  Busy<=0;
  oeCmd<=0;
  crcCnt<=0;
  CardTransferActive<=0;
  qCmd<=1;
  oeDat<=0;
  cmdOut<=0;
  cmdWrite<=0;
 
  InbuffStatus<=0;
  datOut<=0;
  inCmd<=0;
  BusWidth<=1;
  responseType=0;
  crcIn<=0;
  response_S<=0;
  crcEn<=0;
  crcRst<=0;
  cmdRead<=0;
  ValidCmd<=0;
  inValidCmd=0;
  appendCrc<=0;
  RCA<= `RCASTART;
  OCR<= `OCRSTART;
  CardStatus <= `STATUSSTART;
  CID<=`CIDSTART;
  response_CMD<=0;
  outDelayCnt<=0;
  crcDat_rst<=1;
  crcDat_en<=0;
  crcDat_in<=0;
  transf_cnt<=0;
  BlockAddr<=0;
  block_cnt <=0;
     wptr<=0;
     transf_cnt<=0;
     crcDat_rst<=1;
     crcDat_en<=0;
     crcDat_in<=0;
     flash_write_cnt<=0;
flash_blockwrite_cnt<=0;
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	79	tac2	//`include "timescale.v"
2	96	tac2	`include "SD_defines.v"
3	79	tac2	`define tTLH 10 //Clock rise time
4			`define tHL 10 //Clock fall time
5			`define tISU 6 //Input setup time
6			`define tIH 0 //Input hold time
7			`define tODL 14 //Output delay
8
9			`define BLOCKSIZE 512
10	96	tac2	`define MEMSIZE 2048 // 4 block
11	79	tac2	`define BLOCK_BUFFER_SIZE 1
12			`define TIME_BUSY 64
13
14	96	tac2	`define PRG 7
15			`define RCV 6
16			`define DATAS 5
17			`define TRAN 4
18	79	tac2	`module sdModel(`
19			`input sdClk,`
20			`tri cmd,`
21			`tri [3:0] dat`
22
23			`);`
24
25
26			`reg oeCmd;`
27			`reg oeDat;`
28			`reg cmdOut;`
29	96	tac2	`reg [3:0] datOut;`
30			`reg [10:0] transf_cnt;`
31	79	tac2
32	96	tac2
33
34	79	tac2	`reg [5:0] lastCMD;`
35			`reg cardIdentificationState;`
36	96	tac2	`reg CardTransferActive;`
37			`reg [2:0] BusWidth;`
38	79	tac2
39			`assign cmd = oeCmd ? cmdOut : 1'bz;`
40			`assign dat = oeDat ? datOut : 4'bz;`
41
42	96	tac2	`reg InbuffStatus;`
43			`reg [31:0] BlockAddr;`
44			`reg [7:0] Inbuff [0:511];`
45			reg [7:0] FLASHmem [0:`MEMSIZE];
46	79	tac2
47
48			`reg [46:0]inCmd;`
49			`reg [5:0]cmdRead;`
50			`reg [7:0] cmdWrite;`
51			`reg crcIn;`
52			`reg crcEn;`
53			`reg crcRst;`
54			`reg [31:0] CardStatus;`
55			`reg [15:0] RCA;`
56			`reg [31:0] OCR;`
57			`reg [120:0] CID;`
58			`reg Busy; //0 when busy`
59			`wire [6:0] crcOut;`
60	96	tac2	`reg [3:0] crc_c;`
61
62			`reg [3:0] CurrentState;`
63			`reg [3:0] DataCurrentState;`
64	79	tac2	`define RCASTART 16'h20
65			`define OCRSTART 32'hff8000
66			`define STATUSSTART 32'h0
67			`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
68
69			`define outDelay 4
70			`reg [2:0] outDelayCnt;`
71	96	tac2	`reg [9:0] flash_write_cnt;`
72			`reg [8:0] flash_blockwrite_cnt;`
73
74	79	tac2	`parameter SIZE = 10;`
75			`parameter CONTENT_SIZE = 40;`
76			`parameter`
77			`IDLE = 10'b0000_0000_01,`
78			`READ_CMD = 10'b0000_0000_10,`
79			`ANALYZE_CMD = 10'b0000_0001_00,`
80			`SEND_CMD = 10'b0000_0010_00;`
81			`reg [SIZE-1:0] state;`
82			`reg [SIZE-1:0] next_state;`
83
84	96	tac2	`parameter`
85			`DATA_IDLE =10'b0000_0000_01,`
86			`READ_WAITS =10'b0000_0000_10,`
87			`READ_DATA = 10'b0000_0001_00,`
88			`WRITE_FLASH =10'b0000_0010_00,`
89			`WRITE_DATA =10'b0000_0100_00;`
90			`parameter okcrctoken = 4'b0101;`
91			`parameter invalidcrctoken = 4'b1111;`
92			`reg [SIZE-1:0] dataState;`
93			`reg [SIZE-1:0] next_datastate;`
94
95	79	tac2	`reg ValidCmd;`
96			`reg inValidCmd;`
97
98			`reg [7:0] response_S;`
99			`reg [135:0] response_CMD;`
100			`integer responseType;`
101	96	tac2
102			`reg [9:0] block_cnt;`
103			`reg wptr;`
104			`reg crc_ok;`
105			`reg [3:0] last_din;`
106
107
108
109			`reg crcDat_rst;`
110			`reg crcDat_en;`
111			`reg [3:0] crcDat_in;`
112			`wire [15:0] crcDat_out [3:0];`
113
114			`genvar i;`
115			`generate`
116			`for(i=0; i<4; i=i+1) begin:CRC_16_gen`
117	97	tac2	`SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);`
118	96	tac2	`end`
119			`endgenerate`
120			`SD_CRC_7 CRC_7(`
121	79	tac2	`crcIn,`
122			`crcEn,`
123			`sdClk,`
124			`crcRst,`
125			`crcOut);`
126	96	tac2
127
128	79	tac2	`reg appendCrc;`
129			`reg [5:0] startUppCnt;`
130
131	96	tac2	`reg q_start_bit;`
132	79	tac2	`//Card initinCMd`
133			`initial $readmemh("FLASH.txt",FLASHmem);`
134
135			`integer k;`
136			`initial begin`
137			`$display("Contents of Mem after reading data file:");`
138			`for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);`
139			`end`
140			`reg qCmd;`
141			`reg [2:0] crcCnt;`
142			`initial begin`
143			`cardIdentificationState<=1;`
144			`state<=IDLE;`
145	96	tac2	`dataState<=DATA_IDLE;`
146	79	tac2	`Busy<=0;`
147			`oeCmd<=0;`
148			`crcCnt<=0;`
149	96	tac2	`CardTransferActive<=0;`
150	79	tac2	`qCmd<=1;`
151			`oeDat<=0;`
152			`cmdOut<=0;`
153			`cmdWrite<=0;`
154	96	tac2
155			`InbuffStatus<=0;`
156	79	tac2	`datOut<=0;`
157			`inCmd<=0;`
158	96	tac2	`BusWidth<=1;`
159	79	tac2	`responseType=0;`
160			`crcIn<=0;`
161			`response_S<=0;`
162			`crcEn<=0;`
163			`crcRst<=0;`
164			`cmdRead<=0;`
165			`ValidCmd<=0;`
166			`inValidCmd=0;`
167			`appendCrc<=0;`
168			RCA<= `RCASTART;
169			OCR<= `OCRSTART;
170			CardStatus <= `STATUSSTART;
171			CID<=`CIDSTART;
172			`response_CMD<=0;`
173			`outDelayCnt<=0;`
174	96	tac2	`crcDat_rst<=1;`
175			`crcDat_en<=0;`
176			`crcDat_in<=0;`
177			`transf_cnt<=0;`
178			`BlockAddr<=0;`
179			`block_cnt <=0;`
180			`wptr<=0;`
181			`transf_cnt<=0;`
182			`crcDat_rst<=1;`
183			`crcDat_en<=0;`
184			`crcDat_in<=0;`
185			`flash_write_cnt<=0;`
186			`flash_blockwrite_cnt<=0;`
187	79	tac2	`end`
188
189			`//CARD logic`
190
191			`always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)`
192			`begin : FSM_COMBO`
193			`next_state = 0;`
194			`case(state)`
195			`IDLE: begin`
196			`if (!cmd)`
197			`next_state = READ_CMD;`
198			`else`
199			`next_state = IDLE;`
200			`end`
201			`READ_CMD: begin`
202			`if (cmdRead>= 47)`
203			`next_state = ANALYZE_CMD;`
204			`else`
205			`next_state = READ_CMD;`
206			`end`
207			`ANALYZE_CMD: begin`
208			if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
209			`next_state = SEND_CMD;`
210			`else if (inValidCmd)`
211			`next_state = IDLE;`
212			`else`
213			`next_state = ANALYZE_CMD;`
214			`end`
215			`SEND_CMD: begin`
216			`if (cmdWrite>= response_S)`
217			`next_state = IDLE;`
218			`else`
219			`next_state = SEND_CMD;`
220
221			`end`
222
223
224			`endcase`
225			`end`
226
227	96	tac2	`always @ (dataState or CardStatus or crc_c or flash_write_cnt or q_start_bit)`
228			`begin : FSM_COMBODAT`
229			`next_datastate = 0;`
230			`case(dataState)`
231			`DATA_IDLE: begin`
232			if (CardStatus[12:9]==`RCV )
233			`next_datastate = READ_WAITS;`
234			else if (CardStatus[12:9]==`DATAS )
235			`next_datastate = WRITE_DATA;`
236			`else`
237			`next_datastate = DATA_IDLE;`
238			`end`
239
240			`READ_WAITS: begin`
241			`if (q_start_bit == 1'b0 )`
242			`next_datastate = READ_DATA;`
243			`else`
244			`next_datastate = READ_WAITS;`
245			`end`
246
247			`READ_DATA : begin`
248			`if (crc_c==0 )`
249			`next_datastate = WRITE_FLASH;`
250			`else`
251			`next_datastate = READ_DATA;`
252			`end`
253			`WRITE_FLASH : begin`
254			`if (flash_write_cnt>265 )`
255			`next_datastate = DATA_IDLE;`
256			`else`
257			`next_datastate = WRITE_FLASH;`
258
259
260			`end`
261
262
263
264
265
266			`endcase`
267			`end`
268
269	79	tac2	`always @ (posedge sdClk )`
270	96	tac2	`begin`
271
272			`q_start_bit <= dat[0];`
273			`end`
274
275			`always @ (posedge sdClk )`
276	79	tac2	`begin : FSM_SEQ`
277	96	tac2	`state <= next_state;`
278	79	tac2	`end`
279
280	96	tac2	`always @ (posedge sdClk )`
281			`begin : FSM_SEQDAT`
282			`dataState <= next_datastate;`
283			`end`
284	79	tac2
285	96	tac2
286
287	79	tac2	`always @ (posedge sdClk) begin`
288	96	tac2	`if (CardTransferActive) begin`
289			`if (InbuffStatus==0) //empty`
290			`CardStatus[8]<=1;`
291			`else`
292			`CardStatus[8]<=0;`
293			`end`
294			`else`
295			`CardStatus[8]<=0;`
296
297	79	tac2	`startUppCnt<=startUppCnt+1;`
298			`OCR[31]<=Busy;`
299			if (startUppCnt == `TIME_BUSY)
300			`Busy <=1;`
301			`end`
302
303
304			`always @ (posedge sdClk) begin`
305			`qCmd<=cmd;`
306			`end`
307
308			`//read data and cmd on rising edge`
309			`always @ (posedge sdClk) begin`
310			`case(state)`
311			`IDLE: begin`
312
313			`crcIn<=0;`
314			`crcEn<=0;`
315			`crcRst<=1;`
316			`oeCmd<=0;`
317			`oeDat<=0;`
318			`cmdRead<=0;`
319			`appendCrc<=0;`
320			`ValidCmd<=0;`
321			`inValidCmd=0;`
322			`cmdWrite<=0;`
323			`crcCnt<=0;`
324			`response_CMD<=0;`
325			`response_S<=0;`
326			`outDelayCnt<=0;`
327			`responseType=0;`
328			`end`
329			`READ_CMD: begin //read cmd`
330			`crcEn<=1;`
331			`crcRst<=0;`
332			crcIn <= #`tIH qCmd;
333			inCmd[47-cmdRead] <= #`tIH qCmd;
334			`cmdRead <= #1 cmdRead+1;`
335			`if (cmdRead >= 40)`
336			`crcEn<=0;`
337
338			`if (cmdRead == 46) begin`
339			`oeCmd<=1;`
340			`cmdOut<=1;`
341			`end`
342			`end`
343
344			`ANALYZE_CMD: begin//check for valid cmd`
345			`//Wrong CRC go idle`
346			`if (inCmd[46] == 0) //start`
347			`inValidCmd=1;`
348			`else if (inCmd[7:1] != crcOut) begin`
349			`inValidCmd=1;`
350			`$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
351			`$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;`
352			`end`
353			`else if (inCmd[0] != 1) begin//stop`
354			`inValidCmd=1;`
355			`$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
356			`$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;`
357			`end`
358			`else begin`
359	96	tac2	`if(outDelayCnt ==0)`
360			`CardStatus[3]<=0;`
361	79	tac2	`case(inCmd[45:40])`
362
363			`2 : response_S <= 136;`
364			`3 : response_S <= 48;`
365			`7 : response_S <= 48;`
366			`8 : response_S <= 0;`
367			`14 : response_S <= 0;`
368	96	tac2	`16 : response_S <= 48;`
369	79	tac2	`17 : response_S <= 48;`
370			`24 : response_S <= 48;`
371			`33 : response_S <= 48;`
372			`55 : response_S <= 48;`
373			`41 : response_S <= 48;`
374			`endcase`
375			`case(inCmd[45:40])`
376
377			`response_CMD <= 0;`
378			`cardIdentificationState<=1;`
379			`ResetCard;`
380			`end`
381			`2 : begin`
382			`if (lastCMD != 41 && outDelayCnt==0) begin`
383			`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
384			`$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
385			`CardStatus[3]<=1;`
386			`end`
387			`response_CMD[127:8] <= CID;`
388			`appendCrc<=0;`
389			`CardStatus[12:9] <=2;`
390			`end`
391			`3 : begin`
392	96	tac2	`if (lastCMD != 2 && outDelayCnt==0 ) begin`
393	79	tac2	`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
394			`$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;`
395			`CardStatus[3]<=1;`
396			`end`
397			`response_CMD[127:112] <= RCA[15:0] ;`
398			`response_CMD[111:96] <= CardStatus[15:0] ;`
399			`appendCrc<=1;`
400			`CardStatus[12:9] <=3;`
401			`cardIdentificationState<=0;`
402	96	tac2	`end`
403			`6 : begin`
404			`if (lastCMD == 55 && outDelayCnt==0) begin`
405			`if (inCmd[9:8] == 2'b10) begin`
406			`BusWidth <=4;`
407			`$display(sdModel_file_desc, "**BUS WIDTH 4 ") ;`
408			`end`
409			`else`
410			`BusWidth <=1;`
411
412			`response_S<=48;`
413			`response_CMD[127:96] <= CardStatus;`
414			`end`
415			`else if (outDelayCnt==0)begin`
416			`response_CMD <= 0;`
417			`response_S<=0;`
418			`$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
419			`$display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;`
420			`end`
421			`end`
422			`7: begin`
423			`if (outDelayCnt==0) begin`
424			`if (inCmd[39:24]== RCA[15:0]) begin`
425			`CardTransferActive <= 1;`
426			`response_CMD[127:96] <= CardStatus ;`
427			CardStatus[12:9] <=`TRAN;
428			`end`
429			`else begin`
430			`CardTransferActive <= 0;`
431			`response_CMD[127:96] <= CardStatus ;`
432			`CardStatus[12:9] <=3;`
433			`end`
434			`end`
435			`end`
436	79	tac2	`8 : response_CMD[127:96] <= 0; //V1.0 card`
437	96	tac2	`16 : begin`
438			`response_CMD[127:96] <= CardStatus ;`
439
440			`end`
441	79	tac2	`17 : response_CMD[127:96]<= 48;`
442	96	tac2	`24 : begin`
443			`if (outDelayCnt==0) begin`
444			`if (CardStatus[12:9] == 4) begin //If card is in transferstate`
445			`if (CardStatus[8]) begin //If Free write buffer`
446			CardStatus[12:9] <=`RCV;//Put card in Rcv state
447			`response_CMD[127:96] <= CardStatus ;`
448			`BlockAddr = inCmd[39:8];`
449			`if (BlockAddr%512 !=0)`
450			`$display("**Block Misalign Error");`
451			`end`
452			`else begin`
453			`response_CMD[127:96] <= CardStatus;`
454			`$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;`
455			`$display("**Error Try to blockwrite when No Free Writebuffer") ;`
456			`end`
457			`end`
458			`else begin`
459			`response_S <= 0;`
460			`response_CMD[127:96] <= 0;`
461			`end`
462			`end`
463
464			`end`
465	79	tac2	`33 : response_CMD[127:96] <= 48;`
466			`55 :`
467			`begin`
468			`response_CMD[127:96] <= CardStatus ;`
469			`CardStatus[5] <=1; //Next CMD is AP specific CMD`
470			`appendCrc<=1;`
471			`end`
472			`41 :`
473			`begin`
474			`if (cardIdentificationState) begin`
475			`if (lastCMD != 55 && outDelayCnt==0) begin`
476			`$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;`
477	96	tac2	`$display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;`
478	79	tac2	`CardStatus[3]<=1;`
479			`end`
480			`else begin`
481			`responseType=3;`
482			`response_CMD[127:96] <= OCR;`
483			`appendCrc<=0;`
484			`CardStatus[5] <=0;`
485			`if (Busy==1)`
486			`CardStatus[12:9] <=1;`
487			`end`
488			`end`
489			`end`
490
491			`endcase`
492			`ValidCmd<=1;`
493			`crcIn<=0;`
494
495			`outDelayCnt<=outDelayCnt+1;`
496			if (outDelayCnt==`outDelay)
497			`crcRst<=1;`
498			`oeCmd<=1;`
499			`cmdOut<=1;`
500			`response_CMD[135:134] <=0;`

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