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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_cmd_phy.v] - Blame information for rev 10

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`include "SD_defines.v"
//-------------------------
//-------------------------
module sd_cmd_phy (
input sd_clk,
input rst,
input  cmd_dat_i,
output reg cmd_dat_o,
output reg cmd_oe_o,
 
output  [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input  [1:2] fifo_full,
input [1:2] fifo_empty,
output  [1:0]  start_dat_t,
output fifo_acces_token
 
);
//---------------Input ports---------------
 `define WRITE_CMD 32'h18
`define READ_CMD 32'h11
reg [6:0] Response_Size;
`ifdef SIM
 `define INIT_DELAY 64
`else
  `define INIT_DELAY 64
 `endif
 
 `define tx_cmd_fifo_empty fifo_empty [1]
 
parameter SEND_SIZE = 48;
parameter CONTENT_SIZE = 40;
parameter NCR = 2 ;
 
`define Vector_Index_Write  (CONTENT_SIZE-1-cmd_flow_cnt_write)
`define Bit_Nr_Write  (SEND_SIZE-cmd_flow_cnt_write)
//FSM
parameter SIZE = 5;
parameter
INIT          = 5'b00001,
IDLE          = 5'b00010,
WRITE         = 5'b00100,
BUFFER_WRITE  = 5'b01000,
READ          = 5'b10000;
 
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
reg [1:0] start_dat_t_read;
reg [1:0] start_dat_t_write;
 
reg [39:0] in_buffer;
reg [2:0] read_byte_cnt;
//
reg [7:0] cmd_flow_cnt_write;
reg [7:0] cmd_flow_cnt_read;
 
reg cmd_dat_internal;
//
reg big_resp;
 
reg  crc_rst_write;
reg  crc_en_write;
reg  crc_in_write;
wire [6:0] crc_val_write;
 
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
 
reg  crc_rst_read;
reg  crc_en_read;
reg  crc_in_read;
wire [6:0] crc_val_read;
 
reg crc_buffering_write;
reg block_write;
reg block_read;
 
reg in_buff_ptr;
reg out_buff_ptr;
reg [2:0] read_index_cnt;
reg  [7:0] in_buff_0;
reg  [7:0] in_buff_1;
reg [6:0] crc_in_buff;
reg [7:0] response_status;
reg [6:0] index_check;
 
reg add_token_read;
 
CRC_7 CRC_7_WRITE(
.BITVAL (crc_in_write),
.Enable (crc_en_write),
.CLK (sd_clk),
.RST (crc_rst_write),
.CRC (crc_val_write));
 
 
CRC_7 CRC_7_READ(
.BITVAL (crc_in_read),
.Enable (crc_en_read),
.CLK (sd_clk),
.RST (crc_rst_read),
.CRC (crc_val_read));
 
 
 
always @ (posedge sd_clk or posedge rst )
begin
        if  (rst) begin
 
                cmd_dat_internal <=1'b1;
        end
        else begin
                cmd_dat_internal<=cmd_dat_i;
        end
 
 
end
 
always @ (state or cmd_flow_cnt_write or cmd_dat_internal or `tx_cmd_fifo_empty or read_byte_cnt or cmd_flow_cnt_write or cmd_flow_cnt_read )
 
begin : FSM_COMBO
 next_state  = 0;
case(state)
INIT: begin
  if (cmd_flow_cnt_write >= `INIT_DELAY )begin
     next_state = IDLE;
  end
  else begin
     next_state = INIT;
  end
end
IDLE: begin
    if (!`tx_cmd_fifo_empty)
      next_state =BUFFER_WRITE;
    else if (!cmd_dat_internal)
      next_state =READ;
    else
      next_state =IDLE;
 
 
end
BUFFER_WRITE: begin
  if (read_byte_cnt>=5)
   next_state = WRITE;
  else
   next_state =BUFFER_WRITE;
end
 
WRITE : begin
     if (cmd_flow_cnt_write >= SEND_SIZE)
        next_state = IDLE;
      else
        next_state = WRITE;
 
end
READ : begin
      if (cmd_flow_cnt_read >= Response_Size+7)
        next_state = IDLE;
      else
        next_state = READ;
 
end
 
 
default : next_state  = INIT;
 
 endcase
end
 
 
always @ (posedge sd_clk or posedge rst  )
begin : FSM_SEQ
  if (rst ) begin
    state <= #1 INIT;
 end
 else begin
    state <= #1 next_state;
 end
end
reg fifo_acces_read,fifo_acces_write;
assign fifo_acces_token = fifo_acces_read | fifo_acces_write;
assign sd_adr_o = add_token_read ? sd_adr_o_read : sd_adr_o_write;
assign start_dat_t = add_token_read ?  start_dat_t_read : start_dat_t_write;
reg tx_cmd_fifo_empty_tmp;
 
 
always @ (negedge sd_clk or posedge rst  )
begin : OUTPUT_LOGIC
 if (rst  ) begin
   crc_in_write=0;
   crc_en_write=0;
   crc_rst_write=0;
   fifo_acces_write=0;
   cmd_oe_o=1;
   cmd_dat_o = 1;
   crc_buffering_write=0;
   sd_re_o<=0;
   read_byte_cnt<=0;
   block_read<=0;
   sd_adr_o_write<=0;
   cmd_flow_cnt_write=0;
   start_dat_t_write<=0;
   in_buffer<=0;
    tx_cmd_fifo_empty_tmp<=0;
    Response_Size<=40;
 end
 else begin
  case(state)
    INIT : begin
      cmd_flow_cnt_write=cmd_flow_cnt_write+1;
      cmd_oe_o=1;
      cmd_dat_o = 1;
      crc_buffering_write=0;
      start_dat_t_write<=0;
    end
    IDLE: begin
       cmd_flow_cnt_write=0;
       cmd_oe_o=0;
      // cmd_dat_o = 0; 
       start_dat_t_write<=0;
       crc_in_write=0;
       crc_en_write=0;
       crc_rst_write=1;
       read_byte_cnt<=0;
       block_read<=0;
       fifo_acces_write=0;
       in_buffer<=0;
    end
     BUFFER_WRITE : begin
      sd_re_o<=0;
      fifo_acces_write=1;
      tx_cmd_fifo_empty_tmp<=`tx_cmd_fifo_empty;
       if (!tx_cmd_fifo_empty_tmp) begin
        if(sd_re_o)
          read_byte_cnt <= read_byte_cnt+1;
        sd_adr_o_write <=0;
        sd_re_o<=1;
       if(sd_re_o) begin
         case (read_byte_cnt) //If data is Avaible next cycle?
          0: in_buffer[39:32] <=sd_dat_i;
          1: in_buffer[31:24] <=sd_dat_i;
          2: in_buffer[23:16] <=sd_dat_i;
           3: in_buffer[15:8] <=sd_dat_i;
           4: in_buffer[7:0] <=sd_dat_i;
         endcase
         if (in_buffer[39])
           Response_Size<=127;
         else
           Response_Size<=40;
 
         if (in_buffer[37:32] == `READ_CMD)
               block_read<=1;
      end
 
    end
   end
    WRITE: begin
       sd_re_o<=0;
       cmd_oe_o=1;
       cmd_dat_o = 1;
       crc_en_write =0;
       crc_rst_write=0;
        crc_en_write=1;
 
 
      if (crc_buffering_write==1)  begin
        cmd_oe_o =1;
        if (`Bit_Nr_Write > 8 ) begin  // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
                                   if (cmd_flow_cnt_write==0)
                                    cmd_dat_o = 0;
                                   else
                                    cmd_dat_o = in_buffer[`Vector_Index_Write];
 
                                   if (`Bit_Nr_Write > 9 ) begin //1 step ahead
                               crc_in_write = in_buffer[`Vector_Index_Write-1];
                             end else begin
                               crc_en_write=0;
                                   end
                          end
                          else if ( (`Bit_Nr_Write <=8) && (`Bit_Nr_Write >=2) ) begin
                                  crc_en_write=0;
                                  cmd_dat_o = crc_val_write[(`Bit_Nr_Write)-2];
                                   if (block_read)
             start_dat_t_write<=2'b10;
 
                          end
                          else begin
                                  cmd_dat_o =1'b1;
 
                          end
                         cmd_flow_cnt_write=cmd_flow_cnt_write+1;
                end
 
          else begin //Pre load CRC
                    crc_buffering_write=1;
 
                  crc_in_write = 0;
          end
 
 
 
    end
 
  endcase
 end
end
 
always @ (posedge sd_clk or posedge rst  )
begin
  if (rst) begin
   crc_rst_read=1;
   crc_en_read=0;
   crc_in_read=0;
   cmd_flow_cnt_read=0;
   response_status =0;
   block_write=0;
   index_check=0;
   in_buff_ptr=0;
   out_buff_ptr=0;
   sd_adr_o_read<=0;
   add_token_read=0;
   in_buff_0<=0;
   in_buff_1<=0;
   read_index_cnt=0;
    fifo_acces_read=0;
    sd_dat_o<=0;
    start_dat_t_read<=0;
    sd_we_o<=0;
    crc_in_buff=0;
  end
  else begin
   case (state)
   IDLE : begin
        crc_en_read=0;
        crc_rst_read=1;
        cmd_flow_cnt_read=1;
        index_check=0;
        block_write=0;
        in_buff_ptr=0;
        out_buff_ptr=0;
        add_token_read=0;
        read_index_cnt=0;
        sd_we_o<=0;
        add_token_read=0;
         fifo_acces_read=0;
         start_dat_t_read<=0;
   end
   READ : begin
      fifo_acces_read=1;
      add_token_read=1; //Takes command over addres
      crc_en_read=1;
      crc_rst_read=0;
      sd_we_o<=0;
     if (in_buff_ptr != out_buff_ptr) begin
     sd_adr_o_read <=1;
     sd_we_o<=1;
       if (in_buff_ptr)
        sd_dat_o <=in_buff_0;
      else
        sd_dat_o <=in_buff_1;
 
     out_buff_ptr=out_buff_ptr+1;
     end
 
     if (cmd_flow_cnt_read < (Response_Size))begin //40 First Bits         
        crc_in_read = cmd_dat_internal;
        if (cmd_flow_cnt_read<8 ) begin //1+1+6 (S,T,Index)          
 
          index_check[7-cmd_flow_cnt_read] = cmd_dat_internal;
          if (index_check[5:0] == `WRITE_CMD) begin
             block_write=1;
          end
        end
        else begin
          if (!in_buff_ptr) begin
             in_buff_0[7-read_index_cnt]<=cmd_dat_internal;
          end
          else begin
             in_buff_1[7-read_index_cnt]<=cmd_dat_internal;
          end
          read_index_cnt=read_index_cnt+1;
          if (read_index_cnt==0)
             in_buff_ptr=in_buff_ptr+1;
        end
       end
        else if ( cmd_flow_cnt_read - Response_Size <=6 ) begin //7-Crc Bit
                          crc_in_buff [(Response_Size+6)-(cmd_flow_cnt_read)] = cmd_dat_internal;
                          crc_en_read=0;
      end
      else begin  //Commpare CRC read with calcualted.
                           if ((crc_in_buff != crc_val_read)) begin
                                   response_status[0]=1;
                        end
                        else begin
                          response_status[0]=0;
                        end
                        sd_adr_o_read <=1;
                         sd_we_o<=1;
                        sd_dat_o<=response_status;
 
                     if (block_write)
                          start_dat_t_read<=2'b01;
 
      end
 
       cmd_flow_cnt_read = cmd_flow_cnt_read+1;
   end
 
 
 
 
  endcase
  end
 
end
 
 
 
 
 
 
 
endmodule
 
 
 

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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_cmd_phy.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	6	tac2	`include "SD_defines.v"
2			`//-------------------------`
3			`//-------------------------`
4			`module sd_cmd_phy (`
5			`input sd_clk,`
6			`input rst,`
7			`input cmd_dat_i,`
8			`output reg cmd_dat_o,`
9			`output reg cmd_oe_o,`
10
11			`output [1:0] sd_adr_o,`
12			`input [7:0] sd_dat_i,`
13			`output reg [7:0] sd_dat_o,`
14			`output reg sd_we_o,`
15			`output reg sd_re_o,`
16			`input [1:2] fifo_full,`
17			`input [1:2] fifo_empty,`
18			`output [1:0] start_dat_t,`
19			`output fifo_acces_token`
20
21			`);`
22			`//---------------Input ports---------------`
23			`define WRITE_CMD 32'h18
24			`define READ_CMD 32'h11
25			`reg [6:0] Response_Size;`
26			`ifdef SIM
27			`define INIT_DELAY 64
28			`else
29			`define INIT_DELAY 64
30			`endif
31
32			`define tx_cmd_fifo_empty fifo_empty [1]
33
34			`parameter SEND_SIZE = 48;`
35			`parameter CONTENT_SIZE = 40;`
36			`parameter NCR = 2 ;`
37
38			`define Vector_Index_Write (CONTENT_SIZE-1-cmd_flow_cnt_write)
39			`define Bit_Nr_Write (SEND_SIZE-cmd_flow_cnt_write)
40			`//FSM`
41			`parameter SIZE = 5;`
42			`parameter`
43			`INIT = 5'b00001,`
44			`IDLE = 5'b00010,`
45			`WRITE = 5'b00100,`
46			`BUFFER_WRITE = 5'b01000,`
47			`READ = 5'b10000;`
48
49			`reg [SIZE-1:0] state;`
50			`reg [SIZE-1:0] next_state;`
51
52			`reg [1:0] start_dat_t_read;`
53			`reg [1:0] start_dat_t_write;`
54
55			`reg [39:0] in_buffer;`
56			`reg [2:0] read_byte_cnt;`
57			`//`
58			`reg [7:0] cmd_flow_cnt_write;`
59			`reg [7:0] cmd_flow_cnt_read;`
60
61			`reg cmd_dat_internal;`
62			`//`
63			`reg big_resp;`
64
65			`reg crc_rst_write;`
66			`reg crc_en_write;`
67			`reg crc_in_write;`
68			`wire [6:0] crc_val_write;`
69
70			`reg [1:0] sd_adr_o_read;`
71			`reg [1:0] sd_adr_o_write;`
72
73			`reg crc_rst_read;`
74			`reg crc_en_read;`
75			`reg crc_in_read;`
76			`wire [6:0] crc_val_read;`
77
78			`reg crc_buffering_write;`
79			`reg block_write;`
80			`reg block_read;`
81
82			`reg in_buff_ptr;`
83			`reg out_buff_ptr;`
84			`reg [2:0] read_index_cnt;`
85			`reg [7:0] in_buff_0;`
86			`reg [7:0] in_buff_1;`
87			`reg [6:0] crc_in_buff;`
88			`reg [7:0] response_status;`
89			`reg [6:0] index_check;`
90
91			`reg add_token_read;`
92
93			`CRC_7 CRC_7_WRITE(`
94			`.BITVAL (crc_in_write),`
95			`.Enable (crc_en_write),`
96			`.CLK (sd_clk),`
97			`.RST (crc_rst_write),`
98			`.CRC (crc_val_write));`
99
100
101			`CRC_7 CRC_7_READ(`
102			`.BITVAL (crc_in_read),`
103			`.Enable (crc_en_read),`
104			`.CLK (sd_clk),`
105			`.RST (crc_rst_read),`
106			`.CRC (crc_val_read));`
107
108
109
110			`always @ (posedge sd_clk or posedge rst )`
111			`begin`
112			`if (rst) begin`
113
114			`cmd_dat_internal <=1'b1;`
115			`end`
116			`else begin`
117			`cmd_dat_internal<=cmd_dat_i;`
118			`end`
119
120
121			`end`
122
123			always @ (state or cmd_flow_cnt_write or cmd_dat_internal or `tx_cmd_fifo_empty or read_byte_cnt or cmd_flow_cnt_write or cmd_flow_cnt_read )
124
125			`begin : FSM_COMBO`
126			`next_state = 0;`
127			`case(state)`
128			`INIT: begin`
129			if (cmd_flow_cnt_write >= `INIT_DELAY )begin
130			`next_state = IDLE;`
131			`end`
132			`else begin`
133			`next_state = INIT;`
134			`end`
135			`end`
136			`IDLE: begin`
137			if (!`tx_cmd_fifo_empty)
138			`next_state =BUFFER_WRITE;`
139			`else if (!cmd_dat_internal)`
140			`next_state =READ;`
141			`else`
142			`next_state =IDLE;`
143
144
145			`end`
146			`BUFFER_WRITE: begin`
147			`if (read_byte_cnt>=5)`
148			`next_state = WRITE;`
149			`else`
150			`next_state =BUFFER_WRITE;`
151			`end`
152
153			`WRITE : begin`
154			`if (cmd_flow_cnt_write >= SEND_SIZE)`
155			`next_state = IDLE;`
156			`else`
157			`next_state = WRITE;`
158
159			`end`
160			`READ : begin`
161			`if (cmd_flow_cnt_read >= Response_Size+7)`
162			`next_state = IDLE;`
163			`else`
164			`next_state = READ;`
165
166			`end`
167
168
169			`default : next_state = INIT;`
170
171			`endcase`
172			`end`
173
174
175			`always @ (posedge sd_clk or posedge rst )`
176			`begin : FSM_SEQ`
177			`if (rst ) begin`
178			`state <= #1 INIT;`
179			`end`
180			`else begin`
181			`state <= #1 next_state;`
182			`end`
183			`end`
184			`reg fifo_acces_read,fifo_acces_write;`
185			`assign fifo_acces_token = fifo_acces_read \| fifo_acces_write;`
186			`assign sd_adr_o = add_token_read ? sd_adr_o_read : sd_adr_o_write;`
187			`assign start_dat_t = add_token_read ? start_dat_t_read : start_dat_t_write;`
188			`reg tx_cmd_fifo_empty_tmp;`
189
190
191			`always @ (negedge sd_clk or posedge rst )`
192			`begin : OUTPUT_LOGIC`
193			`if (rst ) begin`
194			`crc_in_write=0;`
195			`crc_en_write=0;`
196			`crc_rst_write=0;`
197			`fifo_acces_write=0;`
198			`cmd_oe_o=1;`
199			`cmd_dat_o = 1;`
200			`crc_buffering_write=0;`
201			`sd_re_o<=0;`
202			`read_byte_cnt<=0;`
203			`block_read<=0;`
204			`sd_adr_o_write<=0;`
205			`cmd_flow_cnt_write=0;`
206			`start_dat_t_write<=0;`
207			`in_buffer<=0;`
208			`tx_cmd_fifo_empty_tmp<=0;`
209			`Response_Size<=40;`
210			`end`
211			`else begin`
212			`case(state)`
213			`INIT : begin`
214			`cmd_flow_cnt_write=cmd_flow_cnt_write+1;`
215			`cmd_oe_o=1;`
216			`cmd_dat_o = 1;`
217			`crc_buffering_write=0;`
218			`start_dat_t_write<=0;`
219			`end`
220			`IDLE: begin`
221			`cmd_flow_cnt_write=0;`
222			`cmd_oe_o=0;`
223			`// cmd_dat_o = 0;`
224			`start_dat_t_write<=0;`
225			`crc_in_write=0;`
226			`crc_en_write=0;`
227			`crc_rst_write=1;`
228			`read_byte_cnt<=0;`
229			`block_read<=0;`
230			`fifo_acces_write=0;`
231			`in_buffer<=0;`
232			`end`
233			`BUFFER_WRITE : begin`
234			`sd_re_o<=0;`
235			`fifo_acces_write=1;`
236			tx_cmd_fifo_empty_tmp<=`tx_cmd_fifo_empty;
237			`if (!tx_cmd_fifo_empty_tmp) begin`
238			`if(sd_re_o)`
239			`read_byte_cnt <= read_byte_cnt+1;`
240			`sd_adr_o_write <=0;`
241			`sd_re_o<=1;`
242			`if(sd_re_o) begin`
243			`case (read_byte_cnt) //If data is Avaible next cycle?`
244			`0: in_buffer[39:32] <=sd_dat_i;`
245			`1: in_buffer[31:24] <=sd_dat_i;`
246			`2: in_buffer[23:16] <=sd_dat_i;`
247			`3: in_buffer[15:8] <=sd_dat_i;`
248			`4: in_buffer[7:0] <=sd_dat_i;`
249			`endcase`
250			`if (in_buffer[39])`
251			`Response_Size<=127;`
252			`else`
253			`Response_Size<=40;`
254
255			if (in_buffer[37:32] == `READ_CMD)
256			`block_read<=1;`
257			`end`
258
259			`end`
260			`end`
261			`WRITE: begin`
262			`sd_re_o<=0;`
263			`cmd_oe_o=1;`
264			`cmd_dat_o = 1;`
265			`crc_en_write =0;`
266			`crc_rst_write=0;`
267			`crc_en_write=1;`
268
269
270			`if (crc_buffering_write==1) begin`
271			`cmd_oe_o =1;`
272			if (`Bit_Nr_Write > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
273			`if (cmd_flow_cnt_write==0)`
274			`cmd_dat_o = 0;`
275			`else`
276			cmd_dat_o = in_buffer[`Vector_Index_Write];
277
278			if (`Bit_Nr_Write > 9 ) begin //1 step ahead
279			crc_in_write = in_buffer[`Vector_Index_Write-1];
280			`end else begin`
281			`crc_en_write=0;`
282			`end`
283			`end`
284			else if ( (`Bit_Nr_Write <=8) && (`Bit_Nr_Write >=2) ) begin
285			`crc_en_write=0;`
286			cmd_dat_o = crc_val_write[(`Bit_Nr_Write)-2];
287			`if (block_read)`
288			`start_dat_t_write<=2'b10;`
289
290			`end`
291			`else begin`
292			`cmd_dat_o =1'b1;`
293
294			`end`
295			`cmd_flow_cnt_write=cmd_flow_cnt_write+1;`
296			`end`
297
298			`else begin //Pre load CRC`
299			`crc_buffering_write=1;`
300
301			`crc_in_write = 0;`
302			`end`
303
304
305
306			`end`
307
308			`endcase`
309			`end`
310			`end`
311
312			`always @ (posedge sd_clk or posedge rst )`
313			`begin`
314			`if (rst) begin`
315			`crc_rst_read=1;`
316			`crc_en_read=0;`
317			`crc_in_read=0;`
318			`cmd_flow_cnt_read=0;`
319			`response_status =0;`
320			`block_write=0;`
321			`index_check=0;`
322			`in_buff_ptr=0;`
323			`out_buff_ptr=0;`
324			`sd_adr_o_read<=0;`
325			`add_token_read=0;`
326			`in_buff_0<=0;`
327			`in_buff_1<=0;`
328			`read_index_cnt=0;`
329			`fifo_acces_read=0;`
330			`sd_dat_o<=0;`
331			`start_dat_t_read<=0;`
332			`sd_we_o<=0;`
333			`crc_in_buff=0;`
334			`end`
335			`else begin`
336			`case (state)`
337			`IDLE : begin`
338			`crc_en_read=0;`
339			`crc_rst_read=1;`
340			`cmd_flow_cnt_read=1;`
341			`index_check=0;`
342			`block_write=0;`
343			`in_buff_ptr=0;`
344			`out_buff_ptr=0;`
345			`add_token_read=0;`
346			`read_index_cnt=0;`
347			`sd_we_o<=0;`
348			`add_token_read=0;`
349			`fifo_acces_read=0;`
350			`start_dat_t_read<=0;`
351			`end`
352			`READ : begin`
353			`fifo_acces_read=1;`
354			`add_token_read=1; //Takes command over addres`
355			`crc_en_read=1;`
356			`crc_rst_read=0;`
357			`sd_we_o<=0;`
358			`if (in_buff_ptr != out_buff_ptr) begin`
359			`sd_adr_o_read <=1;`
360			`sd_we_o<=1;`
361			`if (in_buff_ptr)`
362			`sd_dat_o <=in_buff_0;`
363			`else`
364			`sd_dat_o <=in_buff_1;`
365
366			`out_buff_ptr=out_buff_ptr+1;`
367			`end`
368
369			`if (cmd_flow_cnt_read < (Response_Size))begin //40 First Bits`
370			`crc_in_read = cmd_dat_internal;`
371			`if (cmd_flow_cnt_read<8 ) begin //1+1+6 (S,T,Index)`
372
373			`index_check[7-cmd_flow_cnt_read] = cmd_dat_internal;`
374			if (index_check[5:0] == `WRITE_CMD) begin
375			`block_write=1;`
376			`end`
377			`end`
378			`else begin`
379			`if (!in_buff_ptr) begin`
380			`in_buff_0[7-read_index_cnt]<=cmd_dat_internal;`
381			`end`
382			`else begin`
383			`in_buff_1[7-read_index_cnt]<=cmd_dat_internal;`
384			`end`
385			`read_index_cnt=read_index_cnt+1;`
386			`if (read_index_cnt==0)`
387			`in_buff_ptr=in_buff_ptr+1;`
388			`end`
389			`end`
390			`else if ( cmd_flow_cnt_read - Response_Size <=6 ) begin //7-Crc Bit`
391			`crc_in_buff [(Response_Size+6)-(cmd_flow_cnt_read)] = cmd_dat_internal;`
392			`crc_en_read=0;`
393			`end`
394			`else begin //Commpare CRC read with calcualted.`
395			`if ((crc_in_buff != crc_val_read)) begin`
396			`response_status[0]=1;`
397			`end`
398			`else begin`
399			`response_status[0]=0;`
400			`end`
401			`sd_adr_o_read <=1;`
402			`sd_we_o<=1;`
403			`sd_dat_o<=response_status;`
404
405			`if (block_write)`
406			`start_dat_t_read<=2'b01;`
407
408			`end`
409
410			`cmd_flow_cnt_read = cmd_flow_cnt_read+1;`
411			`end`
412
413
414
415
416			`endcase`
417			`end`
418
419			`end`
420
421
422
423
424
425
426
427			`endmodule`
428
429
430