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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_controller_fifo_actel.v] - Blame information for rev 90

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module sd_controller_fifo_wba
(
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
  sd_cmd_dat_i,sd_cmd_out_o,  sd_cmd_oe_o,
  sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
);
input           wb_clk_i;
input           wb_rst_i;
input   [7:0]  wb_dat_i;
output  [7:0]  wb_dat_o;
input   [2:0]  wb_adr_i;
input    [3:0]  wb_sel_i;
input           wb_we_i;
input           wb_cyc_i;
input           wb_stb_i;
output reg          wb_ack_o;
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
wire sd_clk_i;
input sd_clk_i_pad;
reg [7:0] controll_reg;
reg [7:0] status_reg;
reg [7:0] command_timeout_reg;
  assign sd_clk_i = wb_clk_i;
assign sd_clk_o=sd_clk_i;
reg [1:0] wb_fifo_adr_i_writer;
reg [1:0] wb_fifo_adr_i_reader;
wire [1:0] wb_fifo_adr_i;
reg add_token_read;
wire [7:0] wb_fifo_dat_i;
wire [7:0] wb_fifo_dat_o;
reg [7:0]  wb_dat_i_storage;
reg [7:0] wb_dat_o_i;
reg time_enable;
assign sd_clk_o_pad  = sd_clk_i ;
assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;
assign wb_fifo_dat_i =wb_dat_i_storage;
assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o :   wb_dat_o_i ;
wire [1:4]fifo_full ;
wire [1:4]fifo_empty;
reg wb_fifo_we_i;
reg wb_fifo_re_i;
wire [1:0] sd_adr_o;
wire [7:0] sd_dat_o;
wire [7:0] sd_dat_i;
sd_fifo sd_fifo_0
(
   .wb_adr_i  (wb_fifo_adr_i ),
   .wb_dat_i  (wb_fifo_dat_i),
   .wb_dat_o  (wb_fifo_dat_o ),
   .wb_we_i   (wb_fifo_we_i),
   .wb_re_i   (wb_fifo_re_i),
   .wb_clk  (wb_clk_i),
   .sd_adr_i (sd_adr_o ),
   .sd_dat_i (sd_dat_o),
   .sd_dat_o (sd_dat_i ),
   .sd_we_i (sd_we_o),
   .sd_re_i (sd_re_o),
   .sd_clk (sd_clk_o),
   .fifo_full ( fifo_full ),
   .fifo_empty (fifo_empty    ),
   .rst (wb_rst_i)
  ) ;
wire [1:0] sd_adr_o_cmd;
wire [7:0] sd_dat_i_cmd;
wire [7:0] sd_dat_o_cmd;
wire [1:0] sd_adr_o_dat;
wire [7:0] sd_dat_i_dat;
wire [7:0] sd_dat_o_dat;
wire [1:0] st_dat_t;
sd_cmd_phy sdc_cmd_phy_0
(
  .sd_clk (sd_clk_o),
  .rst (wb_rst_i ),
  .cmd_dat_i ( sd_cmd_dat_i  ),
  .cmd_dat_o (sd_cmd_out_o   ),
  .cmd_oe_o (sd_cmd_oe_o   ),
  .sd_adr_o (sd_adr_o_cmd),
  .sd_dat_i (sd_dat_i_cmd),
  .sd_dat_o (sd_dat_o_cmd),
  .sd_we_o (sd_we_o_cmd),
  .sd_re_o (sd_re_o_cmd),
  .fifo_full ( fifo_full[1:2] ),
  .fifo_empty ( fifo_empty [1:2]),
  .start_dat_t (st_dat_t),
  .fifo_acces_token (fifo_acces_token)
  );
  sd_data_phy sd_data_phy_0 (
  .sd_clk (sd_clk_o),
  .rst (wb_rst_i | controll_reg[0]),
  .DAT_oe_o ( sd_dat_oe_o  ),
  .DAT_dat_o (sd_dat_out_o),
  .DAT_dat_i  (sd_dat_dat_i ),
  .sd_adr_o (sd_adr_o_dat   ),
  .sd_dat_i (sd_dat_i_dat  ),
  .sd_dat_o (sd_dat_o_dat  ),
  .sd_we_o  (sd_we_o_dat),
  .sd_re_o (sd_re_o_dat),
  .fifo_full ( fifo_full[3:4] ),
  .fifo_empty ( fifo_empty [3:4]),
  .start_dat (st_dat_t),
  .fifo_acces (~fifo_acces_token)
  );
  assign sd_adr_o =  fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;
  assign sd_dat_o =  fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;
  assign sd_we_o  = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;
  assign sd_re_o  =  fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;
 assign sd_dat_i_dat = sd_dat_i;
 assign sd_dat_i_cmd = sd_dat_i;
  always @(posedge wb_clk_i or posedge wb_rst_i)
        begin
        if (wb_rst_i)
            status_reg<=0;
          else begin
      status_reg[0] <= fifo_full[1];
      status_reg[1] <= fifo_empty[2];
      status_reg[2] <=  fifo_full[3];
      status_reg[3] <=  fifo_empty[4];
    end
  end
  reg delayed_ack;
  always @(posedge wb_clk_i or posedge wb_rst_i)
        begin
          if (wb_rst_i)
            wb_ack_o <=0;
           else
             wb_ack_o <=wb_stb_i & wb_cyc_i &  ~wb_ack_o & delayed_ack;
        end
  always @(posedge wb_clk_i or posedge wb_rst_i)
        begin
    if ( wb_rst_i )begin
            command_timeout_reg<=255;
            wb_dat_i_storage<=0;
            controll_reg<=0;
            wb_fifo_we_i<=0;
            wb_fifo_adr_i_writer<=0;
            time_enable<=0;
          end
          else if (wb_stb_i  & wb_cyc_i & (~wb_ack_o))begin
            if (wb_we_i) begin
              case (wb_adr_i)
              4'h0 : begin
                wb_fifo_adr_i_writer<=0;
                wb_fifo_we_i<=1&!delayed_ack;
                wb_dat_i_storage<=wb_dat_i;
                command_timeout_reg<=255;
                time_enable<=1;
              end
        4'h2 : begin
                wb_fifo_adr_i_writer<=2;
                wb_fifo_we_i<=1&!delayed_ack;
                wb_dat_i_storage<=wb_dat_i;
                command_timeout_reg<=255;
                time_enable<=0;
              end
        4'h5 : controll_reg <= wb_dat_i;
              endcase
            end
           end
           else begin
              wb_fifo_we_i<=0;
             if (!status_reg[1])
               time_enable<=0;
             if ((command_timeout_reg!=0) && (time_enable))
                 command_timeout_reg<=command_timeout_reg-1;
           end
end
always @(posedge wb_clk_i or posedge wb_rst_i )begin
   if ( wb_rst_i) begin
     add_token_read<=0;
     delayed_ack<=0;
     wb_fifo_re_i<=0;
      wb_fifo_adr_i_reader<=0;
      wb_dat_o_i<=0;
  end
 else begin
    delayed_ack<=0;
    wb_fifo_re_i<=0;
   if (wb_stb_i  & wb_cyc_i & (~wb_ack_o)) begin
   delayed_ack<=delayed_ack+1;
    add_token_read<=0;
    if (!wb_we_i) begin
      case (wb_adr_i)
      4'h1 : begin
         add_token_read<=1;
         wb_fifo_adr_i_reader<=1;
              wb_fifo_re_i<=1&delayed_ack;
      end
      4'h3 :begin
         add_token_read<=1;
         wb_fifo_adr_i_reader<=3;
               wb_fifo_re_i<=1 & delayed_ack;
     end
      4'h4 : wb_dat_o_i <= status_reg;
      4'h6 : wb_dat_o_i <= command_timeout_reg;
     endcase
    end
  end
end
end
 assign m_wb_adr_o =0;
 assign m_wb_sel_o =0;
 assign m_wb_we_o=0;
 assign m_wb_dat_o =0;
 assign m_wb_cyc_o=0;
 assign m_wb_stb_o=0;
 assign m_wb_cti_o=0;
 assign m_wb_bte_o=0;
endmodule
module sd_counter
  (
    output reg [9:1] q,
    output [9:1]    q_bin,
    input cke,
    input clk,
    input rst
   );
   reg [9:1] qi;
   wire [9:1] q_next;
   assign q_next =
   qi + 9'd1;
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= 9'd0;
     else
   if (cke)
     qi <= q_next;
   always @ (posedge clk or posedge rst)
     if (rst)
       q <= 9'd0;
     else
       if (cke)
         q <= (q_next>>1) ^ q_next;
   assign q_bin = qi;
endmodule
module CRC_7(BITVAL, Enable, CLK, RST, CRC);
   input        BITVAL;
   input Enable;
   input        CLK;
   input        RST;
   output [6:0] CRC;
   reg    [6:0] CRC;
   wire         inv;
   assign inv = BITVAL ^ CRC[6];
    always @(posedge CLK or posedge RST) begin
                if (RST) begin
                        CRC = 0;
        end
                else begin
                        if (Enable==1) begin
                                CRC[6] = CRC[5];
                                CRC[5] = CRC[4];
                                CRC[4] = CRC[3];
                                CRC[3] = CRC[2] ^ inv;
                                CRC[2] = CRC[1];
                                CRC[1] = CRC[0];
                                CRC[0] = inv;
                        end
                end
     end
endmodule
module CRC_16(BITVAL, Enable, CLK, RST, CRC);
 input        BITVAL;
   input Enable;
   input        CLK;
   input        RST;
   output reg [15:0] CRC;
   wire         inv;
   assign inv = BITVAL ^ CRC[15];
  always @(posedge CLK or posedge RST) begin
                if (RST) begin
                        CRC = 0;
        end
      else begin
        if (Enable==1) begin
         CRC[15] = CRC[14];
         CRC[14] = CRC[13];
         CRC[13] = CRC[12];
         CRC[12] = CRC[11] ^ inv;
         CRC[11] = CRC[10];
         CRC[10] = CRC[9];
         CRC[9] = CRC[8];
         CRC[8] = CRC[7];
         CRC[7] = CRC[6];
         CRC[6] = CRC[5];
         CRC[5] = CRC[4] ^ inv;
         CRC[4] = CRC[3];
         CRC[3] = CRC[2];
         CRC[2] = CRC[1];
         CRC[1] = CRC[0];
         CRC[0] = inv;
        end
         end
      end
endmodule
module sd_data_phy(
input sd_clk,
input rst,
output reg DAT_oe_o,
output reg[3:0] DAT_dat_o,
input  [3:0] DAT_dat_i,
output  [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input  [3:4] fifo_full,
input [3:4] fifo_empty,
input  [1:0] start_dat,
input fifo_acces
);
 reg [5:0] in_buff_ptr_read;
 reg [5:0] out_buff_ptr_read;
 reg crc_ok;
 reg [3:0] last_din_read;
reg [7:0] tmp_crc_token ;
reg[2:0] crc_read_count;
reg [3:0] crc_in_write;
reg crc_en_write;
reg crc_rst_write;
wire [15:0] crc_out_write [3:0];
reg [3:0] crc_in_read;
reg crc_en_read;
reg crc_rst_read;
wire [15:0] crc_out_read [3:0];
  reg[7:0] next_out;
    reg data_read_index;
reg [10:0] transf_cnt_write;
reg [10:0] transf_cnt_read;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE        = 6'b000001;
parameter WRITE_DAT   = 6'b000010;
parameter READ_CRC   = 6'b000100;
parameter WRITE_CRC  = 6'b001000;
parameter  READ_WAIT = 6'b010000;
parameter  READ_DAT  = 6'b100000;
reg in_dat_buffer_empty;
reg [2:0] crc_status_token;
reg busy_int;
reg add_token;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
  CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
end
endgenerate
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
  CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
end
endgenerate
reg q_start_bit;
always @ (state or start_dat or DAT_dat_i[0] or  transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or  in_dat_buffer_empty )
begin : FSM_COMBO
 next_state  = 0;
case(state)
  IDLE: begin
   if (start_dat == 2'b01)
      next_state=WRITE_DAT;
    else if  (start_dat == 2'b10)
      next_state=READ_WAIT;
    else
      next_state=IDLE;
    end
  WRITE_DAT: begin
    if (transf_cnt_write >= 1044+2)
       next_state= READ_CRC;
   else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=WRITE_DAT;
  end
  READ_WAIT: begin
    if (DAT_dat_i[0]== 0 )
       next_state= READ_DAT;
    else
       next_state=READ_WAIT;
  end
  READ_CRC: begin
    if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
       next_state= WRITE_CRC;
    else
       next_state=READ_CRC;
  end
  WRITE_CRC: begin
       next_state= IDLE;
  end
  READ_DAT: begin
    if ((transf_cnt_read >= 1044-3)  && (in_dat_buffer_empty))
       next_state= IDLE;
    else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=READ_DAT;
    end
 endcase
end
always @ (posedge sd_clk or posedge rst   )
 begin
  if (rst ) begin
    q_start_bit<=1;
 end
 else begin
    q_start_bit <= DAT_dat_i[0];
 end
end
always @ (posedge sd_clk or posedge rst   )
begin : FSM_SEQ
  if (rst ) begin
    state <= #1 IDLE;
 end
 else begin
    state <= #1 next_state;
 end
end
reg [4:0] crc_cnt_write;
reg [4:0]crc_cnt_read;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [7:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg data_send_index;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
reg read_byte_cnt;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
reg [3:0] in_dat_buffer [63:0];
always @ (negedge sd_clk or posedge rst   )
begin
if (rst) begin
  DAT_oe_o<=0;
  crc_en_write<=0;
  crc_rst_write<=1;
  transf_cnt_write<=0;
  crc_cnt_write<=15;
  crc_status_token<=7;
  data_send_index<=0;
  out_buff_ptr<=0;
  in_buff_ptr<=0;
  read_byte_cnt<=0;
   write_buf_0<=0;
    write_buf_1<=0;
    sd_re_o<=0;
    sd_data_out<=0;
    sd_adr_o_write<=0;
    crc_in_write<=0;
    DAT_dat_o<=0;
     last_din<=0;
end
else begin
 case(state)
   IDLE: begin
      DAT_oe_o<=0;
      crc_en_write<=0;
      crc_rst_write<=1;
      crc_cnt_write<=16;
      read_byte_cnt<=0;
      crc_status_token<=7;
      data_send_index<=0;
      out_buff_ptr<=0;
      in_buff_ptr<=0;
        sd_re_o<=0;
        transf_cnt_write<=0;
   end
   WRITE_DAT: begin
      transf_cnt_write<=transf_cnt_write+1;
      if ( (in_buff_ptr != out_buff_ptr) ||  (transf_cnt_write<2) ) begin
       read_byte_cnt<=read_byte_cnt+1;
       sd_re_o<=0;
        case (read_byte_cnt)
        0:begin
           sd_adr_o_write <=2;
           sd_re_o<=1;
        end
        1:begin
          if (!in_buff_ptr)
             write_buf_0<=sd_dat_i;
          else
            write_buf_1 <=sd_dat_i;
          in_buff_ptr<=in_buff_ptr+1;
        end
     endcase
     end
      if (!out_buff_ptr)
        sd_data_out<=write_buf_0;
      else
       sd_data_out<=write_buf_1;
        if (transf_cnt_write==1+2) begin
          crc_rst_write<=0;
          crc_en_write<=1;
          last_din <=write_buf_0[3:0];
          DAT_oe_o<=1;
          DAT_dat_o<=0;
          crc_in_write<= write_buf_0[3:0];
          data_send_index<=1;
          out_buff_ptr<=out_buff_ptr+1;
        end
        else if ( (transf_cnt_write>=2+2) && (transf_cnt_write<=1044-19+2 )) begin
          DAT_oe_o<=1;
        case (data_send_index)
           0:begin
              last_din <=sd_data_out[3:0];
              crc_in_write <=sd_data_out[3:0];
               out_buff_ptr<=out_buff_ptr+1;
           end
           1:begin
              last_din <=sd_data_out[7:4];
              crc_in_write <=sd_data_out[7:4];
           end
         endcase
          data_send_index<=data_send_index+1;
          DAT_dat_o<= last_din;
        if ( transf_cnt_write >=1044-19 +2) begin
             crc_en_write<=0;
         end
       end
       else if (transf_cnt_write>1044-19 +2 & crc_cnt_write!=0) begin
         crc_en_write<=0;
         crc_cnt_write<=crc_cnt_write-1;
         DAT_oe_o<=1;
         DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
         DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
         DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
         DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
       end
       else if (transf_cnt_write==1044-2+2) begin
          DAT_oe_o<=1;
          DAT_dat_o<=4'b1111;
      end
      else if (transf_cnt_write !=0) begin
         DAT_oe_o<=0;
      end
   end
 endcase
end
end
always @ (posedge sd_clk or posedge rst   )
begin
  if (rst) begin
    add_token<=0;
    sd_adr_o_read<=0;
    crc_read_count<=0;
    sd_we_o<=0;
    tmp_crc_token<=0;
    crc_rst_read<=0;
    crc_en_read<=0;
    in_buff_ptr_read<=0;
    out_buff_ptr_read<=0;
    crc_cnt_read<=0;
    transf_cnt_read<=0;
    data_read_index<=0;
    in_dat_buffer_empty<=0;
    next_out<=0;
    busy_int<=0;
    sd_dat_o<=0;
  end
  else begin
   case(state)
   IDLE: begin
     add_token<=0;
     crc_read_count<=0;
     sd_we_o<=0;
     tmp_crc_token<=0;
      crc_rst_read<=1;
      crc_en_read<=0;
      in_buff_ptr_read<=0;
     out_buff_ptr_read<=0;
      crc_cnt_read<=15;
      transf_cnt_read<=0;
      data_read_index<=0;
      in_dat_buffer_empty<=0;
    end
    READ_DAT: begin
     add_token<=1;
      crc_rst_read<=0;
      crc_en_read<=1;
      if (fifo_acces) begin
        if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
          data_read_index<=~data_read_index;
          case(data_read_index)
            0: begin
             sd_adr_o_read<=3;
             sd_we_o<=0;
             next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
             next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
           end
           1: begin
              out_buff_ptr_read<=out_buff_ptr_read+2;
            sd_dat_o<=next_out;
            sd_we_o<=1;
            end
          endcase
          end
        else
           in_dat_buffer_empty<=1;
      end
     if (transf_cnt_read<1024) begin
       in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
       crc_in_read<=DAT_dat_i;
       crc_ok<=1;
       transf_cnt_read<=transf_cnt_read+1;
       in_buff_ptr_read<=in_buff_ptr_read+1;
     end
     else if  ( transf_cnt_read <= (1024 +16)) begin
       transf_cnt_read<=transf_cnt_read+1;
       crc_en_read<=0;
       last_din_read <=DAT_dat_i;
       if (transf_cnt_read> 1024) begin
         crc_cnt_read <=crc_cnt_read-1;
          if  (crc_out_read[0][crc_cnt_read] != last_din[0])
           crc_ok<=0;
          if  (crc_out_read[1][crc_cnt_read] != last_din[1])
           crc_ok<=0;
          if  (crc_out_read[2][crc_cnt_read] != last_din[2])
           crc_ok<=0;
          if  (crc_out_read[3][crc_cnt_read] != last_din[3])
           crc_ok<=0;
         if (crc_cnt_read==0) begin
         end
      end
    end
    end
    READ_CRC: begin
       if (crc_read_count<3'b111) begin
         crc_read_count<=crc_read_count+1;
         tmp_crc_token[crc_read_count]  <= DAT_dat_i[0];
        end
      busy_int <=DAT_dat_i[0];
    end
    WRITE_CRC: begin
      add_token<=1;
      sd_adr_o_read<=3;
      sd_we_o<=1;
      sd_dat_o<=tmp_crc_token;
    end
  endcase
end
end
endmodule

Line No.	Rev	Author	Line
1	35	tac2	`module sd_controller_fifo_wba`
2			`(`
3			`wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,`
4			`wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,`
5			`sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o,`
6			`sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad`
7			`);`
8			`input wb_clk_i;`
9			`input wb_rst_i;`
10			`input [7:0] wb_dat_i;`
11			`output [7:0] wb_dat_o;`
12			`input [2:0] wb_adr_i;`
13			`input [3:0] wb_sel_i;`
14			`input wb_we_i;`
15			`input wb_cyc_i;`
16			`input wb_stb_i;`
17			`output reg wb_ack_o;`
18			`input wire [3:0] sd_dat_dat_i;`
19			`output wire [3:0] sd_dat_out_o;`
20			`output wire sd_dat_oe_o;`
21			`input wire sd_cmd_dat_i;`
22			`output wire sd_cmd_out_o;`
23			`output wire sd_cmd_oe_o;`
24			`output sd_clk_o_pad;`
25			`wire sd_clk_i;`
26			`input sd_clk_i_pad;`
27			`reg [7:0] controll_reg;`
28			`reg [7:0] status_reg;`
29			`reg [7:0] command_timeout_reg;`
30			`assign sd_clk_i = wb_clk_i;`
31			`assign sd_clk_o=sd_clk_i;`
32			`reg [1:0] wb_fifo_adr_i_writer;`
33			`reg [1:0] wb_fifo_adr_i_reader;`
34			`wire [1:0] wb_fifo_adr_i;`
35			`reg add_token_read;`
36			`wire [7:0] wb_fifo_dat_i;`
37			`wire [7:0] wb_fifo_dat_o;`
38			`reg [7:0] wb_dat_i_storage;`
39			`reg [7:0] wb_dat_o_i;`
40			`reg time_enable;`
41			`assign sd_clk_o_pad = sd_clk_i ;`
42			`assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;`
43			`assign wb_fifo_dat_i =wb_dat_i_storage;`
44			`assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ;`
45			`wire [1:4]fifo_full ;`
46			`wire [1:4]fifo_empty;`
47			`reg wb_fifo_we_i;`
48			`reg wb_fifo_re_i;`
49			`wire [1:0] sd_adr_o;`
50			`wire [7:0] sd_dat_o;`
51			`wire [7:0] sd_dat_i;`
52			`sd_fifo sd_fifo_0`
53			`(`
54			`.wb_adr_i (wb_fifo_adr_i ),`
55			`.wb_dat_i (wb_fifo_dat_i),`
56			`.wb_dat_o (wb_fifo_dat_o ),`
57			`.wb_we_i (wb_fifo_we_i),`
58			`.wb_re_i (wb_fifo_re_i),`
59			`.wb_clk (wb_clk_i),`
60			`.sd_adr_i (sd_adr_o ),`
61			`.sd_dat_i (sd_dat_o),`
62			`.sd_dat_o (sd_dat_i ),`
63			`.sd_we_i (sd_we_o),`
64			`.sd_re_i (sd_re_o),`
65			`.sd_clk (sd_clk_o),`
66			`.fifo_full ( fifo_full ),`
67			`.fifo_empty (fifo_empty ),`
68			`.rst (wb_rst_i)`
69			`) ;`
70			`wire [1:0] sd_adr_o_cmd;`
71			`wire [7:0] sd_dat_i_cmd;`
72			`wire [7:0] sd_dat_o_cmd;`
73			`wire [1:0] sd_adr_o_dat;`
74			`wire [7:0] sd_dat_i_dat;`
75			`wire [7:0] sd_dat_o_dat;`
76			`wire [1:0] st_dat_t;`
77			`sd_cmd_phy sdc_cmd_phy_0`
78			`(`
79			`.sd_clk (sd_clk_o),`
80			`.rst (wb_rst_i ),`
81			`.cmd_dat_i ( sd_cmd_dat_i ),`
82			`.cmd_dat_o (sd_cmd_out_o ),`
83			`.cmd_oe_o (sd_cmd_oe_o ),`
84			`.sd_adr_o (sd_adr_o_cmd),`
85			`.sd_dat_i (sd_dat_i_cmd),`
86			`.sd_dat_o (sd_dat_o_cmd),`
87			`.sd_we_o (sd_we_o_cmd),`
88			`.sd_re_o (sd_re_o_cmd),`
89			`.fifo_full ( fifo_full[1:2] ),`
90			`.fifo_empty ( fifo_empty [1:2]),`
91			`.start_dat_t (st_dat_t),`
92			`.fifo_acces_token (fifo_acces_token)`
93			`);`
94			`sd_data_phy sd_data_phy_0 (`
95			`.sd_clk (sd_clk_o),`
96			`.rst (wb_rst_i \| controll_reg[0]),`
97			`.DAT_oe_o ( sd_dat_oe_o ),`
98			`.DAT_dat_o (sd_dat_out_o),`
99			`.DAT_dat_i (sd_dat_dat_i ),`
100			`.sd_adr_o (sd_adr_o_dat ),`
101			`.sd_dat_i (sd_dat_i_dat ),`
102			`.sd_dat_o (sd_dat_o_dat ),`
103			`.sd_we_o (sd_we_o_dat),`
104			`.sd_re_o (sd_re_o_dat),`
105			`.fifo_full ( fifo_full[3:4] ),`
106			`.fifo_empty ( fifo_empty [3:4]),`
107			`.start_dat (st_dat_t),`
108			`.fifo_acces (~fifo_acces_token)`
109			`);`
110			`assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;`
111			`assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;`
112			`assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;`
113			`assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;`
114			`assign sd_dat_i_dat = sd_dat_i;`
115			`assign sd_dat_i_cmd = sd_dat_i;`
116			`always @(posedge wb_clk_i or posedge wb_rst_i)`
117			`begin`
118			`if (wb_rst_i)`
119			`status_reg<=0;`
120			`else begin`
121			`status_reg[0] <= fifo_full[1];`
122			`status_reg[1] <= fifo_empty[2];`
123			`status_reg[2] <= fifo_full[3];`
124			`status_reg[3] <= fifo_empty[4];`
125			`end`
126			`end`
127			`reg delayed_ack;`
128			`always @(posedge wb_clk_i or posedge wb_rst_i)`
129			`begin`
130			`if (wb_rst_i)`
131			`wb_ack_o <=0;`
132			`else`
133			`wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack;`
134			`end`
135			`always @(posedge wb_clk_i or posedge wb_rst_i)`
136			`begin`
137			`if ( wb_rst_i )begin`
138			`command_timeout_reg<=255;`
139			`wb_dat_i_storage<=0;`
140			`controll_reg<=0;`
141			`wb_fifo_we_i<=0;`
142			`wb_fifo_adr_i_writer<=0;`
143			`time_enable<=0;`
144			`end`
145			`else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin`
146			`if (wb_we_i) begin`
147			`case (wb_adr_i)`
148			`4'h0 : begin`
149			`wb_fifo_adr_i_writer<=0;`
150			`wb_fifo_we_i<=1&!delayed_ack;`
151			`wb_dat_i_storage<=wb_dat_i;`
152			`command_timeout_reg<=255;`
153			`time_enable<=1;`
154			`end`
155			`4'h2 : begin`
156			`wb_fifo_adr_i_writer<=2;`
157			`wb_fifo_we_i<=1&!delayed_ack;`
158			`wb_dat_i_storage<=wb_dat_i;`
159			`command_timeout_reg<=255;`
160			`time_enable<=0;`
161			`end`
162			`4'h5 : controll_reg <= wb_dat_i;`
163			`endcase`
164			`end`
165			`end`
166			`else begin`
167			`wb_fifo_we_i<=0;`
168			`if (!status_reg[1])`
169			`time_enable<=0;`
170			`if ((command_timeout_reg!=0) && (time_enable))`
171			`command_timeout_reg<=command_timeout_reg-1;`
172			`end`
173			`end`
174			`always @(posedge wb_clk_i or posedge wb_rst_i )begin`
175			`if ( wb_rst_i) begin`
176			`add_token_read<=0;`
177			`delayed_ack<=0;`
178			`wb_fifo_re_i<=0;`
179			`wb_fifo_adr_i_reader<=0;`
180			`wb_dat_o_i<=0;`
181			`end`
182			`else begin`
183			`delayed_ack<=0;`
184			`wb_fifo_re_i<=0;`
185			`if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin`
186			`delayed_ack<=delayed_ack+1;`
187			`add_token_read<=0;`
188			`if (!wb_we_i) begin`
189			`case (wb_adr_i)`
190			`4'h1 : begin`
191			`add_token_read<=1;`
192			`wb_fifo_adr_i_reader<=1;`
193			`wb_fifo_re_i<=1&delayed_ack;`
194			`end`
195			`4'h3 :begin`
196			`add_token_read<=1;`
197			`wb_fifo_adr_i_reader<=3;`
198			`wb_fifo_re_i<=1 & delayed_ack;`
199			`end`
200			`4'h4 : wb_dat_o_i <= status_reg;`
201			`4'h6 : wb_dat_o_i <= command_timeout_reg;`
202			`endcase`
203			`end`
204			`end`
205			`end`
206			`end`
207			`assign m_wb_adr_o =0;`
208			`assign m_wb_sel_o =0;`
209			`assign m_wb_we_o=0;`
210			`assign m_wb_dat_o =0;`
211			`assign m_wb_cyc_o=0;`
212			`assign m_wb_stb_o=0;`
213			`assign m_wb_cti_o=0;`
214			`assign m_wb_bte_o=0;`
215			`endmodule`
216			`module sd_counter`
217			`(`
218			`output reg [9:1] q,`
219			`output [9:1] q_bin,`
220			`input cke,`
221			`input clk,`
222			`input rst`
223			`);`
224			`reg [9:1] qi;`
225			`wire [9:1] q_next;`
226			`assign q_next =`
227			`qi + 9'd1;`
228			`always @ (posedge clk or posedge rst)`
229			`if (rst)`
230			`qi <= 9'd0;`
231			`else`
232			`if (cke)`
233			`qi <= q_next;`
234			`always @ (posedge clk or posedge rst)`
235			`if (rst)`
236			`q <= 9'd0;`
237			`else`
238			`if (cke)`
239			`q <= (q_next>>1) ^ q_next;`
240			`assign q_bin = qi;`
241			`endmodule`
242			`module CRC_7(BITVAL, Enable, CLK, RST, CRC);`
243			`input BITVAL;`
244			`input Enable;`
245			`input CLK;`
246			`input RST;`
247			`output [6:0] CRC;`
248			`reg [6:0] CRC;`
249			`wire inv;`
250			`assign inv = BITVAL ^ CRC[6];`
251			`always @(posedge CLK or posedge RST) begin`
252			`if (RST) begin`
253			`CRC = 0;`
254			`end`
255			`else begin`
256			`if (Enable==1) begin`
257			`CRC[6] = CRC[5];`
258			`CRC[5] = CRC[4];`
259			`CRC[4] = CRC[3];`
260			`CRC[3] = CRC[2] ^ inv;`
261			`CRC[2] = CRC[1];`
262			`CRC[1] = CRC[0];`
263			`CRC[0] = inv;`
264			`end`
265			`end`
266			`end`
267			`endmodule`
268			`module CRC_16(BITVAL, Enable, CLK, RST, CRC);`
269			`input BITVAL;`
270			`input Enable;`
271			`input CLK;`
272			`input RST;`
273			`output reg [15:0] CRC;`
274			`wire inv;`
275			`assign inv = BITVAL ^ CRC[15];`
276			`always @(posedge CLK or posedge RST) begin`
277			`if (RST) begin`
278			`CRC = 0;`
279			`end`
280			`else begin`
281			`if (Enable==1) begin`
282			`CRC[15] = CRC[14];`
283			`CRC[14] = CRC[13];`
284			`CRC[13] = CRC[12];`
285			`CRC[12] = CRC[11] ^ inv;`
286			`CRC[11] = CRC[10];`
287			`CRC[10] = CRC[9];`
288			`CRC[9] = CRC[8];`
289			`CRC[8] = CRC[7];`
290			`CRC[7] = CRC[6];`
291			`CRC[6] = CRC[5];`
292			`CRC[5] = CRC[4] ^ inv;`
293			`CRC[4] = CRC[3];`
294			`CRC[3] = CRC[2];`
295			`CRC[2] = CRC[1];`
296			`CRC[1] = CRC[0];`
297			`CRC[0] = inv;`
298			`end`
299			`end`
300			`end`
301			`endmodule`
302			`module sd_data_phy(`
303			`input sd_clk,`
304			`input rst,`
305			`output reg DAT_oe_o,`
306			`output reg[3:0] DAT_dat_o,`
307			`input [3:0] DAT_dat_i,`
308			`output [1:0] sd_adr_o,`
309			`input [7:0] sd_dat_i,`
310			`output reg [7:0] sd_dat_o,`
311			`output reg sd_we_o,`
312			`output reg sd_re_o,`
313			`input [3:4] fifo_full,`
314			`input [3:4] fifo_empty,`
315			`input [1:0] start_dat,`
316			`input fifo_acces`
317			`);`
318			`reg [5:0] in_buff_ptr_read;`
319			`reg [5:0] out_buff_ptr_read;`
320			`reg crc_ok;`
321			`reg [3:0] last_din_read;`
322			`reg [7:0] tmp_crc_token ;`
323			`reg[2:0] crc_read_count;`
324			`reg [3:0] crc_in_write;`
325			`reg crc_en_write;`
326			`reg crc_rst_write;`
327			`wire [15:0] crc_out_write [3:0];`
328			`reg [3:0] crc_in_read;`
329			`reg crc_en_read;`
330			`reg crc_rst_read;`
331			`wire [15:0] crc_out_read [3:0];`
332			`reg[7:0] next_out;`
333			`reg data_read_index;`
334			`reg [10:0] transf_cnt_write;`
335			`reg [10:0] transf_cnt_read;`
336			`parameter SIZE = 6;`
337			`reg [SIZE-1:0] state;`
338			`reg [SIZE-1:0] next_state;`
339			`parameter IDLE = 6'b000001;`
340			`parameter WRITE_DAT = 6'b000010;`
341			`parameter READ_CRC = 6'b000100;`
342			`parameter WRITE_CRC = 6'b001000;`
343			`parameter READ_WAIT = 6'b010000;`
344			`parameter READ_DAT = 6'b100000;`
345			`reg in_dat_buffer_empty;`
346			`reg [2:0] crc_status_token;`
347			`reg busy_int;`
348			`reg add_token;`
349			`genvar i;`
350			`generate`
351			`for(i=0; i<4; i=i+1) begin:CRC_16_gen_write`
352			`CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);`
353			`end`
354			`endgenerate`
355			`generate`
356			`for(i=0; i<4; i=i+1) begin:CRC_16_gen_read`
357			`CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);`
358			`end`
359			`endgenerate`
360			`reg q_start_bit;`
361			`always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )`
362			`begin : FSM_COMBO`
363			`next_state = 0;`
364			`case(state)`
365			`IDLE: begin`
366			`if (start_dat == 2'b01)`
367			`next_state=WRITE_DAT;`
368			`else if (start_dat == 2'b10)`
369			`next_state=READ_WAIT;`
370			`else`
371			`next_state=IDLE;`
372			`end`
373			`WRITE_DAT: begin`
374			`if (transf_cnt_write >= 1044+2)`
375			`next_state= READ_CRC;`
376			`else if (start_dat == 2'b11)`
377			`next_state=IDLE;`
378			`else`
379			`next_state=WRITE_DAT;`
380			`end`
381			`READ_WAIT: begin`
382			`if (DAT_dat_i[0]== 0 )`
383			`next_state= READ_DAT;`
384			`else`
385			`next_state=READ_WAIT;`
386			`end`
387			`READ_CRC: begin`
388			`if ( (crc_read_count == 3'b111) &&(busy_int ==1) )`
389			`next_state= WRITE_CRC;`
390			`else`
391			`next_state=READ_CRC;`
392			`end`
393			`WRITE_CRC: begin`
394			`next_state= IDLE;`
395			`end`
396			`READ_DAT: begin`
397			`if ((transf_cnt_read >= 1044-3) && (in_dat_buffer_empty))`
398			`next_state= IDLE;`
399			`else if (start_dat == 2'b11)`
400			`next_state=IDLE;`
401			`else`
402			`next_state=READ_DAT;`
403			`end`
404			`endcase`
405			`end`
406			`always @ (posedge sd_clk or posedge rst )`
407			`begin`
408			`if (rst ) begin`
409			`q_start_bit<=1;`
410			`end`
411			`else begin`
412			`q_start_bit <= DAT_dat_i[0];`
413			`end`
414			`end`
415			`always @ (posedge sd_clk or posedge rst )`
416			`begin : FSM_SEQ`
417			`if (rst ) begin`
418			`state <= #1 IDLE;`
419			`end`
420			`else begin`
421			`state <= #1 next_state;`
422			`end`
423			`end`
424			`reg [4:0] crc_cnt_write;`
425			`reg [4:0]crc_cnt_read;`
426			`reg [3:0] last_din;`
427			`reg [2:0] crc_s ;`
428			`reg [7:0] write_buf_0,write_buf_1, sd_data_out;`
429			`reg out_buff_ptr,in_buff_ptr;`
430			`reg data_send_index;`
431			`reg [1:0] sd_adr_o_read;`
432			`reg [1:0] sd_adr_o_write;`
433			`reg read_byte_cnt;`
434			`assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;`
435			`assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;`
436			`reg [3:0] in_dat_buffer [63:0];`
437			`always @ (negedge sd_clk or posedge rst )`
438			`begin`
439			`if (rst) begin`
440			`DAT_oe_o<=0;`
441			`crc_en_write<=0;`
442			`crc_rst_write<=1;`
443			`transf_cnt_write<=0;`
444			`crc_cnt_write<=15;`
445			`crc_status_token<=7;`
446			`data_send_index<=0;`
447			`out_buff_ptr<=0;`
448			`in_buff_ptr<=0;`
449			`read_byte_cnt<=0;`
450			`write_buf_0<=0;`
451			`write_buf_1<=0;`
452			`sd_re_o<=0;`
453			`sd_data_out<=0;`
454			`sd_adr_o_write<=0;`
455			`crc_in_write<=0;`
456			`DAT_dat_o<=0;`
457			`last_din<=0;`
458			`end`
459			`else begin`
460			`case(state)`
461			`IDLE: begin`
462			`DAT_oe_o<=0;`
463			`crc_en_write<=0;`
464			`crc_rst_write<=1;`
465			`crc_cnt_write<=16;`
466			`read_byte_cnt<=0;`
467			`crc_status_token<=7;`
468			`data_send_index<=0;`
469			`out_buff_ptr<=0;`
470			`in_buff_ptr<=0;`
471			`sd_re_o<=0;`
472			`transf_cnt_write<=0;`
473			`end`
474			`WRITE_DAT: begin`
475			`transf_cnt_write<=transf_cnt_write+1;`
476			`if ( (in_buff_ptr != out_buff_ptr) \|\| (transf_cnt_write<2) ) begin`
477			`read_byte_cnt<=read_byte_cnt+1;`
478			`sd_re_o<=0;`
479			`case (read_byte_cnt)`
480			`0:begin`
481			`sd_adr_o_write <=2;`
482			`sd_re_o<=1;`
483			`end`
484			`1:begin`
485			`if (!in_buff_ptr)`
486			`write_buf_0<=sd_dat_i;`
487			`else`
488			`write_buf_1 <=sd_dat_i;`
489			`in_buff_ptr<=in_buff_ptr+1;`
490			`end`
491			`endcase`
492			`end`
493			`if (!out_buff_ptr)`
494			`sd_data_out<=write_buf_0;`
495			`else`
496			`sd_data_out<=write_buf_1;`
497			`if (transf_cnt_write==1+2) begin`
498			`crc_rst_write<=0;`
499			`crc_en_write<=1;`
500			`last_din <=write_buf_0[3:0];`

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