OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_controller_fifo_wb.v] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 36 tac2
`include "sd_defines.v"
2
 
3
module sd_controller_fifo_wba
4
(
5
 
6
 
7
  // WISHBONE common
8
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
9
 
10
  // WISHBONE slave
11
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
12
 
13
    // WISHBONE master
14
 
15
  //SD BUS
16
  sd_cmd_dat_i,sd_cmd_out_o,  sd_cmd_oe_o,
17
  sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
18
  //PLL CLK_IN
19
   `ifdef SD_CLK_EXT
20
    ,sd_clk_i_pad
21
   `endif
22
 
23
 
24
);
25
input           wb_clk_i;     // WISHBONE clock
26
input           wb_rst_i;     // WISHBONE reset
27
input   [7:0]  wb_dat_i;     // WISHBONE data input
28
output  [7:0]  wb_dat_o;     // WISHBONE data output
29
     // WISHBONE error output
30
 
31
// WISHBONE slave
32
input   [2:0]  wb_adr_i;     // WISHBONE address input
33
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
34
input           wb_we_i;      // WISHBONE write enable input
35
input           wb_cyc_i;     // WISHBONE cycle input
36
input           wb_stb_i;     // WISHBONE strobe input
37
 
38
output reg          wb_ack_o;     // WISHBONE acknowledge output
39
 
40
// WISHBONE master
41
 
42
 
43
input wire [3:0] sd_dat_dat_i;
44
output wire [3:0] sd_dat_out_o;
45
output wire sd_dat_oe_o;
46
 
47
input wire sd_cmd_dat_i;
48
output wire sd_cmd_out_o;
49
output wire sd_cmd_oe_o;
50
 
51
output sd_clk_o_pad;
52
wire sd_clk_i;
53
input sd_clk_i_pad;
54
 
55
`define tx_cmd_fifo 4'h0
56
`define rx_cmd_fifo 4'h1
57
`define tx_data_fifo 4'h2
58
`define rx_data_fifo 4'h3
59
`define status 4'h4
60
`define controll 4'h5
61
`define timer 4'h6
62
 
63
reg [7:0] controll_reg;
64
reg [7:0] status_reg;
65
reg [7:0] command_timeout_reg;
66
 
67
`ifdef SD_CLK_BUS_CLK
68
  assign sd_clk_i = wb_clk_i;
69
`endif
70
 
71
`ifdef SD_CLK_EXT
72
  assign sd_clk_i = sd_clk_i_pad;
73
`endif
74
assign sd_clk_o=sd_clk_i;
75
 
76
reg [1:0] wb_fifo_adr_i_writer;
77
reg [1:0] wb_fifo_adr_i_reader;
78
wire [1:0] wb_fifo_adr_i;
79
reg add_token_read;
80
wire [7:0] wb_fifo_dat_i;
81
wire [7:0] wb_fifo_dat_o;
82
reg [7:0]  wb_dat_i_storage;
83
reg [7:0] wb_dat_o_i;
84
reg time_enable;
85
assign sd_clk_o_pad  = sd_clk_i ;
86
 
87
 
88
assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;
89
assign wb_fifo_dat_i =wb_dat_i_storage;
90
assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o :   wb_dat_o_i ;
91
 
92
 
93
 
94
wire [1:4]fifo_full ;
95
wire [1:4]fifo_empty;
96
reg wb_fifo_we_i;
97
reg wb_fifo_re_i;
98
wire [1:0] sd_adr_o;
99
wire [7:0] sd_dat_o;
100
wire [7:0] sd_dat_i;
101
sd_fifo sd_fifo_0
102
(
103
   .wb_adr_i  (wb_fifo_adr_i ),
104
   .wb_dat_i  (wb_fifo_dat_i),
105
   .wb_dat_o  (wb_fifo_dat_o ),
106
   .wb_we_i   (wb_fifo_we_i),
107
   .wb_re_i   (wb_fifo_re_i),
108
   .wb_clk  (wb_clk_i),
109
   .sd_adr_i (sd_adr_o ),
110
   .sd_dat_i (sd_dat_o),
111
   .sd_dat_o (sd_dat_i ),
112
   .sd_we_i (sd_we_o),
113
   .sd_re_i (sd_re_o),
114
   .sd_clk (sd_clk_o),
115
   .fifo_full ( fifo_full ),
116
   .fifo_empty (fifo_empty    ),
117
   .rst (wb_rst_i) // | controll_reg[0])
118
  ) ;
119
 
120
wire [1:0] sd_adr_o_cmd;
121
wire [7:0] sd_dat_i_cmd;
122
wire [7:0] sd_dat_o_cmd;
123
 
124
wire [1:0] sd_adr_o_dat;
125
wire [7:0] sd_dat_i_dat;
126
wire [7:0] sd_dat_o_dat;
127
wire [1:0] st_dat_t;
128
sd_cmd_phy sdc_cmd_phy_0
129
(
130
  .sd_clk (sd_clk_o),
131
  .rst (wb_rst_i ),//| controll_reg[0]),
132
  .cmd_dat_i ( sd_cmd_dat_i  ),
133
  .cmd_dat_o (sd_cmd_out_o   ),
134
  .cmd_oe_o (sd_cmd_oe_o   ),
135
  .sd_adr_o (sd_adr_o_cmd),
136
  .sd_dat_i (sd_dat_i_cmd),
137
  .sd_dat_o (sd_dat_o_cmd),
138
  .sd_we_o (sd_we_o_cmd),
139
  .sd_re_o (sd_re_o_cmd),
140
  .fifo_full ( fifo_full[1:2] ),
141
  .fifo_empty ( fifo_empty [1:2]),
142
  .start_dat_t (st_dat_t),
143
  .fifo_acces_token (fifo_acces_token)
144
  );
145
 
146
 
147
  sd_data_phy sd_data_phy_0 (
148
  .sd_clk (sd_clk_o),
149
  .rst (wb_rst_i | controll_reg[0]),
150
  .DAT_oe_o ( sd_dat_oe_o  ),
151
  .DAT_dat_o (sd_dat_out_o),
152
  .DAT_dat_i  (sd_dat_dat_i ),
153
  .sd_adr_o (sd_adr_o_dat   ),
154
  .sd_dat_i (sd_dat_i_dat  ),
155
  .sd_dat_o (sd_dat_o_dat  ),
156
  .sd_we_o  (sd_we_o_dat),
157
  .sd_re_o (sd_re_o_dat),
158
  .fifo_full ( fifo_full[3:4] ),
159
  .fifo_empty ( fifo_empty [3:4]),
160
  .start_dat (st_dat_t),
161
  .fifo_acces (~fifo_acces_token)
162
  );
163
 
164
 
165
  assign sd_adr_o =  fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;
166
  assign sd_dat_o =  fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;
167
  assign sd_we_o  = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;
168
  assign sd_re_o  =  fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;
169
 
170
 assign sd_dat_i_dat = sd_dat_i;
171
 assign sd_dat_i_cmd = sd_dat_i;
172
 
173
 
174
  always @(posedge wb_clk_i or posedge wb_rst_i)
175
        begin
176
        if (wb_rst_i)
177
            status_reg<=0;
178
          else begin
179
      status_reg[0] <= fifo_full[1];
180
      status_reg[1] <= fifo_empty[2];
181
      status_reg[2] <=  fifo_full[3];
182
      status_reg[3] <=  fifo_empty[4];
183
    end
184
  end
185
 
186
  reg delayed_ack;
187
  always @(posedge wb_clk_i or posedge wb_rst_i)
188
        begin
189
 
190
          if (wb_rst_i)
191
            wb_ack_o <=0;
192
           else
193
             wb_ack_o <=wb_stb_i & wb_cyc_i &  ~wb_ack_o & delayed_ack;
194
 
195
        end
196
 
197
  always @(posedge wb_clk_i or posedge wb_rst_i)
198
        begin
199
 
200
 
201
    if ( wb_rst_i )begin
202
            command_timeout_reg<=`TIME_OUT_TIME;
203
            wb_dat_i_storage<=0;
204
            controll_reg<=0;
205
 
206
            wb_fifo_we_i<=0;
207
            wb_fifo_adr_i_writer<=0;
208
            time_enable<=0;
209
          end
210
          else if (wb_stb_i  & wb_cyc_i & (~wb_ack_o))begin //CS
211
 
212
 
213
            if (wb_we_i) begin
214
              case (wb_adr_i)
215
              `tx_cmd_fifo : begin
216
                wb_fifo_adr_i_writer<=0;
217
                wb_fifo_we_i<=1&!delayed_ack;
218
                wb_dat_i_storage<=wb_dat_i;
219
                command_timeout_reg<=`TIME_OUT_TIME;
220
                time_enable<=1;
221
              end
222
        `tx_data_fifo : begin
223
                wb_fifo_adr_i_writer<=2;
224
                wb_fifo_we_i<=1&!delayed_ack;
225
                wb_dat_i_storage<=wb_dat_i;
226
                command_timeout_reg<=`TIME_OUT_TIME;
227
                time_enable<=0;
228
              end
229
        `controll : controll_reg <= wb_dat_i;
230
              endcase
231
            end
232
           end
233
           else begin
234
            //  wb_fifo_adr_i_writer<=0;
235
              wb_fifo_we_i<=0;
236
 
237
             if (!status_reg[1])
238
               time_enable<=0;
239
 
240
             if ((command_timeout_reg!=0) && (time_enable))
241
                 command_timeout_reg<=command_timeout_reg-1;
242
           end
243
end
244
 
245
 
246
always @(posedge wb_clk_i or posedge wb_rst_i )begin
247
 
248
 
249
   if ( wb_rst_i) begin
250
     add_token_read<=0;
251
     delayed_ack<=0;
252
     wb_fifo_re_i<=0;
253
      wb_fifo_adr_i_reader<=0;
254
      wb_dat_o_i<=0;
255
  end
256
 else begin
257
    delayed_ack<=0;
258
    wb_fifo_re_i<=0;
259
   if (wb_stb_i  & wb_cyc_i & (~wb_ack_o)) begin //C
260
   delayed_ack<=delayed_ack+1;
261
    add_token_read<=0;
262
    if (!wb_we_i) begin
263
 
264
      case (wb_adr_i)
265
      `rx_cmd_fifo : begin
266
 
267
         add_token_read<=1;
268
         wb_fifo_adr_i_reader<=1;
269
              wb_fifo_re_i<=1&delayed_ack;
270
 
271
      end
272
      `rx_data_fifo :begin
273
         add_token_read<=1;
274
         wb_fifo_adr_i_reader<=3;
275
               wb_fifo_re_i<=1 & delayed_ack;
276
 
277
     end
278
      `status : wb_dat_o_i <= status_reg;
279
      `timer : wb_dat_o_i <= command_timeout_reg;
280
 
281
 
282
     endcase
283
    end
284
  end
285
end
286
end
287
 
288
 
289
//just to get rid of warnings....
290
 assign m_wb_adr_o =0;
291
 assign m_wb_sel_o =0;
292
 assign m_wb_we_o=0;
293
 assign m_wb_dat_o =0;
294
 
295
 assign m_wb_cyc_o=0;
296
 assign m_wb_stb_o=0;
297
 assign m_wb_cti_o=0;
298
 assign m_wb_bte_o=0;
299
 
300
 
301
 
302
endmodule
303
 
304
 
305
 
306
 
307
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.