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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_data_phy.v] - Blame information for rev 10

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//-------------------------
//-------------------------
 
 
 
 
`include "SD_defines.v"
`define BUFFER_OFFSET 2
 
module sd_data_phy(
input sd_clk,
input rst,
output reg DAT_oe_o,
output reg[3:0] DAT_dat_o,
input  [3:0] DAT_dat_i,
 
output  [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input  [3:4] fifo_full,
input [3:4] fifo_empty,
input  [1:0] start_dat,
input fifo_acces
 
);
 reg [5:0] in_buff_ptr_read;
 reg [5:0] out_buff_ptr_read;
 reg crc_ok;
 reg [3:0] last_din_read;
 
 
 
reg [7:0] tmp_crc_token ;
reg[2:0] crc_read_count;
 
//CRC16 
reg [3:0] crc_in_write;
reg crc_en_write;
reg crc_rst_write;
wire [15:0] crc_out_write [3:0];
 
reg [3:0] crc_in_read;
reg crc_en_read;
reg crc_rst_read;
wire [15:0] crc_out_read [3:0];
 
  reg[7:0] next_out;
    reg data_read_index;
 
reg [10:0] transf_cnt_write;
reg [10:0] transf_cnt_read;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE        = 6'b000001;
parameter WRITE_DAT   = 6'b000010;
parameter READ_CRC   = 6'b000100;
parameter WRITE_CRC  = 6'b001000;
parameter  READ_WAIT = 6'b010000;
parameter  READ_DAT  = 6'b100000;
 
reg in_dat_buffer_empty;
reg [2:0] crc_status_token;
reg busy_int;
reg add_token;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
  CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
end
endgenerate
 
 
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
  CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
end
endgenerate
 
 
 
reg q_start_bit;
 
always @ (state or start_dat or DAT_dat_i[0] or  transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or  in_dat_buffer_empty )
begin : FSM_COMBO
 next_state  = 0;
case(state)
  IDLE: begin
   if (start_dat == 2'b01)
      next_state=WRITE_DAT;
    else if  (start_dat == 2'b10)
      next_state=READ_WAIT;
    else
      next_state=IDLE;
    end
  WRITE_DAT: begin
    if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
       next_state= READ_CRC;
   else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=WRITE_DAT;
  end
 
  READ_WAIT: begin
    if (DAT_dat_i[0]== 0 )
       next_state= READ_DAT;
    else
       next_state=READ_WAIT;
  end
 
 
  READ_CRC: begin
    if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
       next_state= WRITE_CRC;
    else
       next_state=READ_CRC;
  end
  WRITE_CRC: begin
 
       next_state= IDLE;
 
  end
 
 
 
  READ_DAT: begin
    if ((transf_cnt_read >= `BIT_BLOCK-3)  && (in_dat_buffer_empty)) //Startbit consumed...
       next_state= IDLE;
    else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=READ_DAT;
    end
 endcase
end
 
always @ (posedge sd_clk or posedge rst   )
 begin
  if (rst ) begin
    q_start_bit<=1;
 end
 else begin
    q_start_bit <= DAT_dat_i[0];
 end
end
 
 
//----------------Seq logic------------
always @ (posedge sd_clk or posedge rst   )
begin : FSM_SEQ
  if (rst ) begin
    state <= #1 IDLE;
 end
 else begin
    state <= #1 next_state;
 end
end
 
reg [4:0] crc_cnt_write;
reg [4:0]crc_cnt_read;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [7:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg data_send_index;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
 
 
reg read_byte_cnt;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
 
 
 
 
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
 
reg [3:0] in_dat_buffer [63:0];
 
always @ (negedge sd_clk or posedge rst   )
begin
if (rst) begin
  DAT_oe_o<=0;
  crc_en_write<=0;
  crc_rst_write<=1;
  transf_cnt_write<=0;
  crc_cnt_write<=15;
  crc_status_token<=7;
 
  data_send_index<=0;
  out_buff_ptr<=0;
  in_buff_ptr<=0;
  read_byte_cnt<=0;
   write_buf_0<=0;
    write_buf_1<=0;
    sd_re_o<=0;
    sd_data_out<=0;
    sd_adr_o_write<=0;
    crc_in_write<=0;
    DAT_dat_o<=0;
     last_din<=0;
end
else begin
 case(state)
   IDLE: begin
      DAT_oe_o<=0;
      crc_en_write<=0;
      crc_rst_write<=1;
      crc_cnt_write<=16;
      read_byte_cnt<=0;
 
      crc_status_token<=7;
      data_send_index<=0;
      out_buff_ptr<=0;
      in_buff_ptr<=0;
        sd_re_o<=0;
        transf_cnt_write<=0;
 
   end
   WRITE_DAT: begin
 
      transf_cnt_write<=transf_cnt_write+1;
 
 
      if ( (in_buff_ptr != out_buff_ptr) ||  (transf_cnt_write<2) ) begin
       read_byte_cnt<=read_byte_cnt+1;
       sd_re_o<=0;
        case (read_byte_cnt)
        0:begin
           sd_adr_o_write <=2;
           sd_re_o<=1;
        end
        1:begin
          if (!in_buff_ptr)
             write_buf_0<=sd_dat_i;
          else
            write_buf_1 <=sd_dat_i;
          in_buff_ptr<=in_buff_ptr+1;
        end
     endcase
     end
 
      if (!out_buff_ptr)
        sd_data_out<=write_buf_0;
      else
       sd_data_out<=write_buf_1;
 
        if (transf_cnt_write==1+`BUFFER_OFFSET) begin
 
          crc_rst_write<=0;
          crc_en_write<=1;
          last_din <=write_buf_0[3:0];
          DAT_oe_o<=1;
          DAT_dat_o<=0;
          crc_in_write<= write_buf_0[3:0];
          data_send_index<=1;
          out_buff_ptr<=out_buff_ptr+1;
        end
        else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
          DAT_oe_o<=1;
        case (data_send_index)
           0:begin
              last_din <=sd_data_out[3:0];
              crc_in_write <=sd_data_out[3:0];
               out_buff_ptr<=out_buff_ptr+1;
           end
           1:begin
              last_din <=sd_data_out[7:4];
              crc_in_write <=sd_data_out[7:4];
           end
 
         endcase
          data_send_index<=data_send_index+1;
 
          DAT_dat_o<= last_din;
 
        if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
             crc_en_write<=0;
         end
       end
       else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
 
         crc_en_write<=0;
         crc_cnt_write<=crc_cnt_write-1;
         DAT_oe_o<=1;
         DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
         DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
         DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
         DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
       end
       else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
          DAT_oe_o<=1;
          DAT_dat_o<=4'b1111;
 
      end
      else if (transf_cnt_write !=0) begin
         DAT_oe_o<=0;
      end
 
 
   end
 
 
 endcase
end
end
 
 
always @ (posedge sd_clk or posedge rst   )
begin
  if (rst) begin
    add_token<=0;
    sd_adr_o_read<=0;
    crc_read_count<=0;
    sd_we_o<=0;
    tmp_crc_token<=0;
    crc_rst_read<=0;
    crc_en_read<=0;
    in_buff_ptr_read<=0;
    out_buff_ptr_read<=0;
    crc_cnt_read<=0;
    transf_cnt_read<=0;
    data_read_index<=0;
    in_dat_buffer_empty<=0;
 
    next_out<=0;
    busy_int<=0;
    sd_dat_o<=0;
  end
  else begin
   case(state)
   IDLE: begin
     add_token<=0;
     crc_read_count<=0;
     sd_we_o<=0;
     tmp_crc_token<=0;
      crc_rst_read<=1;
      crc_en_read<=0;
      in_buff_ptr_read<=0;
     out_buff_ptr_read<=0;
      crc_cnt_read<=15;
      transf_cnt_read<=0;
      data_read_index<=0;
      in_dat_buffer_empty<=0;
    end
 
    READ_DAT: begin
     add_token<=1;
      crc_rst_read<=0;
      crc_en_read<=1;
 
 
 
      if (fifo_acces) begin
        if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
          data_read_index<=~data_read_index;
          case(data_read_index)
            0: begin
             sd_adr_o_read<=3;
             sd_we_o<=0;
             next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
             next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
           end
           1: begin
              out_buff_ptr_read<=out_buff_ptr_read+2;
            sd_dat_o<=next_out;
            sd_we_o<=1;
            end
          endcase
          end
        else
           in_dat_buffer_empty<=1;
      end
 
     if (transf_cnt_read<`BIT_BLOCK_REC) begin
 
       in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
       crc_in_read<=DAT_dat_i;
       crc_ok<=1;
       transf_cnt_read<=transf_cnt_read+1;
       in_buff_ptr_read<=in_buff_ptr_read+1;
     end
     else if  ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
       transf_cnt_read<=transf_cnt_read+1;
       crc_en_read<=0;
       last_din_read <=DAT_dat_i;
 
       if (transf_cnt_read> `BIT_BLOCK_REC) begin
         crc_cnt_read <=crc_cnt_read-1;
 
 
          if  (crc_out_read[0][crc_cnt_read] != last_din[0])
           crc_ok<=0;
          if  (crc_out_read[1][crc_cnt_read] != last_din[1])
           crc_ok<=0;
          if  (crc_out_read[2][crc_cnt_read] != last_din[2])
           crc_ok<=0;
          if  (crc_out_read[3][crc_cnt_read] != last_din[3])
           crc_ok<=0;
 
         if (crc_cnt_read==0) begin
          //in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok}
         end
      end
    end
 
 
 
    end
    READ_CRC: begin
       if (crc_read_count<3'b111) begin
         crc_read_count<=crc_read_count+1;
         tmp_crc_token[crc_read_count]  <= DAT_dat_i[0];
        end
 
      busy_int <=DAT_dat_i[0];
 
    end
    WRITE_CRC: begin
      add_token<=1;
      sd_adr_o_read<=3;
      sd_we_o<=1;
      sd_dat_o<=tmp_crc_token;
    end
 
  endcase
end
 
end
//Sync
 
 
 
 
 
 
 
endmodule
 
 
 

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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_data_phy.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	6	tac2	`//-------------------------`
2			`//-------------------------`
3
4
5
6
7			`include "SD_defines.v"
8			`define BUFFER_OFFSET 2
9
10			`module sd_data_phy(`
11			`input sd_clk,`
12			`input rst,`
13			`output reg DAT_oe_o,`
14			`output reg[3:0] DAT_dat_o,`
15			`input [3:0] DAT_dat_i,`
16
17			`output [1:0] sd_adr_o,`
18			`input [7:0] sd_dat_i,`
19			`output reg [7:0] sd_dat_o,`
20			`output reg sd_we_o,`
21			`output reg sd_re_o,`
22			`input [3:4] fifo_full,`
23			`input [3:4] fifo_empty,`
24			`input [1:0] start_dat,`
25			`input fifo_acces`
26
27			`);`
28			`reg [5:0] in_buff_ptr_read;`
29			`reg [5:0] out_buff_ptr_read;`
30			`reg crc_ok;`
31			`reg [3:0] last_din_read;`
32
33
34
35			`reg [7:0] tmp_crc_token ;`
36			`reg[2:0] crc_read_count;`
37
38			`//CRC16`
39			`reg [3:0] crc_in_write;`
40			`reg crc_en_write;`
41			`reg crc_rst_write;`
42			`wire [15:0] crc_out_write [3:0];`
43
44			`reg [3:0] crc_in_read;`
45			`reg crc_en_read;`
46			`reg crc_rst_read;`
47			`wire [15:0] crc_out_read [3:0];`
48
49			`reg[7:0] next_out;`
50			`reg data_read_index;`
51
52			`reg [10:0] transf_cnt_write;`
53			`reg [10:0] transf_cnt_read;`
54			`parameter SIZE = 6;`
55			`reg [SIZE-1:0] state;`
56			`reg [SIZE-1:0] next_state;`
57			`parameter IDLE = 6'b000001;`
58			`parameter WRITE_DAT = 6'b000010;`
59			`parameter READ_CRC = 6'b000100;`
60			`parameter WRITE_CRC = 6'b001000;`
61			`parameter READ_WAIT = 6'b010000;`
62			`parameter READ_DAT = 6'b100000;`
63
64			`reg in_dat_buffer_empty;`
65			`reg [2:0] crc_status_token;`
66			`reg busy_int;`
67			`reg add_token;`
68			`genvar i;`
69			`generate`
70			`for(i=0; i<4; i=i+1) begin:CRC_16_gen_write`
71			`CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);`
72			`end`
73			`endgenerate`
74
75
76			`generate`
77			`for(i=0; i<4; i=i+1) begin:CRC_16_gen_read`
78			`CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);`
79			`end`
80			`endgenerate`
81
82
83
84			`reg q_start_bit;`
85
86			`always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )`
87			`begin : FSM_COMBO`
88			`next_state = 0;`
89			`case(state)`
90			`IDLE: begin`
91			`if (start_dat == 2'b01)`
92			`next_state=WRITE_DAT;`
93			`else if (start_dat == 2'b10)`
94			`next_state=READ_WAIT;`
95			`else`
96			`next_state=IDLE;`
97			`end`
98			`WRITE_DAT: begin`
99			if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
100			`next_state= READ_CRC;`
101			`else if (start_dat == 2'b11)`
102			`next_state=IDLE;`
103			`else`
104			`next_state=WRITE_DAT;`
105			`end`
106
107			`READ_WAIT: begin`
108			`if (DAT_dat_i[0]== 0 )`
109			`next_state= READ_DAT;`
110			`else`
111			`next_state=READ_WAIT;`
112			`end`
113
114
115			`READ_CRC: begin`
116			`if ( (crc_read_count == 3'b111) &&(busy_int ==1) )`
117			`next_state= WRITE_CRC;`
118			`else`
119			`next_state=READ_CRC;`
120			`end`
121			`WRITE_CRC: begin`
122
123			`next_state= IDLE;`
124
125			`end`
126
127
128
129			`READ_DAT: begin`
130			if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) //Startbit consumed...
131			`next_state= IDLE;`
132			`else if (start_dat == 2'b11)`
133			`next_state=IDLE;`
134			`else`
135			`next_state=READ_DAT;`
136			`end`
137			`endcase`
138			`end`
139
140			`always @ (posedge sd_clk or posedge rst )`
141			`begin`
142			`if (rst ) begin`
143			`q_start_bit<=1;`
144			`end`
145			`else begin`
146			`q_start_bit <= DAT_dat_i[0];`
147			`end`
148			`end`
149
150
151			`//----------------Seq logic------------`
152			`always @ (posedge sd_clk or posedge rst )`
153			`begin : FSM_SEQ`
154			`if (rst ) begin`
155			`state <= #1 IDLE;`
156			`end`
157			`else begin`
158			`state <= #1 next_state;`
159			`end`
160			`end`
161
162			`reg [4:0] crc_cnt_write;`
163			`reg [4:0]crc_cnt_read;`
164			`reg [3:0] last_din;`
165			`reg [2:0] crc_s ;`
166			`reg [7:0] write_buf_0,write_buf_1, sd_data_out;`
167			`reg out_buff_ptr,in_buff_ptr;`
168			`reg data_send_index;`
169			`reg [1:0] sd_adr_o_read;`
170			`reg [1:0] sd_adr_o_write;`
171
172
173			`reg read_byte_cnt;`
174			`assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;`
175
176
177
178
179			`assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;`
180
181			`reg [3:0] in_dat_buffer [63:0];`
182
183			`always @ (negedge sd_clk or posedge rst )`
184			`begin`
185			`if (rst) begin`
186			`DAT_oe_o<=0;`
187			`crc_en_write<=0;`
188			`crc_rst_write<=1;`
189			`transf_cnt_write<=0;`
190			`crc_cnt_write<=15;`
191			`crc_status_token<=7;`
192
193			`data_send_index<=0;`
194			`out_buff_ptr<=0;`
195			`in_buff_ptr<=0;`
196			`read_byte_cnt<=0;`
197			`write_buf_0<=0;`
198			`write_buf_1<=0;`
199			`sd_re_o<=0;`
200			`sd_data_out<=0;`
201			`sd_adr_o_write<=0;`
202			`crc_in_write<=0;`
203			`DAT_dat_o<=0;`
204			`last_din<=0;`
205			`end`
206			`else begin`
207			`case(state)`
208			`IDLE: begin`
209			`DAT_oe_o<=0;`
210			`crc_en_write<=0;`
211			`crc_rst_write<=1;`
212			`crc_cnt_write<=16;`
213			`read_byte_cnt<=0;`
214
215			`crc_status_token<=7;`
216			`data_send_index<=0;`
217			`out_buff_ptr<=0;`
218			`in_buff_ptr<=0;`
219			`sd_re_o<=0;`
220			`transf_cnt_write<=0;`
221
222			`end`
223			`WRITE_DAT: begin`
224
225			`transf_cnt_write<=transf_cnt_write+1;`
226
227
228			`if ( (in_buff_ptr != out_buff_ptr) \|\| (transf_cnt_write<2) ) begin`
229			`read_byte_cnt<=read_byte_cnt+1;`
230			`sd_re_o<=0;`
231			`case (read_byte_cnt)`
232			`0:begin`
233			`sd_adr_o_write <=2;`
234			`sd_re_o<=1;`
235			`end`
236			`1:begin`
237			`if (!in_buff_ptr)`
238			`write_buf_0<=sd_dat_i;`
239			`else`
240			`write_buf_1 <=sd_dat_i;`
241			`in_buff_ptr<=in_buff_ptr+1;`
242			`end`
243			`endcase`
244			`end`
245
246			`if (!out_buff_ptr)`
247			`sd_data_out<=write_buf_0;`
248			`else`
249			`sd_data_out<=write_buf_1;`
250
251			if (transf_cnt_write==1+`BUFFER_OFFSET) begin
252
253			`crc_rst_write<=0;`
254			`crc_en_write<=1;`
255			`last_din <=write_buf_0[3:0];`
256			`DAT_oe_o<=1;`
257			`DAT_dat_o<=0;`
258			`crc_in_write<= write_buf_0[3:0];`
259			`data_send_index<=1;`
260			`out_buff_ptr<=out_buff_ptr+1;`
261			`end`
262			else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
263			`DAT_oe_o<=1;`
264			`case (data_send_index)`
265			`0:begin`
266			`last_din <=sd_data_out[3:0];`
267			`crc_in_write <=sd_data_out[3:0];`
268			`out_buff_ptr<=out_buff_ptr+1;`
269			`end`
270			`1:begin`
271			`last_din <=sd_data_out[7:4];`
272			`crc_in_write <=sd_data_out[7:4];`
273			`end`
274
275			`endcase`
276			`data_send_index<=data_send_index+1;`
277
278			`DAT_dat_o<= last_din;`
279
280			if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
281			`crc_en_write<=0;`
282			`end`
283			`end`
284			else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
285
286			`crc_en_write<=0;`
287			`crc_cnt_write<=crc_cnt_write-1;`
288			`DAT_oe_o<=1;`
289			`DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];`
290			`DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];`
291			`DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];`
292			`DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];`
293			`end`
294			else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
295			`DAT_oe_o<=1;`
296			`DAT_dat_o<=4'b1111;`
297
298			`end`
299			`else if (transf_cnt_write !=0) begin`
300			`DAT_oe_o<=0;`
301			`end`
302
303
304			`end`
305
306
307			`endcase`
308			`end`
309			`end`
310
311
312			`always @ (posedge sd_clk or posedge rst )`
313			`begin`
314			`if (rst) begin`
315			`add_token<=0;`
316			`sd_adr_o_read<=0;`
317			`crc_read_count<=0;`
318			`sd_we_o<=0;`
319			`tmp_crc_token<=0;`
320			`crc_rst_read<=0;`
321			`crc_en_read<=0;`
322			`in_buff_ptr_read<=0;`
323			`out_buff_ptr_read<=0;`
324			`crc_cnt_read<=0;`
325			`transf_cnt_read<=0;`
326			`data_read_index<=0;`
327			`in_dat_buffer_empty<=0;`
328
329			`next_out<=0;`
330			`busy_int<=0;`
331			`sd_dat_o<=0;`
332			`end`
333			`else begin`
334			`case(state)`
335			`IDLE: begin`
336			`add_token<=0;`
337			`crc_read_count<=0;`
338			`sd_we_o<=0;`
339			`tmp_crc_token<=0;`
340			`crc_rst_read<=1;`
341			`crc_en_read<=0;`
342			`in_buff_ptr_read<=0;`
343			`out_buff_ptr_read<=0;`
344			`crc_cnt_read<=15;`
345			`transf_cnt_read<=0;`
346			`data_read_index<=0;`
347			`in_dat_buffer_empty<=0;`
348			`end`
349
350			`READ_DAT: begin`
351			`add_token<=1;`
352			`crc_rst_read<=0;`
353			`crc_en_read<=1;`
354
355
356
357			`if (fifo_acces) begin`
358			`if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin`
359			`data_read_index<=~data_read_index;`
360			`case(data_read_index)`
361			`0: begin`
362			`sd_adr_o_read<=3;`
363			`sd_we_o<=0;`
364			`next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];`
365			`next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];`
366			`end`
367			`1: begin`
368			`out_buff_ptr_read<=out_buff_ptr_read+2;`
369			`sd_dat_o<=next_out;`
370			`sd_we_o<=1;`
371			`end`
372			`endcase`
373			`end`
374			`else`
375			`in_dat_buffer_empty<=1;`
376			`end`
377
378			if (transf_cnt_read<`BIT_BLOCK_REC) begin
379
380			`in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;`
381			`crc_in_read<=DAT_dat_i;`
382			`crc_ok<=1;`
383			`transf_cnt_read<=transf_cnt_read+1;`
384			`in_buff_ptr_read<=in_buff_ptr_read+1;`
385			`end`
386			else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
387			`transf_cnt_read<=transf_cnt_read+1;`
388			`crc_en_read<=0;`
389			`last_din_read <=DAT_dat_i;`
390
391			if (transf_cnt_read> `BIT_BLOCK_REC) begin
392			`crc_cnt_read <=crc_cnt_read-1;`
393
394
395			`if (crc_out_read[0][crc_cnt_read] != last_din[0])`
396			`crc_ok<=0;`
397			`if (crc_out_read[1][crc_cnt_read] != last_din[1])`
398			`crc_ok<=0;`
399			`if (crc_out_read[2][crc_cnt_read] != last_din[2])`
400			`crc_ok<=0;`
401			`if (crc_out_read[3][crc_cnt_read] != last_din[3])`
402			`crc_ok<=0;`
403
404			`if (crc_cnt_read==0) begin`
405			`//in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok}`
406			`end`
407			`end`
408			`end`
409
410
411
412			`end`
413			`READ_CRC: begin`
414			`if (crc_read_count<3'b111) begin`
415			`crc_read_count<=crc_read_count+1;`
416			`tmp_crc_token[crc_read_count] <= DAT_dat_i[0];`
417			`end`
418
419			`busy_int <=DAT_dat_i[0];`
420
421			`end`
422			`WRITE_CRC: begin`
423			`add_token<=1;`
424			`sd_adr_o_read<=3;`
425			`sd_we_o<=1;`
426			`sd_dat_o<=tmp_crc_token;`
427			`end`
428
429			`endcase`
430			`end`
431
432			`end`
433			`//Sync`
434
435
436
437
438
439
440
441			`endmodule`
442
443
444