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URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_fifo.v] - Blame information for rev 10

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Line No. Rev Author Line
1 6 tac2 
 
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module sd_fifo
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  (
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    input  [1:0] wb_adr_i,
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    input [7:0]  wb_dat_i,
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    output [7:0] wb_dat_o,
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    input        wb_we_i,
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    input        wb_re_i,
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    input        wb_clk,
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    input [1:0]  sd_adr_i,
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    input [7:0]  sd_dat_i,
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    output [7:0] sd_dat_o,
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    input        sd_we_i,
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    input        sd_re_i,
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    input        sd_clk,
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    output [1:4] fifo_full,
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    output [1:4] fifo_empty,
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    input        rst
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   );
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   wire [8:0]     wptr1, rptr1, wptr2, rptr2, wptr3, rptr3, wptr4, rptr4;
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   wire [8:0]     wadr1, radr1, wadr2, radr2, wadr3, radr3, wadr4, radr4;
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   wire          dpram_we_a, dpram_we_b;
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   wire [10:0]    dpram_a_a, dpram_a_b;
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   sd_counter wptr1a
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     (
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      .q(wptr1),
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      .q_bin(wadr1),
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      .cke((wb_adr_i==2'd0) & wb_we_i & !fifo_full[1]),
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      .clk(wb_clk),
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      .rst(rst)
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      );
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   sd_counter rptr1a
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     (
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      .q(rptr1),
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      .q_bin(radr1),
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      .cke((sd_adr_i==2'd0) & sd_re_i & !fifo_empty[1]),
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      .clk(sd_clk),
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      .rst(rst)
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      );
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  versatile_fifo_async_cmp
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    #
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    (
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     .ADDR_WIDTH(9)
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     )
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    cmp1
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    (
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      .wptr(wptr1),
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      .rptr(rptr1),
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      .fifo_empty(fifo_empty[1]),
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      .fifo_full(fifo_full[1]),
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      .wclk(wb_clk),
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      .rclk(sd_clk),
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      .rst(rst)
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      );
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   sd_counter wptr2a
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     (
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      .q(wptr2),
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      .q_bin(wadr2),
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      .cke((sd_adr_i==2'd1) & sd_we_i & !fifo_full[2]),
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      .clk(sd_clk),
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      .rst(rst)
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      );
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   sd_counter rptr2a
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     (
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      .q(rptr2),
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      .q_bin(radr2),
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      .cke((wb_adr_i==2'd1) & wb_re_i & !fifo_empty[2]),
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      .clk(wb_clk),
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      .rst(rst)
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      );
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  versatile_fifo_async_cmp
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    #
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    (
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     .ADDR_WIDTH(9)
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     )
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    cmp2
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    (
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      .wptr(wptr2),
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      .rptr(rptr2),
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      .fifo_empty(fifo_empty[2]),
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      .fifo_full(fifo_full[2]),
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      .wclk(sd_clk),
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      .rclk(wb_clk),
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      .rst(rst)
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      );
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   sd_counter wptr3a
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     (
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      .q(wptr3),
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      .q_bin(wadr3),
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      .cke((wb_adr_i==2'd2) & wb_we_i & !fifo_full[3]),
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      .clk(wb_clk),
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      .rst(rst)
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      );
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   sd_counter rptr3a
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     (
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      .q(rptr3),
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      .q_bin(radr3),
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      .cke((sd_adr_i==2'd2) & sd_re_i & !fifo_empty[3]),
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      .clk(sd_clk),
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      .rst(rst)
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      );
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  versatile_fifo_async_cmp
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    #
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    (
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     .ADDR_WIDTH(9)
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     )
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    cmp3
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    (
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      .wptr(wptr3),
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      .rptr(rptr3),
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      .fifo_empty(fifo_empty[3]),
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      .fifo_full(fifo_full[3]),
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      .wclk(wb_clk),
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      .rclk(sd_clk),
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      .rst(rst)
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      );
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   sd_counter wptr4a
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     (
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      .q(wptr4),
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      .q_bin(wadr4),
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      .cke((sd_adr_i==2'd3) & sd_we_i & !fifo_full[4]),
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      .clk(sd_clk),
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      .rst(rst)
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      );
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   sd_counter rptr4a
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     (
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      .q(rptr4),
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      .q_bin(radr4),
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      .cke((wb_adr_i==2'd3) & wb_re_i & !fifo_empty[4]),
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      .clk(wb_clk),
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      .rst(rst)
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      );
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  versatile_fifo_async_cmp
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    #
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    (
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     .ADDR_WIDTH(9)
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     )
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    cmp4
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    (
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      .wptr(wptr4),
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      .rptr(rptr4),
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      .fifo_empty(fifo_empty[4]),
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      .fifo_full(fifo_full[4]),
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      .wclk(sd_clk),
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      .rclk(wb_clk),
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      .rst(rst)
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      );
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   assign dpram_we_a = ((wb_adr_i==2'd0) & !fifo_full[1]) ? wb_we_i :
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                       ((wb_adr_i==2'd2) & !fifo_full[3]) ? wb_we_i :
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                       1'b0;
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   assign dpram_we_b = ((sd_adr_i==2'd1) & !fifo_full[2]) ? sd_we_i :
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                       ((sd_adr_i==2'd3) & !fifo_full[4]) ? sd_we_i :
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                       1'b0;
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   assign dpram_a_a = (wb_adr_i==2'd0) ? {wb_adr_i,wadr1} :
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                      (wb_adr_i==2'd1) ? {wb_adr_i,radr2} :
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                      (wb_adr_i==2'd2) ? {wb_adr_i,wadr3} :
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                      {wb_adr_i,radr4};
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   assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} :
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                      (sd_adr_i==2'd1) ? {sd_adr_i,wadr2} :
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                      (sd_adr_i==2'd2) ? {sd_adr_i,radr3} : //(sd_adr_i==2'd3) ? {sd_adr_i,radr3} :--->(sd_adr_i==2'd2) ? {sd_adr_i,radr3} :
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                      {sd_adr_i,wadr4};
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 //versatile_fifo_dual_port_ram_dc_dw
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   versatile_fifo_dptam_dw
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     dpram
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     (
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      .d_a(wb_dat_i),
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      .q_a(wb_dat_o),
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      .adr_a(dpram_a_a),
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      .we_a(dpram_we_a),
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      .clk_a(wb_clk),
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      .q_b(sd_dat_o),
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      .adr_b(dpram_a_b),
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      .d_b(sd_dat_i),
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      .we_b(dpram_we_b),
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      .clk_b(sd_clk)
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      );
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endmodule // sd_fifo
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