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[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [versatile_fifo_dptam_dw.v] - Blame information for rev 10

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module versatile_fifo_dptam_dw
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  (
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   d_a,
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   q_a,
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   adr_a,
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   we_a,
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   clk_a,
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   q_b,
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   adr_b,
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   d_b,
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   we_b,
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   clk_b
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   );
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   parameter DATA_WIDTH = 8;
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   parameter ADDR_WIDTH = 14;
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   input [(DATA_WIDTH-1):0]      d_a;
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   input [(ADDR_WIDTH-1):0]       adr_a;
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   input [(ADDR_WIDTH-1):0]       adr_b;
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   input                         we_a;
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   output reg[(DATA_WIDTH-1):0]   q_b;
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   input [(DATA_WIDTH-1):0]       d_b;
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   output reg [(DATA_WIDTH-1):0] q_a;
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   input                         we_b;
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   input                         clk_a, clk_b;
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   reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
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   always @ (posedge clk_a)
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     begin
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     q_a <= ram[adr_a];
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        if (we_a)  begin
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             ram[adr_a] <= d_a;
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          end
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end
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   always @ (posedge clk_b)
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     begin
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     q_b <= ram[adr_b];
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        if (we_b)
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          begin
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             ram[adr_b] <= d_b;
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          end
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     end
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endmodule
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