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/*$$HEADER*/
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/******************************************************************************/
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/* */
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/* H E A D E R I N F O R M A T I O N */
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/* */
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/******************************************************************************/
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// Project Name : Development Board Debugger Example
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// File Name : BootReset.S
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// Prepared By : jb
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// Project Start : 2009-01-01
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/* */
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/* C O P Y R I G H T N O T I C E */
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/* */
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/******************************************************************************/
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// Copyright (c) ORSoC 2009 All rights reserved.
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// The information in this document is the property of ORSoC.
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// Except as specifically authorized in writing by ORSoC, the receiver of
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// this document shall keep the information contained herein confidential and
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// shall protect the same in whole or in part thereof from disclosure and
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// dissemination to third parties. Disclosure and disseminations to the receiver's
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// employees shall only be made on a strict need to know basis.
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/*$$DESCRIPTION*/
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/******************************************************************************/
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/* */
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/* D E S C R I P T I O N */
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/* */
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/******************************************************************************/
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// Define the contents of the reset vector (from 0x100), an IC enable routine
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// as well as en external IRQ service routine.
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/*$$CHANGE HISTORY*/
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/******************************************************************************/
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/* */
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/* C H A N G E H I S T O R Y */
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/* */
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/******************************************************************************/
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// Date Version Description
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//------------------------------------------------------------------------
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// 090101 1.0 First version jb
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/*$$INCLUDE FILES*/
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/******************************************************************************/
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/* */
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/* I N C L U D E F I L E S */
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/* */
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/******************************************************************************/
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#include "board.h"
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#include "spr_defs.h"
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/*$$PRIVATE MACROS*/
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/******************************************************************************/
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/* */
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/* P R I V A T E M A C R O S */
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/* */
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/******************************************************************************/
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/******************************************************************************/
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/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */
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/******************************************************************************/
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.macro load32i reg const
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l.movhi \reg,hi(\const)
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l.ori \reg,\reg,lo(\const)
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.endm
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/******************************************************************************/
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/* S E T U P E X C E P T I O N V E C T O R */
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/******************************************************************************/
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.macro exception_vector name org
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.org \org
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.p2align 8
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.global __exception_\name
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__exception_\name:
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l.j __exception_\name
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l.nop
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.endm
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/******************************************************************************/
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/* B R A N C H T O N A M E */
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/******************************************************************************/
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.macro BSR name
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l.j \name
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l.nop
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ret_\name:
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.endm
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/*$$RESET START*/
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/******************************************************************************/
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/* */
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/* R E S E T S T A R T */
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/* */
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/******************************************************************************/
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.section .vectors, "ax"
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.org 0x100 - 0x100 // Sector .vectors start at 0x100
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_reset:
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// Set stack pointer (r1) to 00003560
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// Clear all other registers
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.equ sp,0x00003560 ;
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l.movhi r0,0x0000 ; #r0 = 0
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l.ori r0,r0,0x0000 ;
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l.movhi r1,hi(sp) ; #r1 = sp
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l.ori r1,r1,lo(sp) ;
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l.or r2,r0,r0 ; #clear r2
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l.or r3,r0,r0 ; #clear r3
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l.or r4,r0,r0 ; #clear r4
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l.or r5,r0,r0 ; #clear r5
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l.or r6,r0,r0 ; #clear r6
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l.or r7,r0,r0 ; #clear r7
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l.or r8,r0,r0 ; #clear r8
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l.or r9,r0,r0 ; #clear r9
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l.or r10,r0,r0 ; #clear r10
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l.or r11,r0,r0 ; #clear r11
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l.or r12,r0,r0 ; #clear r12
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l.or r13,r0,r0 ; #clear r13
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l.or r14,r0,r0 ; #clear r14
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l.or r15,r0,r0 ; #clear r15
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l.or r16,r0,r0 ; #clear r16
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l.or r17,r0,r0 ; #clear r17
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l.or r18,r0,r0 ; #clear r18
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l.or r19,r0,r0 ; #clear r19
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l.or r20,r0,r0 ; #clear r20
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l.or r21,r0,r0 ; #clear r21
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l.or r22,r0,r0 ; #clear r22
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l.or r23,r0,r0 ; #clear r23
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l.or r24,r0,r0 ; #clear r24
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l.or r25,r0,r0 ; #clear r25
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l.or r26,r0,r0 ; #clear r26
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l.or r27,r0,r0 ; #clear r27
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l.or r28,r0,r0 ; #clear r28
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l.or r29,r0,r0 ; #clear r29
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l.or r30,r0,r0 ; #clear r30
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l.or r31,r0,r0 ; #clear r31
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#if IC_ENABLE == 1 /* INSTRUCTION CACHE */
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BSR ic_enable
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#endif
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// Jump to start of program
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load32i r2, (_Start)
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l.jr r2
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l.nop
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exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100
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exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100
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exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100
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exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100
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exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100
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exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100
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// Defines what will happen when an external interrupt occurs
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.org 0x800 - 0x100
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.global __external_IRQ
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__external_IRQ:
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l.addi r1,r1,-30*4 //move SP 30*4 adresses lower
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l.sw 0x1c(r1),r9
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l.jal (save_state)
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l.nop
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// we mess with r3, r4 and r9
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//
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l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt
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l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled
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l.sfeqi r4,0
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l.bnf JUMP // external irq enabled, all ok.
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l.nop
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JUMP: l.jal (_external_exeption)
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l.nop
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l.jal (restore_state)
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l.nop
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l.lwz r9 ,0x1c(r1)
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l.addi r1,r1,30*4 //move SP 30*4 adresses lower
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//Return from exception
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l.rfe
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// Save current state (all general purpose registers)
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save_state:
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l.sw 0x0(r1),r2
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l.sw 0x4(r1),r3
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l.sw 0x8(r1),r4
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l.sw 0xc(r1),r5
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l.sw 0x10(r1),r6
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l.sw 0x14(r1),r7
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l.sw 0x18(r1),r8
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l.sw 0x20(r1),r10
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l.sw 0x24(r1),r11
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l.sw 0x28(r1),r12
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l.sw 0x2c(r1),r13
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l.sw 0x30(r1),r14
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l.sw 0x34(r1),r15
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l.sw 0x38(r1),r16
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l.sw 0x3c(r1),r17
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l.sw 0x40(r1),r18
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l.sw 0x44(r1),r19
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l.sw 0x48(r1),r20
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l.sw 0x4c(r1),r21
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l.sw 0x50(r1),r22
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l.sw 0x54(r1),r23
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l.sw 0x58(r1),r24
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l.sw 0x5c(r1),r25
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l.sw 0x60(r1),r26
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l.sw 0x64(r1),r27
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l.sw 0x68(r1),r28
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l.sw 0x6c(r1),r29
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l.sw 0x70(r1),r30
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l.jr r9
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l.nop
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// Restore current state
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restore_state:
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// disable interrupts (if needed)
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l.lwz r2,0x0(r1)
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l.lwz r3 ,0x4(r1)
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l.lwz r4 ,0x8(r1)
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l.lwz r5 ,0xc(r1)
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l.lwz r6 ,0x10(r1)
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l.lwz r7 ,0x14(r1)
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l.lwz r8 ,0x18(r1)
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l.lwz r10,0x20(r1)
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l.lwz r11,0x24(r1)
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l.lwz r12,0x28(r1)
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l.lwz r13,0x2c(r1)
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l.lwz r14,0x30(r1)
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l.lwz r15,0x34(r1)
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l.lwz r16,0x38(r1)
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l.lwz r17,0x3c(r1)
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l.lwz r18,0x40(r1)
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l.lwz r19,0x44(r1)
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l.lwz r20,0x48(r1)
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l.lwz r21,0x4c(r1)
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l.lwz r22,0x50(r1)
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l.lwz r23,0x54(r1)
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l.lwz r24,0x58(r1)
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l.lwz r25,0x5c(r1)
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l.lwz r26,0x60(r1)
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l.lwz r27,0x64(r1)
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l.lwz r28,0x68(r1)
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l.lwz r29,0x6c(r1)
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l.lwz r30,0x70(r1)
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l.jr r9
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l.nop
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/***************************
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* Instruction cache enable
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*/
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#if IC_ENABLE == 1
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ic_enable:
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Invalidate IC */
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l.addi r6,r0,0
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l.addi r5,r0,IC_SIZE
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1:
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.bf 1b
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l.addi r6,r6,IC_LINE
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/* Enable IC */
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| 305 |
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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| 310 |
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l.nop
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l.nop
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| 312 |
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l.nop
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| 313 |
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l.nop
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| 314 |
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l.nop
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| 315 |
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l.nop
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l.nop
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l.nop
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l.j ret_ic_enable
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l.nop
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#endif
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