URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [sw/] [sdc_dma/] [sd_controller.c] - Blame information for rev 127

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#include "orsocdef.h"
#include "board.h"
#include "sd_controller.h"
 
#define SD_REG(REG)  REG32(SD_CONTROLLER_BASE+REG) 
 
 
 
int sd_get_rca(sd_card *d)
{
      uint32 rtn_reg=0;
      SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48;
          SD_REG(SD_ARG)=0;
 
      if (sd_wait_rsp() == 0)
           return 0;
      else{
                  rtn_reg = SD_REG(SD_NORMAL_INT_STATUS);
          if ( (rtn_reg  & EI) == EI)    //Error in response, init failed return.
                   return 0;
                rtn_reg = SD_REG(SD_RESP1);
                d->rca=((rtn_reg&RCA_RCA_MASK)>>16);
           uart_print_str("rca fine");
 
          }
          return 1;
 
}
 
 
//return 0 if no response else return 1.
uint8 sd_wait_rsp()
{
  volatile unsigned long r1, r2;
 
 //Polling for timeout and command complete
 while (1 )
 {
  r1= SD_REG(SD_ERROR_INT_STATUS);
  r2= SD_REG(SD_NORMAL_INT_STATUS) ;
 
   if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT)
          return 0;
   else if ((r2  & CMD_COMPLETE ) == CMD_COMPLETE)
          return 1;
 
 }
  //Later Exception restart module
  return 0;
 
}
 
 
 
int sd_cmd_free() //Return 1 if CMD is busy
{
  unsigned int a= SD_REG(SD_STATUS);
  return (a & 1);
}
 sd_card sd_controller_init ()
{
  sd_card dev;
 
   volatile unsigned long rtn_reg=0;
   volatile  unsigned long rtn_reg1=0;
 
   REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x00008FF;
 
   REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000001;
   REG32(SD_CONTROLLER_BASE+SD_CLOCK_D)=0x0000002;
   REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000000;
 
        REG32(SD_CONTROLLER_BASE+SD_ARG)   =0x0000;
        REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
    sd_wait_rsp();
 
        SD_REG(SD_COMMAND) = ( CMD8 | CICE | CRCE | RSP_48);
    SD_REG(SD_ARG) = VHS|CHECK_PATTERN;
 
        dev.phys_spec_2_0 = sd_wait_rsp();
        REG32(SD_CONTROLLER_BASE+SD_ARG)   =0x0000;
                REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
                    sd_wait_rsp();
     if (dev.phys_spec_2_0)
          {
                // uart_print_str("2_0 CARD /n");
            return dev;
          }
          else
          {
 
                REG32(SD_CONTROLLER_BASE+SD_ARG)   =0x0000;
                REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;
                while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {}
 
 
                rtn_reg=0;
        while ((rtn_reg & BUSY) != BUSY)
            {
          REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48;
              REG32(SD_CONTROLLER_BASE+SD_ARG) =0;
          if (!sd_wait_rsp())
                         return dev;
         REG32(SD_CONTROLLER_BASE+SD_COMMAND) =ACMD41 | RSP_48;
                 REG32(SD_CONTROLLER_BASE+SD_ARG)   =0;
         if (!sd_wait_rsp())
                         return dev;
                  rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ;
                }
            dev.Voltage_window=rtn_reg&VOLTAGE_MASK;
                dev.HCS_s = 0;
 
        }
 
 
                //GET CID
        REG32(SD_CONTROLLER_BASE+SD_COMMAND) =CMD2 | RSP_146;
                REG32(SD_CONTROLLER_BASE+SD_ARG)   =0;
                if (!sd_wait_rsp())
                         return dev;
        //Get RCA
            SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48;
                SD_REG(SD_ARG)=0;
                if (!sd_wait_rsp())
                         return dev;
                 rtn_reg = SD_REG(SD_RESP1);
                dev.rca = ((rtn_reg&RCA_RCA_MASK));
 
        dev.Active=1;
    return dev;
 
}

Line No.	Rev	Author	Line
1	69	tac2
2			`#include "orsocdef.h"`
3			`#include "board.h"`
4			`#include "sd_controller.h"`
5
6			`#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG)`
7
8
9
10			`int sd_get_rca(sd_card *d)`
11			`{`
12			`uint32 rtn_reg=0;`
13			`SD_REG(SD_COMMAND) = CMD3 \| CICE \| CRCE \| RSP_48;`
14			`SD_REG(SD_ARG)=0;`
15
16			`if (sd_wait_rsp() == 0)`
17			`return 0;`
18			`else{`
19			`rtn_reg = SD_REG(SD_NORMAL_INT_STATUS);`
20			`if ( (rtn_reg & EI) == EI) //Error in response, init failed return.`
21			`return 0;`
22			`rtn_reg = SD_REG(SD_RESP1);`
23			`d->rca=((rtn_reg&RCA_RCA_MASK)>>16);`
24			`uart_print_str("rca fine");`
25
26			`}`
27			`return 1;`
28
29			`}`
30
31
32			`//return 0 if no response else return 1.`
33			`uint8 sd_wait_rsp()`
34			`{`
35			`volatile unsigned long r1, r2;`
36
37			`//Polling for timeout and command complete`
38			`while (1 )`
39			`{`
40			`r1= SD_REG(SD_ERROR_INT_STATUS);`
41			`r2= SD_REG(SD_NORMAL_INT_STATUS) ;`
42
43			`if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT)`
44			`return 0;`
45			`else if ((r2 & CMD_COMPLETE ) == CMD_COMPLETE)`
46			`return 1;`
47
48			`}`
49			`//Later Exception restart module`
50			`return 0;`
51
52			`}`
53
54
55
56			`int sd_cmd_free() //Return 1 if CMD is busy`
57			`{`
58			`unsigned int a= SD_REG(SD_STATUS);`
59			`return (a & 1);`
60			`}`
61			`sd_card sd_controller_init ()`
62			`{`
63			`sd_card dev;`
64
65			`volatile unsigned long rtn_reg=0;`
66			`volatile unsigned long rtn_reg1=0;`
67
68			`REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x00008FF;`
69
70			`REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000001;`
71			`REG32(SD_CONTROLLER_BASE+SD_CLOCK_D)=0x0000002;`
72			`REG32(SD_CONTROLLER_BASE+SD_SOFTWARE_RST)=0x0000000;`
73
74			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;`
75			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;`
76			`sd_wait_rsp();`
77
78			`SD_REG(SD_COMMAND) = ( CMD8 \| CICE \| CRCE \| RSP_48);`
79			`SD_REG(SD_ARG) = VHS\|CHECK_PATTERN;`
80
81			`dev.phys_spec_2_0 = sd_wait_rsp();`
82			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;`
83			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;`
84			`sd_wait_rsp();`
85			`if (dev.phys_spec_2_0)`
86			`{`
87			`// uart_print_str("2_0 CARD /n");`
88			`return dev;`
89			`}`
90			`else`
91			`{`
92
93			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000;`
94			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000;`
95			`while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {}`
96
97
98			`rtn_reg=0;`
99			`while ((rtn_reg & BUSY) != BUSY)`
100			`{`
101			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55\|RSP_48;`
102			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0;`
103			`if (!sd_wait_rsp())`
104			`return dev;`
105			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) =ACMD41 \| RSP_48;`
106			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0;`
107			`if (!sd_wait_rsp())`
108			`return dev;`
109			`rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ;`
110			`}`
111			`dev.Voltage_window=rtn_reg&VOLTAGE_MASK;`
112			`dev.HCS_s = 0;`
113
114			`}`
115
116
117			`//GET CID`
118			`REG32(SD_CONTROLLER_BASE+SD_COMMAND) =CMD2 \| RSP_146;`
119			`REG32(SD_CONTROLLER_BASE+SD_ARG) =0;`
120			`if (!sd_wait_rsp())`
121			`return dev;`
122			`//Get RCA`
123			`SD_REG(SD_COMMAND) = CMD3 \| CICE \| CRCE \| RSP_48;`
124			`SD_REG(SD_ARG)=0;`
125			`if (!sd_wait_rsp())`
126			`return dev;`
127			`rtn_reg = SD_REG(SD_RESP1);`
128			`dev.rca = ((rtn_reg&RCA_RCA_MASK));`
129
130			`dev.Active=1;`
131			`return dev;`
132
133			`}`

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[/] [sdcard_mass_storage_controller/] [trunk/] [sw/] [sdc_dma/] [sd_controller.c] - Blame information for rev 127