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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [sw/] [sdc_fifo/] [main.c] - Blame information for rev 85

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/*$$HEADER*/
/******************************************************************************/
/*                                                                            */
/*                    H E A D E R   I N F O R M A T I O N                     */
/*                                                                            */
/******************************************************************************/
 
// Project Name                   : Development Board Debugger Example 
// File Name                      : main.c
// Prepared By                    : jb
// Project Start                  : 2009-01-01
 
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/*                                                                            */
/*                      C O P Y R I G H T   N O T I C E                       */
/*                                                                            */
/******************************************************************************/
 
// Copyright (c) ORSoC 2009 All rights reserved.
 
// The information in this document is the property of ORSoC.
// Except as specifically authorized in writing by ORSoC, the receiver of
// this document shall keep the information contained herein confidential and
// shall protect the same in whole or in part thereof from disclosure and
// dissemination to third parties. Disclosure and disseminations to the receiver's
// employees shall only be made on a strict need to know basis.
 
 
/*$$DESCRIPTION*/
/******************************************************************************/
/*                                                                            */
/*                           D E S C R I P T I O N                            */
/*                                                                            */
/******************************************************************************/
 
// Perform some simple functions, used as an example when first using the 
// debug cable and proxy with GDB.
 
/*$$CHANGE HISTORY*/
/******************************************************************************/
/*                                                                            */
/*                         C H A N G E  H I S T O R Y                         */
/*                                                                            */
/******************************************************************************/
 
// Date         Version Description
//------------------------------------------------------------------------
// 090101       1.0     First version                           jb
 
/*$$INCLUDE FILES*/
/******************************************************************************/
/*                                                                            */
/*                      I N C L U D E   F I L E S                             */
/*                                                                            */
/******************************************************************************/
 
#define INCLUDED_FROM_C_FILE
 
#include "orsocdef.h"
#include "board.h"
#include "uart.h"
#include "main.h"
#define SD_REG(REG)  REG32(SD_CONTROLLER_BASE+REG) 
/*$$PRIVATE MACROS*/
/******************************************************************************/
/*                                                                            */
/*                      P R I V A T E   M A C R O S                           */
/*                                                                            */
/******************************************************************************/
 
/*$$GLOBAL VARIABLES*/
/******************************************************************************/
/*                                                                            */
/*                   G L O B A L   V A R I A B L E S                          */
/*                                                                            */
/******************************************************************************/
 
/*$$PRIVATE VARIABLES*/
/******************************************************************************/
/*                                                                            */
/*                  P R I V A T E   V A R I A B L E S                         */
/*                                                                            */
/******************************************************************************/
 
 
/*$$FUNCTIONS*/
/******************************************************************************/
/*                                                                            */
/*                          F U N C T I O N S                                 */
/*                                                                            */
/******************************************************************************/
 
 
/******************************************************************************/
/*                        W R I T E  T O EXTERNAL SDRAM 1                     */
/******************************************************************************/
 
// Write to External SDRAM  
void Write_External_SDRAM_1(void)
{
   uint32      i;
   uint32      read;
   uint32      range;
   uint32      adr_offset;
 
   range      = 0x7ff;        // Max range: 0x7fffff
   adr_offset = 0x00000000;  // External memory offset
 
   for (i=0x0; i < range; i=i+4) {
      REG32(adr_offset + i)   = (adr_offset + i);
   }
 
   for (i=0x0; i < range; i=i+4) {
     read = REG32(adr_offset + i);
     if (read != (adr_offset + i)) {
       while(TRUE){            //ERROR=HALT PROCESSOR 
       }
     }
   }
}
 
 
/*$$EXTERNAL EXEPTIONS*/
/******************************************************************************/
/*                  E X T E R N A L   E X E P T I O N S                       */
/******************************************************************************/
 
 
void external_exeption()
{
  REG uint8 i;
  REG uint32 PicSr,sr;
 
}
 
/*$$MAIN*/
/******************************************************************************/
/*                                                                            */
/*                       M A I N   P R O G R A M                              */
/*                                                                            */
/******************************************************************************/
 
 
 
 
 
 
//TO do
// Always check if error in repose (CRC, CICE) etc
// Always check for CICM (Command inhibit before senindg)
// Timeout when polling
// Divied into dividing Functions
// Clean up
 
 
#define BUSY 0x80
#define CRC_TOKEN 0x29
 
//SDC_REGISTERS
#define TX_CMD_FIFO 0x00
#define RX_CMD_FIFO 0x04
#define TX_DATA_FIFO 0x08
#define RX_DATA_FIFO 0x0C
#define STATUS 0x10
#define CONTROLL 0x14
#define TIMER_REG 0x18
 
//Program Defines
#define TRANSMISSION_FAILURE 1
#define TRANSMISSION_SUCCESSFUL 0
#define BYTE_1_MASK 0x000000FF
#define BYTE_2_MASK 0x0000FF00
#define BYTE_3_MASK 0x00FF0000
#define BYTE_4_MASK 0xFF000000
#define MMC_DATA_SIZE 512
 
BYTE MMCWRData[MMC_DATA_SIZE];
BYTE MMCRDData[MMC_DATA_SIZE];
 
unsigned char rca[2];
 
bool mmc_get_cmd_bigrsp (volatile unsigned char *rsp)
{
   unsigned char rtn_reg=0;
   unsigned char rtn_reg_timer=0;
  int arr_cnt=0;
 rtn_reg_timer= SD_REG(TIMER_REG);
  while (rtn_reg_timer != 0)
  {
     rtn_reg = SD_REG(STATUS);
                 if  (( rtn_reg & 0x2) != 0x2) //RX Fifo not Empty
                 {
                         rsp[arr_cnt]=SD_REG(RX_CMD_FIFO);
                         arr_cnt++;
 
                 }
                 if (arr_cnt==15)
                                return 1;
      rtn_reg_timer= SD_REG(TIMER_REG);
  }
  return 0;
}
 
/************************** SD mmc_get_cmd_rsp *********************************/
/*
* Read CMD_RX_FIFO, add to the rsp array,
* 1 on success, return 0 at timeout
*
*/
bool mmc_get_cmd_rsp (volatile unsigned char *rsp)
{
   volatile unsigned char rtn_reg=0;
   volatile unsigned char rtn_reg_timer=0;
  int arr_cnt=0;
 rtn_reg_timer= SD_REG(TIMER_REG);
  while (rtn_reg_timer != 0)
  {
     rtn_reg = SD_REG(STATUS);
                 if  (( rtn_reg & 0x2) != 0x2) //RX Fifo not Empty
                 {
                         rsp[arr_cnt]=SD_REG(RX_CMD_FIFO);
                         arr_cnt++;
 
                 }
                 if (arr_cnt==5)
                                return 1;
      rtn_reg_timer= SD_REG(TIMER_REG);
  }
  return 0;
}
 
 
 
bool cmd_trans_succesful (volatile unsigned char resp)
{
  if ( (resp & 0x1) != 1 )
          return 1;
  else
          return 0;
 
}
void write_0(int i)
{
    while( i !=0){
     SD_REG(TX_CMD_FIFO)=0;
         i--;
}
 
}
int  mmc_init()
 
{
 
         volatile unsigned char rtn_reg=0;
         volatile unsigned int spv_2_0 =0;
         volatile unsigned char response[15];
         volatile unsigned char out_cmd[5];
         response[0]=0;
         //Reset the hardware
         /* initialise the MMC card into SD-Bus mode, is performed in HW*/
         SD_REG(CONTROLL)=1;
         SD_REG(CONTROLL)=0;
 
     //Reset SD Card. CMD 0, Arg 0. 
         //No response, wait for timeout
         SD_REG(TX_CMD_FIFO)=0x40;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
 
         while ( SD_REG(TIMER_REG) != 0){}
 
     //Check for SD 2.0 Card, 
         SD_REG(TX_CMD_FIFO)=0x48;
         SD_REG(TX_CMD_FIFO)=0x00;
          SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x01;
         SD_REG(TX_CMD_FIFO)=0xAA;
 
     //if response, card is v2.0 compatible, else reset card.
     if (mmc_get_cmd_rsp(&response[0]) )
       spv_2_0 = 1;
         else
         {
           SD_REG(CONTROLL)=1;
           SD_REG(CONTROLL)=0;
       SD_REG(TX_CMD_FIFO)=0x40;
           SD_REG(TX_CMD_FIFO)=0x00;
           SD_REG(TX_CMD_FIFO)=0x00;
           SD_REG(TX_CMD_FIFO)=0x00;
           SD_REG(TX_CMD_FIFO)=0x00;
 
           while ( SD_REG(TIMER_REG) != 0){}
         }
 
         if(spv_2_0==0)
         {
                //Send CMD55+ACMD41 until Busy bit is cleared (Response[0][8]==1)
                while ( (rtn_reg & BUSY) != BUSY )
                {       SD_REG(TX_CMD_FIFO)=0x77;
                        SD_REG(TX_CMD_FIFO)=0x00;
                        SD_REG(TX_CMD_FIFO)=0x00;
                        SD_REG(TX_CMD_FIFO)=0x00;
                        SD_REG(TX_CMD_FIFO)=0x00;
                        if ( mmc_get_cmd_rsp(&response[0]) && response[4]==0)
                        {
                                SD_REG(TX_CMD_FIFO)=0x69;
                                SD_REG(TX_CMD_FIFO)=0x00;
                                SD_REG(TX_CMD_FIFO)=0x00;
                                SD_REG(TX_CMD_FIFO)=0x00;
                                SD_REG(TX_CMD_FIFO)=0x00;
                                if (mmc_get_cmd_rsp(&response[0]))
                                        rtn_reg = response[0];
                                else
                                        return TRANSMISSION_FAILURE;
          }
          else
                 return TRANSMISSION_FAILURE;
         }
 
         }
         //else Physical Specification Version 2.00
         //Check response
         //Initialization (ACMD41 HCS=1)
         //Check for High Capacity or Standrd Capacity,  Ver.2.00 Card
 
     //CMD 2- get CSD, 136 bit response (Bit-40 this)
         SD_REG(TX_CMD_FIFO)=0xC2;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
 
     if (!mmc_get_cmd_bigrsp(&response[0]))
                return TRANSMISSION_FAILURE;
 
         //CMD 3- get RCA nr            
         SD_REG(TX_CMD_FIFO)=0x43;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
         SD_REG(TX_CMD_FIFO)=0x00;
     if (mmc_get_cmd_rsp(&response[0]))
         {
                 rca[0] = response[0];
                 rca[1] = response[1];
         }
         else
                return TRANSMISSION_FAILURE;
 
     //Put card in transfer state, CMD 7
         SD_REG(TX_CMD_FIFO)=0x47;
         SD_REG(TX_CMD_FIFO)= rca[0] ;
         SD_REG(TX_CMD_FIFO)= rca[1] ;
         SD_REG(TX_CMD_FIFO)=0x0f;
         SD_REG(TX_CMD_FIFO)=0x0f;
         if (!mmc_get_cmd_rsp(&response[0]))
           return TRANSMISSION_FAILURE;
 
         //Set block size 512. CMD 16
         SD_REG(TX_CMD_FIFO)=0x50;
          SD_REG(TX_CMD_FIFO)=0;
           SD_REG(TX_CMD_FIFO)=0;
         SD_REG(TX_CMD_FIFO)=0x02;
         SD_REG(TX_CMD_FIFO)=0;
         if (!mmc_get_cmd_rsp(&response[0]))
            return TRANSMISSION_FAILURE;
 
          //Set bus width to 4. CMD 55 + ACMD 6   
          SD_REG(TX_CMD_FIFO)=0x77;
          SD_REG(TX_CMD_FIFO)= rca[0] ;
          SD_REG(TX_CMD_FIFO)= rca[1] ;
           SD_REG(TX_CMD_FIFO)=0;
            SD_REG(TX_CMD_FIFO)=0;
          if (!mmc_get_cmd_rsp(&response[0]))
                return TRANSMISSION_FAILURE;
          // ACMD 6
          SD_REG(TX_CMD_FIFO)=0x46;
           SD_REG(TX_CMD_FIFO)=0;
            SD_REG(TX_CMD_FIFO)=0;
                 SD_REG(TX_CMD_FIFO)=0;
          SD_REG(TX_CMD_FIFO)=0x02;
          if (!mmc_get_cmd_rsp(&response[0]))
                        return TRANSMISSION_FAILURE;
 
   return TRANSMISSION_SUCCESSFUL;
}
 
 
int mmc_write_block(uint32 block_number)
{
   uint32 var;
   volatile unsigned char rtn_reg=0;
     unsigned char response[4];
   int i;
 
 
    var= block_number << 9 ;
 
   for (i=0; i < MMC_DATA_SIZE; i++)
           SD_REG(TX_DATA_FIFO) = MMCWRData[i];
 
 
   //Send CMD24, Single block write
    SD_REG(TX_CMD_FIFO)=0x58;
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 24) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 16) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 8) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)(var & 0xFF);
        if (!mmc_get_cmd_rsp(&response[0]))
                        return TRANSMISSION_FAILURE;
 
    //Wait for TX_DATA_FIFO to get empty                
        while ( (SD_REG(STATUS)& 0x04) == 0x04) {}
    //Wait for RX_DATA_FIFO to not get empty, indicate transmision is complete and CRC token is avaible.        
        while ( (SD_REG(STATUS) & 0x08) == 0x08) {}
 
        //Check for correct CRC repsonse token == 0x29...
        //Busy cehck is performed in HW
        rtn_reg =SD_REG(RX_DATA_FIFO);
        if ((rtn_reg & CRC_TOKEN) == CRC_TOKEN)
         return TRANSMISSION_SUCCESSFUL;
        else
         return TRANSMISSION_FAILURE;
}
 
int mmc_read_block(uint32 block_number)
{
    volatile int i = 0;
    volatile unsigned char response[4];
        volatile unsigned char rsp;
   uint32 var;
   WORD Checksum;
 
    var= block_number << 9;
 
    SD_REG(TX_CMD_FIFO)=0x51;
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 24) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 16) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 8) & 0xFF);
        SD_REG(TX_CMD_FIFO)=(BYTE)(var & 0xFF);
   if (!mmc_get_cmd_rsp(&response[0]))
                        return TRANSMISSION_FAILURE;
 
rsp =  SD_REG(STATUS) & 0x08;
while ( rsp == 0x08) {
rsp =  SD_REG(STATUS) & 0x08;}
  //Checksum is notread
 
i=0;
 
 /* while (i<MMC_DATA_SIZE){
 
  MMCRDData[i]=SD_REG(RX_DATA_FIFO);
  i++;
  }
   */
 
         BYTE *p;
  p=&MMCRDData[0];
 
   register int  RX_REG asm ("r0") ;
    register int RSP asm ("r6") ;
    register int  LOOP_END asm ("r2") ;
        register int  DAT_RSP asm ("r3") ;
 
         register int  SAVE_RX_REG asm ("r18") ;
         register int  SAVE_RSP asm ("r19") ;
         register int  SAVE_LOOP_END asm ("r20") ;
         register int  SAVE_DAT_RSP asm ("r21") ;
 
    //  asm volatile ("l.mtspr %0,%1, %2" : "=r"(RSP) : "m"(p), "i"(0));
        // 10007f8:     19 80 01 00     l.movhi r12,0x100
  //10007fc:    a9 8c 34 10     l.ori r12,r12,0x3410
 
        asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_RSP ) : "r"(RSP), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_RX_REG ) : "r"(RX_REG), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_LOOP_END ) : "r"(LOOP_END), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_DAT_RSP ) : "r"(DAT_RSP), "i"(0));
 
 
        RSP=&MMCRDData[0];
  // asm volatile ("l.movhi %0,%1" : "=r"(RSP) : "i"(0x100) );
   //asm volatile ("l.ori %0,%1, %2" : "=r"(RSP) :  "r"(RSP)  , "i"(0x4db0) );
 
 
    asm volatile ("l.movhi %0,%1" : "=r"(RX_REG) : "i"(0xa000) );
    asm volatile ("l.ori %0,%1, %2" : "=r"(RX_REG) :  "r"(RX_REG)  , "i"(0xc) );
 
 
   asm volatile ("l.addi %0,%1,%2" : "=r"(LOOP_END) : "r"(RSP) , "i"(0x200) );
 
   asm ("label:");
   asm volatile ("l.lwz %0,%1 %2" : "=r"(DAT_RSP) : "i"(0), "r"(RX_REG) );
   asm volatile ("l.sb  %0 %1, %2" :  : "i"(0), "r"(RSP) , "r"(DAT_RSP) );
   asm volatile ("l.addi %0,%1,%2" : "=r"(RSP) : "r"(RSP), "i"(0x1) );
 
        asm volatile ("l.sfne %0,%1" : "=r"(RSP) :"r"(LOOP_END) );
 
        asm volatile ("l.bf  label" );
 
        asm volatile ("l.nop");
        asm volatile ("l.addi %0,%1, %2" : "=r"(RSP) : "r"(SAVE_RSP ), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(RX_REG) : "r"(SAVE_RX_REG ), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(LOOP_END ) : "r"(SAVE_LOOP_END), "i"(0));
        asm volatile ("l.addi %0,%1, %2" : "=r"(DAT_RSP ) : "r"(SAVE_DAT_RSP), "i"(0));
 
 
  return TRANSMISSION_SUCCESSFUL;
}
void Start()
{
     volatile unsigned char rtn_reg=0;
    volatile unsigned char response[16];
     volatile int a;
         volatile int i;
 
         for (i=0;i<512;i++)
            MMCWRData[i]=0xff;
 
        uart_init();
        a=mmc_init();
        if (a)
                 uart_print_str("1");
         else
                 uart_print_str("0");
 
//       mmc_write_block(0); 
    mmc_read_block(0);
         for (i=0;i<512;i++)
        uart_print_long(  MMCRDData[i]);
 
                 mmc_read_block(1);
         for (i=0;i<512;i++)
          uart_print_long(  MMCRDData[i]);
 
 
}

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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [sw/] [sdc_fifo/] [main.c] - Blame information for rev 85

Line No.	Rev	Author	Line
1	85	tac2
2			`/$$HEADER/`
3			`/******************************************************************************/`
4			`/* */`
5			`/* H E A D E R I N F O R M A T I O N */`
6			`/* */`
7			`/******************************************************************************/`
8
9			`// Project Name : Development Board Debugger Example`
10			`// File Name : main.c`
11			`// Prepared By : jb`
12			`// Project Start : 2009-01-01`
13
14
15			`/$$COPYRIGHT NOTICE/`
16			`/******************************************************************************/`
17			`/* */`
18			`/* C O P Y R I G H T N O T I C E */`
19			`/* */`
20			`/******************************************************************************/`
21
22			`// Copyright (c) ORSoC 2009 All rights reserved.`
23
24			`// The information in this document is the property of ORSoC.`
25			`// Except as specifically authorized in writing by ORSoC, the receiver of`
26			`// this document shall keep the information contained herein confidential and`
27			`// shall protect the same in whole or in part thereof from disclosure and`
28			`// dissemination to third parties. Disclosure and disseminations to the receiver's`
29			`// employees shall only be made on a strict need to know basis.`
30
31
32			`/$$DESCRIPTION/`
33			`/******************************************************************************/`
34			`/* */`
35			`/* D E S C R I P T I O N */`
36			`/* */`
37			`/******************************************************************************/`
38
39			`// Perform some simple functions, used as an example when first using the`
40			`// debug cable and proxy with GDB.`
41
42			`/$$CHANGE HISTORY/`
43			`/******************************************************************************/`
44			`/* */`
45			`/* C H A N G E H I S T O R Y */`
46			`/* */`
47			`/******************************************************************************/`
48
49			`// Date Version Description`
50			`//------------------------------------------------------------------------`
51			`// 090101 1.0 First version jb`
52
53			`/$$INCLUDE FILES/`
54			`/******************************************************************************/`
55			`/* */`
56			`/* I N C L U D E F I L E S */`
57			`/* */`
58			`/******************************************************************************/`
59
60			`#define INCLUDED_FROM_C_FILE`
61
62			`#include "orsocdef.h"`
63			`#include "board.h"`
64			`#include "uart.h"`
65			`#include "main.h"`
66			`#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG)`
67			`/$$PRIVATE MACROS/`
68			`/******************************************************************************/`
69			`/* */`
70			`/* P R I V A T E M A C R O S */`
71			`/* */`
72			`/******************************************************************************/`
73
74			`/$$GLOBAL VARIABLES/`
75			`/******************************************************************************/`
76			`/* */`
77			`/* G L O B A L V A R I A B L E S */`
78			`/* */`
79			`/******************************************************************************/`
80
81			`/$$PRIVATE VARIABLES/`
82			`/******************************************************************************/`
83			`/* */`
84			`/* P R I V A T E V A R I A B L E S */`
85			`/* */`
86			`/******************************************************************************/`
87
88
89			`/$$FUNCTIONS/`
90			`/******************************************************************************/`
91			`/* */`
92			`/* F U N C T I O N S */`
93			`/* */`
94			`/******************************************************************************/`
95
96
97			`/******************************************************************************/`
98			`/* W R I T E T O EXTERNAL SDRAM 1 */`
99			`/******************************************************************************/`
100
101			`// Write to External SDRAM`
102			`void Write_External_SDRAM_1(void)`
103			`{`
104			`uint32 i;`
105			`uint32 read;`
106			`uint32 range;`
107			`uint32 adr_offset;`
108
109			`range = 0x7ff; // Max range: 0x7fffff`
110			`adr_offset = 0x00000000; // External memory offset`
111
112			`for (i=0x0; i < range; i=i+4) {`
113			`REG32(adr_offset + i) = (adr_offset + i);`
114			`}`
115
116			`for (i=0x0; i < range; i=i+4) {`
117			`read = REG32(adr_offset + i);`
118			`if (read != (adr_offset + i)) {`
119			`while(TRUE){ //ERROR=HALT PROCESSOR`
120			`}`
121			`}`
122			`}`
123			`}`
124
125
126			`/$$EXTERNAL EXEPTIONS/`
127			`/******************************************************************************/`
128			`/* E X T E R N A L E X E P T I O N S */`
129			`/******************************************************************************/`
130
131
132			`void external_exeption()`
133			`{`
134			`REG uint8 i;`
135			`REG uint32 PicSr,sr;`
136
137			`}`
138
139			`/$$MAIN/`
140			`/******************************************************************************/`
141			`/* */`
142			`/* M A I N P R O G R A M */`
143			`/* */`
144			`/******************************************************************************/`
145
146
147
148
149
150
151			`//TO do`
152			`// Always check if error in repose (CRC, CICE) etc`
153			`// Always check for CICM (Command inhibit before senindg)`
154			`// Timeout when polling`
155			`// Divied into dividing Functions`
156			`// Clean up`
157
158
159			`#define BUSY 0x80`
160			`#define CRC_TOKEN 0x29`
161
162			`//SDC_REGISTERS`
163			`#define TX_CMD_FIFO 0x00`
164			`#define RX_CMD_FIFO 0x04`
165			`#define TX_DATA_FIFO 0x08`
166			`#define RX_DATA_FIFO 0x0C`
167			`#define STATUS 0x10`
168			`#define CONTROLL 0x14`
169			`#define TIMER_REG 0x18`
170
171			`//Program Defines`
172			`#define TRANSMISSION_FAILURE 1`
173			`#define TRANSMISSION_SUCCESSFUL 0`
174			`#define BYTE_1_MASK 0x000000FF`
175			`#define BYTE_2_MASK 0x0000FF00`
176			`#define BYTE_3_MASK 0x00FF0000`
177			`#define BYTE_4_MASK 0xFF000000`
178			`#define MMC_DATA_SIZE 512`
179
180			`BYTE MMCWRData[MMC_DATA_SIZE];`
181			`BYTE MMCRDData[MMC_DATA_SIZE];`
182
183			`unsigned char rca[2];`
184
185			`bool mmc_get_cmd_bigrsp (volatile unsigned char *rsp)`
186			`{`
187			`unsigned char rtn_reg=0;`
188			`unsigned char rtn_reg_timer=0;`
189			`int arr_cnt=0;`
190			`rtn_reg_timer= SD_REG(TIMER_REG);`
191			`while (rtn_reg_timer != 0)`
192			`{`
193			`rtn_reg = SD_REG(STATUS);`
194			`if (( rtn_reg & 0x2) != 0x2) //RX Fifo not Empty`
195			`{`
196			`rsp[arr_cnt]=SD_REG(RX_CMD_FIFO);`
197			`arr_cnt++;`
198
199			`}`
200			`if (arr_cnt==15)`
201			`return 1;`
202			`rtn_reg_timer= SD_REG(TIMER_REG);`
203			`}`
204			`return 0;`
205			`}`
206
207			`/************************ SD mmc_get_cmd_rsp *******************************/`
208			`/*`
209			`* Read CMD_RX_FIFO, add to the rsp array,`
210			`* 1 on success, return 0 at timeout`
211			`*`
212			`*/`
213			`bool mmc_get_cmd_rsp (volatile unsigned char *rsp)`
214			`{`
215			`volatile unsigned char rtn_reg=0;`
216			`volatile unsigned char rtn_reg_timer=0;`
217			`int arr_cnt=0;`
218			`rtn_reg_timer= SD_REG(TIMER_REG);`
219			`while (rtn_reg_timer != 0)`
220			`{`
221			`rtn_reg = SD_REG(STATUS);`
222			`if (( rtn_reg & 0x2) != 0x2) //RX Fifo not Empty`
223			`{`
224			`rsp[arr_cnt]=SD_REG(RX_CMD_FIFO);`
225			`arr_cnt++;`
226
227			`}`
228			`if (arr_cnt==5)`
229			`return 1;`
230			`rtn_reg_timer= SD_REG(TIMER_REG);`
231			`}`
232			`return 0;`
233			`}`
234
235
236
237			`bool cmd_trans_succesful (volatile unsigned char resp)`
238			`{`
239			`if ( (resp & 0x1) != 1 )`
240			`return 1;`
241			`else`
242			`return 0;`
243
244			`}`
245			`void write_0(int i)`
246			`{`
247			`while( i !=0){`
248			`SD_REG(TX_CMD_FIFO)=0;`
249			`i--;`
250			`}`
251
252			`}`
253			`int mmc_init()`
254
255			`{`
256
257			`volatile unsigned char rtn_reg=0;`
258			`volatile unsigned int spv_2_0 =0;`
259			`volatile unsigned char response[15];`
260			`volatile unsigned char out_cmd[5];`
261			`response[0]=0;`
262			`//Reset the hardware`
263			`/* initialise the MMC card into SD-Bus mode, is performed in HW*/`
264			`SD_REG(CONTROLL)=1;`
265			`SD_REG(CONTROLL)=0;`
266
267			`//Reset SD Card. CMD 0, Arg 0.`
268			`//No response, wait for timeout`
269			`SD_REG(TX_CMD_FIFO)=0x40;`
270			`SD_REG(TX_CMD_FIFO)=0x00;`
271			`SD_REG(TX_CMD_FIFO)=0x00;`
272			`SD_REG(TX_CMD_FIFO)=0x00;`
273			`SD_REG(TX_CMD_FIFO)=0x00;`
274
275			`while ( SD_REG(TIMER_REG) != 0){}`
276
277			`//Check for SD 2.0 Card,`
278			`SD_REG(TX_CMD_FIFO)=0x48;`
279			`SD_REG(TX_CMD_FIFO)=0x00;`
280			`SD_REG(TX_CMD_FIFO)=0x00;`
281			`SD_REG(TX_CMD_FIFO)=0x01;`
282			`SD_REG(TX_CMD_FIFO)=0xAA;`
283
284			`//if response, card is v2.0 compatible, else reset card.`
285			`if (mmc_get_cmd_rsp(&response[0]) )`
286			`spv_2_0 = 1;`
287			`else`
288			`{`
289			`SD_REG(CONTROLL)=1;`
290			`SD_REG(CONTROLL)=0;`
291			`SD_REG(TX_CMD_FIFO)=0x40;`
292			`SD_REG(TX_CMD_FIFO)=0x00;`
293			`SD_REG(TX_CMD_FIFO)=0x00;`
294			`SD_REG(TX_CMD_FIFO)=0x00;`
295			`SD_REG(TX_CMD_FIFO)=0x00;`
296
297			`while ( SD_REG(TIMER_REG) != 0){}`
298			`}`
299
300			`if(spv_2_0==0)`
301			`{`
302			`//Send CMD55+ACMD41 until Busy bit is cleared (Response[0][8]==1)`
303			`while ( (rtn_reg & BUSY) != BUSY )`
304			`{ SD_REG(TX_CMD_FIFO)=0x77;`
305			`SD_REG(TX_CMD_FIFO)=0x00;`
306			`SD_REG(TX_CMD_FIFO)=0x00;`
307			`SD_REG(TX_CMD_FIFO)=0x00;`
308			`SD_REG(TX_CMD_FIFO)=0x00;`
309			`if ( mmc_get_cmd_rsp(&response[0]) && response[4]==0)`
310			`{`
311			`SD_REG(TX_CMD_FIFO)=0x69;`
312			`SD_REG(TX_CMD_FIFO)=0x00;`
313			`SD_REG(TX_CMD_FIFO)=0x00;`
314			`SD_REG(TX_CMD_FIFO)=0x00;`
315			`SD_REG(TX_CMD_FIFO)=0x00;`
316			`if (mmc_get_cmd_rsp(&response[0]))`
317			`rtn_reg = response[0];`
318			`else`
319			`return TRANSMISSION_FAILURE;`
320			`}`
321			`else`
322			`return TRANSMISSION_FAILURE;`
323			`}`
324
325			`}`
326			`//else Physical Specification Version 2.00`
327			`//Check response`
328			`//Initialization (ACMD41 HCS=1)`
329			`//Check for High Capacity or Standrd Capacity, Ver.2.00 Card`
330
331			`//CMD 2- get CSD, 136 bit response (Bit-40 this)`
332			`SD_REG(TX_CMD_FIFO)=0xC2;`
333			`SD_REG(TX_CMD_FIFO)=0x00;`
334			`SD_REG(TX_CMD_FIFO)=0x00;`
335			`SD_REG(TX_CMD_FIFO)=0x00;`
336			`SD_REG(TX_CMD_FIFO)=0x00;`
337
338			`if (!mmc_get_cmd_bigrsp(&response[0]))`
339			`return TRANSMISSION_FAILURE;`
340
341			`//CMD 3- get RCA nr`
342			`SD_REG(TX_CMD_FIFO)=0x43;`
343			`SD_REG(TX_CMD_FIFO)=0x00;`
344			`SD_REG(TX_CMD_FIFO)=0x00;`
345			`SD_REG(TX_CMD_FIFO)=0x00;`
346			`SD_REG(TX_CMD_FIFO)=0x00;`
347			`if (mmc_get_cmd_rsp(&response[0]))`
348			`{`
349			`rca[0] = response[0];`
350			`rca[1] = response[1];`
351			`}`
352			`else`
353			`return TRANSMISSION_FAILURE;`
354
355			`//Put card in transfer state, CMD 7`
356			`SD_REG(TX_CMD_FIFO)=0x47;`
357			`SD_REG(TX_CMD_FIFO)= rca[0] ;`
358			`SD_REG(TX_CMD_FIFO)= rca[1] ;`
359			`SD_REG(TX_CMD_FIFO)=0x0f;`
360			`SD_REG(TX_CMD_FIFO)=0x0f;`
361			`if (!mmc_get_cmd_rsp(&response[0]))`
362			`return TRANSMISSION_FAILURE;`
363
364			`//Set block size 512. CMD 16`
365			`SD_REG(TX_CMD_FIFO)=0x50;`
366			`SD_REG(TX_CMD_FIFO)=0;`
367			`SD_REG(TX_CMD_FIFO)=0;`
368			`SD_REG(TX_CMD_FIFO)=0x02;`
369			`SD_REG(TX_CMD_FIFO)=0;`
370			`if (!mmc_get_cmd_rsp(&response[0]))`
371			`return TRANSMISSION_FAILURE;`
372
373			`//Set bus width to 4. CMD 55 + ACMD 6`
374			`SD_REG(TX_CMD_FIFO)=0x77;`
375			`SD_REG(TX_CMD_FIFO)= rca[0] ;`
376			`SD_REG(TX_CMD_FIFO)= rca[1] ;`
377			`SD_REG(TX_CMD_FIFO)=0;`
378			`SD_REG(TX_CMD_FIFO)=0;`
379			`if (!mmc_get_cmd_rsp(&response[0]))`
380			`return TRANSMISSION_FAILURE;`
381			`// ACMD 6`
382			`SD_REG(TX_CMD_FIFO)=0x46;`
383			`SD_REG(TX_CMD_FIFO)=0;`
384			`SD_REG(TX_CMD_FIFO)=0;`
385			`SD_REG(TX_CMD_FIFO)=0;`
386			`SD_REG(TX_CMD_FIFO)=0x02;`
387			`if (!mmc_get_cmd_rsp(&response[0]))`
388			`return TRANSMISSION_FAILURE;`
389
390			`return TRANSMISSION_SUCCESSFUL;`
391			`}`
392
393
394			`int mmc_write_block(uint32 block_number)`
395			`{`
396			`uint32 var;`
397			`volatile unsigned char rtn_reg=0;`
398			`unsigned char response[4];`
399			`int i;`
400
401
402			`var= block_number << 9 ;`
403
404			`for (i=0; i < MMC_DATA_SIZE; i++)`
405			`SD_REG(TX_DATA_FIFO) = MMCWRData[i];`
406
407
408			`//Send CMD24, Single block write`
409			`SD_REG(TX_CMD_FIFO)=0x58;`
410			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 24) & 0xFF);`
411			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 16) & 0xFF);`
412			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 8) & 0xFF);`
413			`SD_REG(TX_CMD_FIFO)=(BYTE)(var & 0xFF);`
414			`if (!mmc_get_cmd_rsp(&response[0]))`
415			`return TRANSMISSION_FAILURE;`
416
417			`//Wait for TX_DATA_FIFO to get empty`
418			`while ( (SD_REG(STATUS)& 0x04) == 0x04) {}`
419			`//Wait for RX_DATA_FIFO to not get empty, indicate transmision is complete and CRC token is avaible.`
420			`while ( (SD_REG(STATUS) & 0x08) == 0x08) {}`
421
422			`//Check for correct CRC repsonse token == 0x29...`
423			`//Busy cehck is performed in HW`
424			`rtn_reg =SD_REG(RX_DATA_FIFO);`
425			`if ((rtn_reg & CRC_TOKEN) == CRC_TOKEN)`
426			`return TRANSMISSION_SUCCESSFUL;`
427			`else`
428			`return TRANSMISSION_FAILURE;`
429			`}`
430
431			`int mmc_read_block(uint32 block_number)`
432			`{`
433			`volatile int i = 0;`
434			`volatile unsigned char response[4];`
435			`volatile unsigned char rsp;`
436			`uint32 var;`
437			`WORD Checksum;`
438
439			`var= block_number << 9;`
440
441			`SD_REG(TX_CMD_FIFO)=0x51;`
442			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 24) & 0xFF);`
443			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 16) & 0xFF);`
444			`SD_REG(TX_CMD_FIFO)=(BYTE)((var >> 8) & 0xFF);`
445			`SD_REG(TX_CMD_FIFO)=(BYTE)(var & 0xFF);`
446			`if (!mmc_get_cmd_rsp(&response[0]))`
447			`return TRANSMISSION_FAILURE;`
448
449			`rsp = SD_REG(STATUS) & 0x08;`
450			`while ( rsp == 0x08) {`
451			`rsp = SD_REG(STATUS) & 0x08;}`
452			`//Checksum is notread`
453
454			`i=0;`
455
456			`/* while (i<MMC_DATA_SIZE){`
457
458			`MMCRDData[i]=SD_REG(RX_DATA_FIFO);`
459			`i++;`
460			`}`
461			`*/`
462
463			`BYTE *p;`
464			`p=&MMCRDData[0];`
465
466			`register int RX_REG asm ("r0") ;`
467			`register int RSP asm ("r6") ;`
468			`register int LOOP_END asm ("r2") ;`
469			`register int DAT_RSP asm ("r3") ;`
470
471			`register int SAVE_RX_REG asm ("r18") ;`
472			`register int SAVE_RSP asm ("r19") ;`
473			`register int SAVE_LOOP_END asm ("r20") ;`
474			`register int SAVE_DAT_RSP asm ("r21") ;`
475
476			`// asm volatile ("l.mtspr %0,%1, %2" : "=r"(RSP) : "m"(p), "i"(0));`
477			`// 10007f8: 19 80 01 00 l.movhi r12,0x100`
478			`//10007fc: a9 8c 34 10 l.ori r12,r12,0x3410`
479
480			`asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_RSP ) : "r"(RSP), "i"(0));`
481			`asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_RX_REG ) : "r"(RX_REG), "i"(0));`
482			`asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_LOOP_END ) : "r"(LOOP_END), "i"(0));`
483			`asm volatile ("l.addi %0,%1, %2" : "=r"(SAVE_DAT_RSP ) : "r"(DAT_RSP), "i"(0));`
484
485
486			`RSP=&MMCRDData[0];`
487			`// asm volatile ("l.movhi %0,%1" : "=r"(RSP) : "i"(0x100) );`
488			`//asm volatile ("l.ori %0,%1, %2" : "=r"(RSP) : "r"(RSP) , "i"(0x4db0) );`
489
490
491			`asm volatile ("l.movhi %0,%1" : "=r"(RX_REG) : "i"(0xa000) );`
492			`asm volatile ("l.ori %0,%1, %2" : "=r"(RX_REG) : "r"(RX_REG) , "i"(0xc) );`
493
494
495			`asm volatile ("l.addi %0,%1,%2" : "=r"(LOOP_END) : "r"(RSP) , "i"(0x200) );`
496
497			`asm ("label:");`
498			`asm volatile ("l.lwz %0,%1 %2" : "=r"(DAT_RSP) : "i"(0), "r"(RX_REG) );`
499			`asm volatile ("l.sb %0 %1, %2" : : "i"(0), "r"(RSP) , "r"(DAT_RSP) );`
500			`asm volatile ("l.addi %0,%1,%2" : "=r"(RSP) : "r"(RSP), "i"(0x1) );`
501
502			`asm volatile ("l.sfne %0,%1" : "=r"(RSP) :"r"(LOOP_END) );`
503
504			`asm volatile ("l.bf label" );`
505
506			`asm volatile ("l.nop");`
507			`asm volatile ("l.addi %0,%1, %2" : "=r"(RSP) : "r"(SAVE_RSP ), "i"(0));`
508			`asm volatile ("l.addi %0,%1, %2" : "=r"(RX_REG) : "r"(SAVE_RX_REG ), "i"(0));`
509			`asm volatile ("l.addi %0,%1, %2" : "=r"(LOOP_END ) : "r"(SAVE_LOOP_END), "i"(0));`
510			`asm volatile ("l.addi %0,%1, %2" : "=r"(DAT_RSP ) : "r"(SAVE_DAT_RSP), "i"(0));`
511
512
513			`return TRANSMISSION_SUCCESSFUL;`
514			`}`
515			`void Start()`
516			`{`
517			`volatile unsigned char rtn_reg=0;`
518			`volatile unsigned char response[16];`
519			`volatile int a;`
520			`volatile int i;`
521
522			`for (i=0;i<512;i++)`
523			`MMCWRData[i]=0xff;`
524
525			`uart_init();`
526			`a=mmc_init();`
527			`if (a)`
528			`uart_print_str("1");`
529			`else`
530			`uart_print_str("0");`
531
532			`// mmc_write_block(0);`
533			`mmc_read_block(0);`
534			`for (i=0;i<512;i++)`
535			`uart_print_long( MMCRDData[i]);`
536
537			`mmc_read_block(1);`
538			`for (i=0;i<512;i++)`
539			`uart_print_long( MMCRDData[i]);`
540
541
542			`}`