OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [Makefile] - Blame information for rev 188

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 14 rkastl
# Recursive makefile for simulations
2
 
3 179 rkastl
LIBS = libaltera_mf libcycloneii
4 137 rkastl
SIMS = grpCrc/unitCrc grpStrobesClocks/unitTimeoutGenerator
5 184 rkastl
SYSVSIMS = grpSdVerification/unitSdVerificationTestbench
6 137 rkastl
SYNS = grpSd/unitTbdSd
7 14 rkastl
 
8 188 rkastl
.PHONY: libs sim svsim syn clean
9
 
10 179 rkastl
all: clean libs sim svsim syn
11 178 rkastl
 
12 179 rkastl
libs:
13 186 rkastl
        for i in $(LIBS); do make -C $$i/sim; done
14 179 rkastl
 
15
sim: libs
16 186 rkastl
        for i in $(SIMS); do make -C $$i/sim; done
17 14 rkastl
 
18 179 rkastl
svsim: libs sim
19 186 rkastl
        for i in $(SYSVSIMS); do make -C $$i/sim; done
20 48 rkastl
 
21 15 rkastl
syn:
22 186 rkastl
        for i in $(SYNS); do make -C $$i/syn; done
23 15 rkastl
 
24 14 rkastl
clean:
25 186 rkastl
        for i in $(SIMS); do make -C $$i/sim clean; done
26
        for i in $(SYSVSIMS); do make -C $$i/sim clean; done
27
        for i in $(SYNS); do make -C $$i/syn clean; done
28
        for i in $(LIBS); do make -C $$i/sim clean; done
29 179 rkastl
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.