Subversion Repositories sdhc-sc-core

// SDHC-SC-Core

// Secure Digital High Capacity Self Configuring Core

//

// (C) Copyright 2010, Rainer Kastl

// All rights reserved.

//

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// modification, are permitted provided that the following conditions are met:

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//       notice, this list of conditions and the following disclaimer.

//     * Redistributions in binary form must reproduce the above copyright

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//       derived from this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND

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//

// File        : SdWb.sv

// Owner       : Rainer Kastl

// Description : SD Wishbone constants for SystemVerilog

// Links       :

//

`ifndef SDWB_SV

`define SDWB_SV

`include "WbTransaction.sv";

const WbData cOperationRead = 'h00000001;

const WbData cOperationWrite = 'h00000010;

const WbAddr cOperationAddr = 'b000;

const WbAddr cStartAddrAddr = 'b001;

const WbAddr cEndAddrAddr = 'b010;

const WbAddr cReadDataAddr = 'b011;

const WbAddr cWriteDataAddr = 'b100;

`endif