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rkastl |
-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdWbClkDomainSync-Rtl-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Synchronization between Sd and Wb clk domains
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Global.all;
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use work.Wishbone.all;
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use work.Sd.all;
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use work.SdWb.all;
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entity SdWbClkDomainSync is
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generic (
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gUseSameClocks : boolean := false
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);
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port (
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iWbClk : in std_ulogic;
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iWbRstSync : in std_ulogic;
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iSdClk : in std_ulogic;
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iSdRstSync : in std_ulogic;
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iWbCtrl : in aSdWbSlaveToSdController;
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iWbWriteFifo : in aoWriteFifo;
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iWbReadFifo : in aoReadFifo;
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iSdCtrl : in aSdControllerToSdWbSlave;
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iSdWriteFifo : in aoReadFifo;
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iSdReadFifo : in aoWriteFifo;
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oWbCtrlSync : out aSdControllerToSdWbSlave;
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oWbWriteFifo : out aiWriteFifo;
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oWbReadFifo : out aiReadFifo;
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oSdCtrlSync : out aSdWbSlaveToSdController;
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oSdWriteFifo : out aiReadFifo;
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oSdReadFifo : out aiWriteFifo
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);
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end entity SdWbClkDomainSync;
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architecture Rtl of SdWbClkDomainSync is
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signal ReadFifoQTemp : std_logic_vector(31 downto 0);
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signal WriteFifoQTemp : std_logic_vector(31 downto 0);
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begin
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SdWbControllerSync_inst: entity work.SdWbControllerSync
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generic map (
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gUseSameClocks => gUseSameClocks
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)
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port map (
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iWbClk => iWbClk,
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iWbRstSync => iWbRstSync,
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iSdClk => iSdClk,
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iSdRstSync => iSdRstSync,
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iSdWb => iWbCtrl,
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oSdWb => oWbCtrlSync,
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iSdController => iSdCtrl,
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oSdController => oSdCtrlSync
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);
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WriteDataFifo_inst: entity work.WriteDataFifo
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port map (
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data => std_logic_vector(iWbWriteFifo.data),
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rdclk => iSdClk,
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rdreq => iSdWriteFifo.rdreq,
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wrclk => iWbClk,
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wrreq => iWbWriteFifo.wrreq,
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q => ReadFifoQTemp,
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rdempty => oSdWriteFifo.rdempty,
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wrfull => oWbWriteFifo.wrfull
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);
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oSdWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
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ReadDataFifo_inst: entity work.WriteDataFifo
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port map (
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data => std_logic_vector(iSdReadFifo.data),
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rdclk => iWbClk,
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rdreq => iWbReadFifo.rdreq,
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wrclk => iSdClk,
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wrreq => iSdReadFifo.wrreq,
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q => WriteFifoQTemp,
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rdempty => oWbReadFifo.rdempty,
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wrfull => oSdReadFifo.wrfull
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);
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oWbReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
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end architecture Rtl;
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