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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : TestWbMaster-e.vhdl
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-- Owner : Rainer Kastl
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-- Description : Wishbone master for testing SDHC-SC-Core on the SbX
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity TestWbMaster is
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port (
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-- Wishbone interface
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CLK_I : in std_ulogic;
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RST_I : in std_ulogic;
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-- Wishbone master
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ERR_I : in std_ulogic;
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RTY_I : in std_ulogic;
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ACK_I : in std_ulogic;
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DAT_I : in std_ulogic_vector(31 downto 0);
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CYC_O : out std_ulogic;
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STB_O : out std_ulogic;
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WE_O : out std_ulogic;
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CTI_O : out std_ulogic_vector(2 downto 0);
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BTE_O : out std_ulogic_vector(1 downto 0);
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ADR_O : out std_ulogic_vector(6 downto 4);
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DAT_O : out std_ulogic_vector(31 downto 0);
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SEL_O : out std_ulogic_vector(0 downto 0);
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-- status signal
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LEDBANK_O : out std_ulogic_vector(7 downto 0)
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);
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end entity TestWbMaster;
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