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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : Wishbone-p.vhdl
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-- Owner : Rainer Kastl
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-- Description :
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-- Links :
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--
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-------------------------------------------------
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-- file: Wishbone-p.vhdl
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-- author: Rainer Kastl
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--
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-- Wishbone specific package.
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-- Wishbone specification revision B.3
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-------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package Wishbone is
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type aEndian is (big, little);
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subtype aCti is std_ulogic_vector(2 downto 0);
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constant cCtiClassicCycle : aCti := "000";
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constant cCtiConstAdrBurstCyc : aCti := "001";
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constant cCtiIncBurstCyc : aCti := "010";
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constant cCtiEndOfBurst : aCti := "111";
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subtype aBte is std_ulogic_vector(1 downto 0);
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constant cBteLinear : aBte := "00";
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constant cBteFourBeat : aBte := "01";
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constant cBteEightBeat : aBte := "10";
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constant cBteSixteenBeat : aBte := "11";
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-- Control inputs for a wishbone slave
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-- Unfortunately unconstrained types in records are only supported in
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-- VHDL2008, therefore signals with a range dependend on generics can not be
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-- put inside the record (iSel, iAdr, iDat).
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type aWbSlaveCtrlInput is record
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-- Control signals
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Cyc : std_ulogic; -- Indicates a bus cycle
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Lock : std_ulogic; -- Indicates that the current cycle is not interruptable
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Stb : std_ulogic; -- Indicates the selection of the slave
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We : std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle
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Cti : aCti; -- used for synchronous cycle termination
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Bte : aBte; -- Burst type extension
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end record;
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-- Control output signals of a wishbone slave
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-- See aWbSlaveCtrlInput for a explanation why oDat is not in the record.
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type aWbSlaveCtrlOutput is record
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-- Control signals
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Ack : std_ulogic; -- Indicates the end of a normal bus cycle
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Err : std_ulogic; -- Indicates an error
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Rty : std_ulogic; -- Indicates that the request should be retried
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end record;
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constant cDefaultWbSlaveCtrlOutput : aWbSlaveCtrlOutput := ('0','0','0');
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end package Wishbone;
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