1 |
123 |
rkastl |
-- Copyright (C) 1991-2010 Altera Corporation
|
2 |
|
|
-- Your use of Altera Corporation's design tools, logic functions
|
3 |
|
|
-- and other software and tools, and its AMPP partner logic
|
4 |
|
|
-- functions, and any output files from any of the foregoing
|
5 |
|
|
-- (including device programming or simulation files), and any
|
6 |
|
|
-- associated documentation or information are expressly subject
|
7 |
|
|
-- to the terms and conditions of the Altera Program License
|
8 |
|
|
-- Subscription Agreement, Altera MegaCore Function License
|
9 |
|
|
-- Agreement, or other applicable license agreement, including,
|
10 |
|
|
-- without limitation, that your use is for the sole purpose of
|
11 |
|
|
-- programming logic devices manufactured by Altera and sold by
|
12 |
|
|
-- Altera or its authorized distributors. Please refer to the
|
13 |
|
|
-- applicable agreement for further details.
|
14 |
|
|
-- Quartus II 9.1 Build 350 10/07/2009
|
15 |
|
|
|
16 |
|
|
LIBRARY IEEE;
|
17 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
18 |
|
|
use IEEE.VITAL_Timing.all;
|
19 |
|
|
use work.cycloneii_atom_pack.all;
|
20 |
|
|
|
21 |
|
|
package cycloneii_components is
|
22 |
|
|
|
23 |
|
|
|
24 |
|
|
--
|
25 |
|
|
-- cycloneii_ram_block
|
26 |
|
|
--
|
27 |
|
|
|
28 |
|
|
COMPONENT cycloneii_ram_block
|
29 |
|
|
GENERIC (
|
30 |
|
|
operation_mode : STRING := "single_port";
|
31 |
|
|
mixed_port_feed_through_mode : STRING := "dont_care";
|
32 |
|
|
ram_block_type : STRING := "auto";
|
33 |
|
|
logical_ram_name : STRING := "ram_name";
|
34 |
|
|
init_file : STRING := "init_file.hex";
|
35 |
|
|
init_file_layout : STRING := "none";
|
36 |
|
|
data_interleave_width_in_bits : INTEGER := 1;
|
37 |
|
|
data_interleave_offset_in_bits : INTEGER := 1;
|
38 |
|
|
port_a_logical_ram_depth : INTEGER := 0;
|
39 |
|
|
port_a_logical_ram_width : INTEGER := 0;
|
40 |
|
|
port_a_first_address : INTEGER := 0;
|
41 |
|
|
port_a_last_address : INTEGER := 0;
|
42 |
|
|
port_a_first_bit_number : INTEGER := 0;
|
43 |
|
|
port_a_data_in_clear : STRING := "none";
|
44 |
|
|
port_a_address_clear : STRING := "none";
|
45 |
|
|
port_a_write_enable_clear : STRING := "none";
|
46 |
|
|
port_a_data_out_clear : STRING := "none";
|
47 |
|
|
port_a_byte_enable_clear : STRING := "none";
|
48 |
|
|
port_a_data_in_clock : STRING := "clock0";
|
49 |
|
|
port_a_address_clock : STRING := "clock0";
|
50 |
|
|
port_a_write_enable_clock : STRING := "clock0";
|
51 |
|
|
port_a_byte_enable_clock : STRING := "clock0";
|
52 |
|
|
port_a_data_out_clock : STRING := "none";
|
53 |
|
|
port_a_data_width : INTEGER := 1;
|
54 |
|
|
port_a_address_width : INTEGER := 1;
|
55 |
|
|
port_a_byte_enable_mask_width : INTEGER := 1;
|
56 |
|
|
port_b_logical_ram_depth : INTEGER := 0;
|
57 |
|
|
port_b_logical_ram_width : INTEGER := 0;
|
58 |
|
|
port_b_first_address : INTEGER := 0;
|
59 |
|
|
port_b_last_address : INTEGER := 0;
|
60 |
|
|
port_b_first_bit_number : INTEGER := 0;
|
61 |
|
|
port_b_data_in_clear : STRING := "none";
|
62 |
|
|
port_b_address_clear : STRING := "none";
|
63 |
|
|
port_b_read_enable_write_enable_clear: STRING := "none";
|
64 |
|
|
port_b_byte_enable_clear : STRING := "none";
|
65 |
|
|
port_b_data_out_clear : STRING := "none";
|
66 |
|
|
port_b_data_in_clock : STRING := "clock1";
|
67 |
|
|
port_b_address_clock : STRING := "clock1";
|
68 |
|
|
port_b_read_enable_write_enable_clock: STRING := "clock1";
|
69 |
|
|
port_b_byte_enable_clock : STRING := "clock1";
|
70 |
|
|
port_b_data_out_clock : STRING := "none";
|
71 |
|
|
port_b_data_width : INTEGER := 1;
|
72 |
|
|
port_b_address_width : INTEGER := 1;
|
73 |
|
|
port_b_byte_enable_mask_width : INTEGER := 1;
|
74 |
|
|
power_up_uninitialized : STRING := "false";
|
75 |
|
|
port_b_disable_ce_on_output_registers : STRING := "off";
|
76 |
|
|
port_b_disable_ce_on_input_registers : STRING := "off";
|
77 |
|
|
port_b_byte_size : INTEGER := 0;
|
78 |
|
|
port_a_disable_ce_on_output_registers : STRING := "off";
|
79 |
|
|
port_a_disable_ce_on_input_registers : STRING := "off";
|
80 |
|
|
port_a_byte_size : INTEGER := 0;
|
81 |
|
|
safe_write : STRING := "err_on_2clk";
|
82 |
|
|
init_file_restructured : STRING := "unused";
|
83 |
|
|
lpm_type : string := "cycloneii_ram_block";
|
84 |
|
|
lpm_hint : string := "true";
|
85 |
|
|
mem_init0 : BIT_VECTOR := X"0";
|
86 |
|
|
mem_init1 : BIT_VECTOR := X"0";
|
87 |
|
|
connectivity_checking : string := "off"
|
88 |
|
|
);
|
89 |
|
|
PORT (
|
90 |
|
|
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
91 |
|
|
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
92 |
|
|
portawe : IN STD_LOGIC := '0';
|
93 |
|
|
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
94 |
|
|
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
95 |
|
|
portbrewe : IN STD_LOGIC := '0';
|
96 |
|
|
clk0 : IN STD_LOGIC := '0';
|
97 |
|
|
clk1 : IN STD_LOGIC := '0';
|
98 |
|
|
ena0 : IN STD_LOGIC := '1';
|
99 |
|
|
ena1 : IN STD_LOGIC := '1';
|
100 |
|
|
clr0 : IN STD_LOGIC := '0';
|
101 |
|
|
clr1 : IN STD_LOGIC := '0';
|
102 |
|
|
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
103 |
|
|
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
104 |
|
|
devclrn : IN STD_LOGIC := '1';
|
105 |
|
|
devpor : IN STD_LOGIC := '1';
|
106 |
|
|
portaaddrstall : IN STD_LOGIC := '0';
|
107 |
|
|
portbaddrstall : IN STD_LOGIC := '0';
|
108 |
|
|
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
109 |
|
|
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
|
110 |
|
|
);
|
111 |
|
|
END COMPONENT;
|
112 |
|
|
|
113 |
|
|
--
|
114 |
|
|
-- cycloneii_jtag
|
115 |
|
|
--
|
116 |
|
|
|
117 |
|
|
COMPONENT cycloneii_jtag
|
118 |
|
|
generic (
|
119 |
|
|
lpm_type : string := "cycloneii_jtag"
|
120 |
|
|
);
|
121 |
|
|
port (
|
122 |
|
|
tms : in std_logic := '0';
|
123 |
|
|
tck : in std_logic := '0';
|
124 |
|
|
tdi : in std_logic := '0';
|
125 |
|
|
ntrst : in std_logic := '0';
|
126 |
|
|
tdoutap : in std_logic := '0';
|
127 |
|
|
tdouser : in std_logic := '0';
|
128 |
|
|
tdo: out std_logic;
|
129 |
|
|
tmsutap: out std_logic;
|
130 |
|
|
tckutap: out std_logic;
|
131 |
|
|
tdiutap: out std_logic;
|
132 |
|
|
shiftuser: out std_logic;
|
133 |
|
|
clkdruser: out std_logic;
|
134 |
|
|
updateuser: out std_logic;
|
135 |
|
|
runidleuser: out std_logic;
|
136 |
|
|
usr1user: out std_logic
|
137 |
|
|
);
|
138 |
|
|
END COMPONENT;
|
139 |
|
|
|
140 |
|
|
--
|
141 |
|
|
-- cycloneii_crcblock
|
142 |
|
|
--
|
143 |
|
|
|
144 |
|
|
COMPONENT cycloneii_crcblock
|
145 |
|
|
generic (
|
146 |
|
|
oscillator_divider : integer := 1;
|
147 |
|
|
lpm_type : string := "cycloneii_crcblock"
|
148 |
|
|
);
|
149 |
|
|
port (
|
150 |
|
|
clk : in std_logic := '0';
|
151 |
|
|
shiftnld : in std_logic := '0';
|
152 |
|
|
ldsrc : in std_logic := '0';
|
153 |
|
|
crcerror : out std_logic;
|
154 |
|
|
regout : out std_logic
|
155 |
|
|
);
|
156 |
|
|
END COMPONENT;
|
157 |
|
|
|
158 |
|
|
--
|
159 |
|
|
-- cycloneii_asmiblock
|
160 |
|
|
--
|
161 |
|
|
|
162 |
|
|
COMPONENT cycloneii_asmiblock
|
163 |
|
|
generic (
|
164 |
|
|
lpm_type : string := "cycloneii_asmiblock"
|
165 |
|
|
);
|
166 |
|
|
port (dclkin : in std_logic;
|
167 |
|
|
scein : in std_logic;
|
168 |
|
|
sdoin : in std_logic;
|
169 |
|
|
oe : in std_logic;
|
170 |
|
|
data0out: out std_logic);
|
171 |
|
|
END COMPONENT;
|
172 |
|
|
|
173 |
|
|
--
|
174 |
|
|
-- cycloneii_pll
|
175 |
|
|
--
|
176 |
|
|
|
177 |
|
|
COMPONENT cycloneii_pll
|
178 |
|
|
GENERIC (
|
179 |
|
|
operation_mode : string := "normal";
|
180 |
|
|
pll_type : string := "auto"; -- EGPP/FAST/AUTO
|
181 |
|
|
compensate_clock : string := "clk0";
|
182 |
|
|
feedback_source : string := "clk0";
|
183 |
|
|
qualify_conf_done : string := "off";
|
184 |
|
|
test_input_comp_delay : integer := 0;
|
185 |
|
|
test_feedback_comp_delay : integer := 0;
|
186 |
|
|
inclk0_input_frequency : integer := 10000;
|
187 |
|
|
inclk1_input_frequency : integer := 10000;
|
188 |
|
|
gate_lock_signal : string := "no";
|
189 |
|
|
gate_lock_counter : integer := 1;
|
190 |
|
|
self_reset_on_gated_loss_lock : string := "off";
|
191 |
|
|
valid_lock_multiplier : integer := 1;
|
192 |
|
|
invalid_lock_multiplier : integer := 5;
|
193 |
|
|
sim_gate_lock_device_behavior : string := "off";
|
194 |
|
|
switch_over_type : string := "manual";
|
195 |
|
|
switch_over_on_lossclk : string := "off";
|
196 |
|
|
switch_over_on_gated_lock : string := "off";
|
197 |
|
|
switch_over_counter : integer := 1;
|
198 |
|
|
enable_switch_over_counter : string := "on";
|
199 |
|
|
bandwidth : integer := 0;
|
200 |
|
|
bandwidth_type : string := "auto";
|
201 |
|
|
down_spread : string := "0.0";
|
202 |
|
|
spread_frequency : integer := 0;
|
203 |
|
|
clk0_output_frequency : integer := 0;
|
204 |
|
|
clk0_multiply_by : integer := 1;
|
205 |
|
|
clk0_divide_by : integer := 1;
|
206 |
|
|
clk0_phase_shift : string := "0";
|
207 |
|
|
clk0_duty_cycle : integer := 50;
|
208 |
|
|
clk1_output_frequency : integer := 0;
|
209 |
|
|
clk1_multiply_by : integer := 1;
|
210 |
|
|
clk1_divide_by : integer := 1;
|
211 |
|
|
clk1_phase_shift : string := "0";
|
212 |
|
|
clk1_duty_cycle : integer := 50;
|
213 |
|
|
clk2_output_frequency : integer := 0;
|
214 |
|
|
clk2_multiply_by : integer := 1;
|
215 |
|
|
clk2_divide_by : integer := 1;
|
216 |
|
|
clk2_phase_shift : string := "0";
|
217 |
|
|
clk2_duty_cycle : integer := 50;
|
218 |
|
|
clk3_output_frequency : integer := 0;
|
219 |
|
|
clk3_multiply_by : integer := 1;
|
220 |
|
|
clk3_divide_by : integer := 1;
|
221 |
|
|
clk3_phase_shift : string := "0";
|
222 |
|
|
clk3_duty_cycle : integer := 50;
|
223 |
|
|
clk4_output_frequency : integer := 0;
|
224 |
|
|
clk4_multiply_by : integer := 1;
|
225 |
|
|
clk4_divide_by : integer := 1;
|
226 |
|
|
clk4_phase_shift : string := "0";
|
227 |
|
|
clk4_duty_cycle : integer := 50;
|
228 |
|
|
clk5_output_frequency : integer := 0;
|
229 |
|
|
clk5_multiply_by : integer := 1;
|
230 |
|
|
clk5_divide_by : integer := 1;
|
231 |
|
|
clk5_phase_shift : string := "0";
|
232 |
|
|
clk5_duty_cycle : integer := 50;
|
233 |
|
|
pfd_min : integer := 0;
|
234 |
|
|
pfd_max : integer := 0;
|
235 |
|
|
vco_min : integer := 0;
|
236 |
|
|
vco_max : integer := 0;
|
237 |
|
|
vco_center : integer := 0;
|
238 |
|
|
m_initial : integer := 1;
|
239 |
|
|
m : integer := 0;
|
240 |
|
|
n : integer := 1;
|
241 |
|
|
m2 : integer := 1;
|
242 |
|
|
n2 : integer := 1;
|
243 |
|
|
ss : integer := 0;
|
244 |
|
|
c0_high : integer := 1;
|
245 |
|
|
c0_low : integer := 1;
|
246 |
|
|
c0_initial : integer := 1;
|
247 |
|
|
c0_mode : string := "bypass";
|
248 |
|
|
c0_ph : integer := 0;
|
249 |
|
|
c1_high : integer := 1;
|
250 |
|
|
c1_low : integer := 1;
|
251 |
|
|
c1_initial : integer := 1;
|
252 |
|
|
c1_mode : string := "bypass";
|
253 |
|
|
c1_ph : integer := 0;
|
254 |
|
|
c2_high : integer := 1;
|
255 |
|
|
c2_low : integer := 1;
|
256 |
|
|
c2_initial : integer := 1;
|
257 |
|
|
c2_mode : string := "bypass";
|
258 |
|
|
c2_ph : integer := 0;
|
259 |
|
|
c3_high : integer := 1;
|
260 |
|
|
c3_low : integer := 1;
|
261 |
|
|
c3_initial : integer := 1;
|
262 |
|
|
c3_mode : string := "bypass";
|
263 |
|
|
c3_ph : integer := 0;
|
264 |
|
|
c4_high : integer := 1;
|
265 |
|
|
c4_low : integer := 1;
|
266 |
|
|
c4_initial : integer := 1;
|
267 |
|
|
c4_mode : string := "bypass";
|
268 |
|
|
c4_ph : integer := 0;
|
269 |
|
|
c5_high : integer := 1;
|
270 |
|
|
c5_low : integer := 1;
|
271 |
|
|
c5_initial : integer := 1;
|
272 |
|
|
c5_mode : string := "bypass";
|
273 |
|
|
c5_ph : integer := 0;
|
274 |
|
|
m_ph : integer := 0;
|
275 |
|
|
clk0_counter : string := "c0";
|
276 |
|
|
clk1_counter : string := "c1";
|
277 |
|
|
clk2_counter : string := "c2";
|
278 |
|
|
clk3_counter : string := "c3";
|
279 |
|
|
clk4_counter : string := "c4";
|
280 |
|
|
clk5_counter : string := "c5";
|
281 |
|
|
c1_use_casc_in : string := "off";
|
282 |
|
|
c2_use_casc_in : string := "off";
|
283 |
|
|
c3_use_casc_in : string := "off";
|
284 |
|
|
c4_use_casc_in : string := "off";
|
285 |
|
|
c5_use_casc_in : string := "off";
|
286 |
|
|
m_test_source : integer := 5;
|
287 |
|
|
c0_test_source : integer := 5;
|
288 |
|
|
c1_test_source : integer := 5;
|
289 |
|
|
c2_test_source : integer := 5;
|
290 |
|
|
c3_test_source : integer := 5;
|
291 |
|
|
c4_test_source : integer := 5;
|
292 |
|
|
c5_test_source : integer := 5;
|
293 |
|
|
enable0_counter : string := "c0";
|
294 |
|
|
enable1_counter : string := "c1";
|
295 |
|
|
sclkout0_phase_shift : string := "0";
|
296 |
|
|
sclkout1_phase_shift : string := "0";
|
297 |
|
|
charge_pump_current : integer := 52;
|
298 |
|
|
loop_filter_r : string := " 1.000000";
|
299 |
|
|
loop_filter_c : integer := 16;
|
300 |
|
|
use_vco_bypass : string := "false";
|
301 |
|
|
use_dc_coupling : string := "false";
|
302 |
|
|
pll_compensation_delay : integer := 0;
|
303 |
|
|
simulation_type : string := "functional";
|
304 |
|
|
lpm_type : string := "cycloneii_pll";
|
305 |
|
|
family_name : string := "CycloneII";
|
306 |
|
|
clk0_use_even_counter_mode : string := "off";
|
307 |
|
|
clk1_use_even_counter_mode : string := "off";
|
308 |
|
|
clk2_use_even_counter_mode : string := "off";
|
309 |
|
|
clk3_use_even_counter_mode : string := "off";
|
310 |
|
|
clk4_use_even_counter_mode : string := "off";
|
311 |
|
|
clk5_use_even_counter_mode : string := "off";
|
312 |
|
|
clk0_use_even_counter_value : string := "off";
|
313 |
|
|
clk1_use_even_counter_value : string := "off";
|
314 |
|
|
clk2_use_even_counter_value : string := "off";
|
315 |
|
|
clk3_use_even_counter_value : string := "off";
|
316 |
|
|
clk4_use_even_counter_value : string := "off";
|
317 |
|
|
clk5_use_even_counter_value : string := "off";
|
318 |
|
|
vco_multiply_by : integer := 0;
|
319 |
|
|
vco_divide_by : integer := 0;
|
320 |
|
|
vco_post_scale : integer := 1;
|
321 |
|
|
XOn : Boolean := DefGlitchXOn;
|
322 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
323 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
324 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
325 |
|
|
TimingChecksOn : Boolean := true;
|
326 |
|
|
InstancePath : STRING := "*";
|
327 |
|
|
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
328 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
329 |
|
|
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
|
330 |
|
|
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
331 |
|
|
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
|
332 |
|
|
);
|
333 |
|
|
PORT
|
334 |
|
|
(
|
335 |
|
|
inclk : in std_logic_vector(1 downto 0);
|
336 |
|
|
ena : in std_logic := '1';
|
337 |
|
|
clkswitch : in std_logic := '0';
|
338 |
|
|
areset : in std_logic := '0';
|
339 |
|
|
pfdena : in std_logic := '1';
|
340 |
|
|
testclearlock : in std_logic := '0';
|
341 |
|
|
sbdin : in std_logic := '0';
|
342 |
|
|
clk : out std_logic_vector(2 downto 0);
|
343 |
|
|
locked : out std_logic;
|
344 |
|
|
testupout : out std_logic;
|
345 |
|
|
testdownout : out std_logic;
|
346 |
|
|
sbdout : out std_logic
|
347 |
|
|
);
|
348 |
|
|
END COMPONENT;
|
349 |
|
|
|
350 |
|
|
--
|
351 |
|
|
-- cycloneii_routing_wire
|
352 |
|
|
--
|
353 |
|
|
|
354 |
|
|
COMPONENT cycloneii_routing_wire
|
355 |
|
|
generic (
|
356 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
357 |
|
|
XOn : Boolean := DefGlitchXOn;
|
358 |
|
|
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
359 |
|
|
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
|
360 |
|
|
tipd_datain : VitalDelayType01 := DefPropDelay01
|
361 |
|
|
);
|
362 |
|
|
PORT (
|
363 |
|
|
datain : in std_logic;
|
364 |
|
|
dataout : out std_logic
|
365 |
|
|
);
|
366 |
|
|
END COMPONENT;
|
367 |
|
|
|
368 |
|
|
--
|
369 |
|
|
-- cycloneii_lcell_ff
|
370 |
|
|
--
|
371 |
|
|
|
372 |
|
|
COMPONENT cycloneii_lcell_ff
|
373 |
|
|
generic (
|
374 |
|
|
x_on_violation : string := "on";
|
375 |
|
|
lpm_type : string := "cycloneii_lcell_ff";
|
376 |
|
|
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
377 |
|
|
tsetup_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
378 |
|
|
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
379 |
|
|
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
380 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
381 |
|
|
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
382 |
|
|
thold_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
383 |
|
|
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
384 |
|
|
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
385 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
386 |
|
|
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
|
387 |
|
|
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
|
388 |
|
|
tpd_sdata_regout: VitalDelayType01 := DefPropDelay01;
|
389 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
390 |
|
|
tipd_datain : VitalDelayType01 := DefPropDelay01;
|
391 |
|
|
tipd_sdata : VitalDelayType01 := DefPropDelay01;
|
392 |
|
|
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
393 |
|
|
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
394 |
|
|
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
395 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
396 |
|
|
TimingChecksOn: Boolean := True;
|
397 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
398 |
|
|
XOn: Boolean := DefGlitchXOn;
|
399 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
400 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
401 |
|
|
InstancePath: STRING := "*"
|
402 |
|
|
);
|
403 |
|
|
port (
|
404 |
|
|
datain : in std_logic := '0';
|
405 |
|
|
clk : in std_logic := '0';
|
406 |
|
|
aclr : in std_logic := '0';
|
407 |
|
|
sclr : in std_logic := '0';
|
408 |
|
|
sload : in std_logic := '0';
|
409 |
|
|
ena : in std_logic := '1';
|
410 |
|
|
sdata : in std_logic := '0';
|
411 |
|
|
devclrn : in std_logic := '1';
|
412 |
|
|
devpor : in std_logic := '1';
|
413 |
|
|
regout : out std_logic
|
414 |
|
|
);
|
415 |
|
|
END COMPONENT;
|
416 |
|
|
|
417 |
|
|
--
|
418 |
|
|
-- cycloneii_lcell_comb
|
419 |
|
|
--
|
420 |
|
|
|
421 |
|
|
COMPONENT cycloneii_lcell_comb
|
422 |
|
|
generic (
|
423 |
|
|
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
|
424 |
|
|
sum_lutc_input : string := "datac";
|
425 |
|
|
lpm_type : string := "cycloneii_lcell_comb";
|
426 |
|
|
TimingChecksOn: Boolean := True;
|
427 |
|
|
MsgOn: Boolean := DefGlitchMsgOn;
|
428 |
|
|
XOn: Boolean := DefGlitchXOn;
|
429 |
|
|
MsgOnChecks: Boolean := DefMsgOnChecks;
|
430 |
|
|
XOnChecks: Boolean := DefXOnChecks;
|
431 |
|
|
InstancePath: STRING := "*";
|
432 |
|
|
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
|
433 |
|
|
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
|
434 |
|
|
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
|
435 |
|
|
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
|
436 |
|
|
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
|
437 |
|
|
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
|
438 |
|
|
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
|
439 |
|
|
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
|
440 |
|
|
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
|
441 |
|
|
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
|
442 |
|
|
tipd_dataa : VitalDelayType01 := DefPropDelay01;
|
443 |
|
|
tipd_datab : VitalDelayType01 := DefPropDelay01;
|
444 |
|
|
tipd_datac : VitalDelayType01 := DefPropDelay01;
|
445 |
|
|
tipd_datad : VitalDelayType01 := DefPropDelay01;
|
446 |
|
|
tipd_cin : VitalDelayType01 := DefPropDelay01
|
447 |
|
|
);
|
448 |
|
|
port (
|
449 |
|
|
dataa : in std_logic := '1';
|
450 |
|
|
datab : in std_logic := '1';
|
451 |
|
|
datac : in std_logic := '1';
|
452 |
|
|
datad : in std_logic := '1';
|
453 |
|
|
cin : in std_logic := '0';
|
454 |
|
|
combout : out std_logic;
|
455 |
|
|
cout : out std_logic
|
456 |
|
|
);
|
457 |
|
|
END COMPONENT;
|
458 |
|
|
|
459 |
|
|
--
|
460 |
|
|
-- cycloneii_io
|
461 |
|
|
--
|
462 |
|
|
|
463 |
|
|
COMPONENT cycloneii_io
|
464 |
|
|
generic (
|
465 |
|
|
operation_mode : string := "input";
|
466 |
|
|
open_drain_output : string := "false";
|
467 |
|
|
bus_hold : string := "false";
|
468 |
|
|
output_register_mode : string := "none";
|
469 |
|
|
output_async_reset : string := "none";
|
470 |
|
|
output_sync_reset : string := "none";
|
471 |
|
|
output_power_up : string := "low";
|
472 |
|
|
tie_off_output_clock_enable : string := "false";
|
473 |
|
|
oe_register_mode : string := "none";
|
474 |
|
|
oe_async_reset : string := "none";
|
475 |
|
|
oe_sync_reset : string := "none";
|
476 |
|
|
oe_power_up : string := "low";
|
477 |
|
|
tie_off_oe_clock_enable : string := "false";
|
478 |
|
|
input_register_mode : string := "none";
|
479 |
|
|
input_async_reset : string := "none";
|
480 |
|
|
input_sync_reset : string := "none";
|
481 |
|
|
use_differential_input : string := "false";
|
482 |
|
|
lpm_type : string := "cycloneii_io";
|
483 |
|
|
input_power_up : string := "low");
|
484 |
|
|
port (
|
485 |
|
|
datain : in std_logic := '0';
|
486 |
|
|
oe : in std_logic := '1';
|
487 |
|
|
outclk : in std_logic := '0';
|
488 |
|
|
outclkena : in std_logic := '1';
|
489 |
|
|
inclk : in std_logic := '0';
|
490 |
|
|
inclkena : in std_logic := '1';
|
491 |
|
|
areset : in std_logic := '0';
|
492 |
|
|
sreset : in std_logic := '0';
|
493 |
|
|
devclrn : in std_logic := '1';
|
494 |
|
|
devpor : in std_logic := '1';
|
495 |
|
|
devoe : in std_logic := '1';
|
496 |
|
|
linkin : in std_logic := '0';
|
497 |
|
|
differentialin : in std_logic := '0';
|
498 |
|
|
differentialout : out std_logic;
|
499 |
|
|
linkout : out std_logic;
|
500 |
|
|
combout : out std_logic;
|
501 |
|
|
regout : out std_logic;
|
502 |
|
|
padio : inout std_logic
|
503 |
|
|
);
|
504 |
|
|
END COMPONENT;
|
505 |
|
|
|
506 |
|
|
--
|
507 |
|
|
-- cycloneii_clk_delay_ctrl
|
508 |
|
|
--
|
509 |
|
|
|
510 |
|
|
COMPONENT cycloneii_clk_delay_ctrl
|
511 |
|
|
generic (
|
512 |
|
|
behavioral_sim_delay : integer := 0;
|
513 |
|
|
delay_chain : STRING := "54";
|
514 |
|
|
delay_chain_mode : STRING := "static";
|
515 |
|
|
uses_calibration : STRING := "false";
|
516 |
|
|
use_new_style_dq_detection : STRING := "false";
|
517 |
|
|
tan_delay_under_delay_ctrl_signal : STRING := "unused";
|
518 |
|
|
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
519 |
|
|
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
520 |
|
|
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
521 |
|
|
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
522 |
|
|
lpm_type : STRING := "cycloneii_clk_delay_ctrl";
|
523 |
|
|
TimingChecksOn : Boolean := True;
|
524 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
525 |
|
|
XOn : Boolean := DefGlitchXOn;
|
526 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
527 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
528 |
|
|
InstancePath : STRING := "*";
|
529 |
|
|
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
|
530 |
|
|
tpd_disablecalibration_clkout : VitalDelayType01 := DefPropDelay01;
|
531 |
|
|
tpd_pllcalibrateclkdelayedin_clkout : VitalDelayType01 := DefPropDelay01;
|
532 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
533 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
534 |
|
|
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01;
|
535 |
|
|
tipd_pllcalibrateclkdelayedin : VitalDelayType01 := DefPropDelay01
|
536 |
|
|
);
|
537 |
|
|
port (
|
538 |
|
|
clk : in std_logic := '0';
|
539 |
|
|
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
|
540 |
|
|
disablecalibration : in std_logic := '1';
|
541 |
|
|
pllcalibrateclkdelayedin: in std_logic := '0';
|
542 |
|
|
devclrn : in std_logic := '1';
|
543 |
|
|
devpor : in std_logic := '1';
|
544 |
|
|
clkout : out std_logic
|
545 |
|
|
);
|
546 |
|
|
END COMPONENT;
|
547 |
|
|
|
548 |
|
|
--
|
549 |
|
|
-- cycloneii_clk_delay_cal_ctrl
|
550 |
|
|
--
|
551 |
|
|
|
552 |
|
|
COMPONENT cycloneii_clk_delay_cal_ctrl
|
553 |
|
|
generic (
|
554 |
|
|
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
555 |
|
|
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
556 |
|
|
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
557 |
|
|
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
|
558 |
|
|
lpm_type : STRING := "cycloneii_clk_delay_cal_ctrl";
|
559 |
|
|
TimingChecksOn : Boolean := True;
|
560 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
561 |
|
|
XOn : Boolean := DefGlitchXOn;
|
562 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
563 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
564 |
|
|
InstancePath : STRING := "*";
|
565 |
|
|
tpd_plldataclk_calibratedata : VitalDelayType01 := DefPropDelay01;
|
566 |
|
|
tpd_disablecalibration_calibratedata : VitalDelayType01 := DefPropDelay01;
|
567 |
|
|
tpd_pllcalibrateclk_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
|
568 |
|
|
tpd_disablecalibration_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
|
569 |
|
|
tipd_plldataclk : VitalDelayType01 := DefPropDelay01;
|
570 |
|
|
tipd_pllcalibrateclk : VitalDelayType01 := DefPropDelay01;
|
571 |
|
|
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
|
572 |
|
|
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01
|
573 |
|
|
);
|
574 |
|
|
port (
|
575 |
|
|
plldataclk : in std_logic := '0';
|
576 |
|
|
pllcalibrateclk : in std_logic := '0';
|
577 |
|
|
disablecalibration : in std_logic := '1';
|
578 |
|
|
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
|
579 |
|
|
devclrn : in std_logic := '1';
|
580 |
|
|
devpor : in std_logic := '1';
|
581 |
|
|
calibratedata : out std_logic;
|
582 |
|
|
pllcalibrateclkdelayedout : out std_logic
|
583 |
|
|
);
|
584 |
|
|
END COMPONENT;
|
585 |
|
|
|
586 |
|
|
--
|
587 |
|
|
-- cycloneii_mac_mult
|
588 |
|
|
--
|
589 |
|
|
|
590 |
|
|
COMPONENT cycloneii_mac_mult
|
591 |
|
|
GENERIC (
|
592 |
|
|
dataa_width : integer := 18;
|
593 |
|
|
datab_width : integer := 18;
|
594 |
|
|
dataa_clock : string := "none";
|
595 |
|
|
datab_clock : string := "none";
|
596 |
|
|
signa_clock : string := "none";
|
597 |
|
|
signb_clock : string := "none";
|
598 |
|
|
TimingChecksOn : Boolean := True;
|
599 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
600 |
|
|
XOn : Boolean := DefGlitchXOn;
|
601 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
602 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
603 |
|
|
InstancePath : STRING := "*";
|
604 |
|
|
lpm_hint : string := "true";
|
605 |
|
|
lpm_type : string := "cycloneii_mac_mult"
|
606 |
|
|
);
|
607 |
|
|
PORT (
|
608 |
|
|
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
|
609 |
|
|
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
|
610 |
|
|
signa : IN std_logic := '1';
|
611 |
|
|
signb : IN std_logic := '1';
|
612 |
|
|
clk : IN std_logic := '0';
|
613 |
|
|
aclr : IN std_logic := '0';
|
614 |
|
|
ena : IN std_logic := '0';
|
615 |
|
|
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
|
616 |
|
|
devclrn : IN std_logic := '1';
|
617 |
|
|
devpor : IN std_logic := '1'
|
618 |
|
|
);
|
619 |
|
|
END COMPONENT;
|
620 |
|
|
|
621 |
|
|
--
|
622 |
|
|
-- cycloneii_mac_out
|
623 |
|
|
--
|
624 |
|
|
|
625 |
|
|
COMPONENT cycloneii_mac_out
|
626 |
|
|
GENERIC (
|
627 |
|
|
dataa_width : integer := 1;
|
628 |
|
|
output_clock : string := "none";
|
629 |
|
|
TimingChecksOn : Boolean := True;
|
630 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
631 |
|
|
XOn : Boolean := DefGlitchXOn;
|
632 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
633 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
634 |
|
|
InstancePath : STRING := "*";
|
635 |
|
|
tipd_dataa : VitalDelayArrayType01(35 downto 0)
|
636 |
|
|
:= (OTHERS => DefPropDelay01);
|
637 |
|
|
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
638 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
639 |
|
|
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
640 |
|
|
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
|
641 |
|
|
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
|
642 |
|
|
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
|
643 |
|
|
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
|
644 |
|
|
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
|
645 |
|
|
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
646 |
|
|
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
647 |
|
|
lpm_hint : string := "true";
|
648 |
|
|
lpm_type : string := "cycloneii_mac_out");
|
649 |
|
|
PORT (
|
650 |
|
|
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
|
651 |
|
|
clk : IN std_logic := '0';
|
652 |
|
|
aclr : IN std_logic := '0';
|
653 |
|
|
ena : IN std_logic := '1';
|
654 |
|
|
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
|
655 |
|
|
devclrn : IN std_logic := '1';
|
656 |
|
|
devpor : IN std_logic := '1'
|
657 |
|
|
);
|
658 |
|
|
END COMPONENT;
|
659 |
|
|
|
660 |
|
|
--
|
661 |
|
|
-- cycloneii_clkctrl
|
662 |
|
|
--
|
663 |
|
|
|
664 |
|
|
COMPONENT cycloneii_clkctrl
|
665 |
|
|
generic (
|
666 |
|
|
clock_type : STRING := "Auto";
|
667 |
|
|
lpm_type : STRING := "cycloneii_clkctrl";
|
668 |
|
|
ena_register_mode : STRING := "Falling Edge";
|
669 |
|
|
TimingChecksOn : Boolean := True;
|
670 |
|
|
MsgOn : Boolean := DefGlitchMsgOn;
|
671 |
|
|
XOn : Boolean := DefGlitchXOn;
|
672 |
|
|
MsgOnChecks : Boolean := DefMsgOnChecks;
|
673 |
|
|
XOnChecks : Boolean := DefXOnChecks;
|
674 |
|
|
InstancePath : STRING := "*";
|
675 |
|
|
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
676 |
|
|
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
677 |
|
|
tipd_ena : VitalDelayType01 := DefPropDelay01
|
678 |
|
|
);
|
679 |
|
|
port (
|
680 |
|
|
inclk : in std_logic_vector(3 downto 0) := "0000";
|
681 |
|
|
clkselect : in std_logic_vector(1 downto 0) := "00";
|
682 |
|
|
ena : in std_logic := '1';
|
683 |
|
|
devclrn : in std_logic := '1';
|
684 |
|
|
devpor : in std_logic := '1';
|
685 |
|
|
outclk : out std_logic
|
686 |
|
|
);
|
687 |
|
|
END COMPONENT;
|
688 |
|
|
|
689 |
|
|
end cycloneii_components;
|