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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Blame information for rev 21

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Bank Controller
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description:
9
    This module takes requests from sdrc_req_gen, checks for page hit/miss and
10
    issues precharge/activate commands and then passes the request to sdrc_xfr_ctl.
11
 
12
  To Do:
13
    nothing
14
 
15
  Author(s):
16
      - Dinesh Annayya, dinesha@opencores.org
17
  Version  :  1.0  - 8th Jan 2012
18
 
19
 
20
 
21
 Copyright (C) 2000 Authors and OPENCORES.ORG
22
 
23
 This source file may be used and distributed without
24
 restriction provided that this copyright statement is not
25
 removed from the file and that any derivative work contains
26
 the original copyright notice and the associated disclaimer.
27
 
28
 This source file is free software; you can redistribute it
29
 and/or modify it under the terms of the GNU Lesser General
30
 Public License as published by the Free Software Foundation;
31
 either version 2.1 of the License, or (at your option) any
32
later version.
33
 
34
 This source is distributed in the hope that it will be
35
 useful, but WITHOUT ANY WARRANTY; without even the implied
36
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
37
 PURPOSE.  See the GNU Lesser General Public License for more
38
 details.
39
 
40
 You should have received a copy of the GNU Lesser General
41
 Public License along with this source; if not, download it
42
 from http://www.opencores.org/lgpl.shtml
43
 
44
*******************************************************************/
45
 
46
 
47
`include "sdrc.def"
48
 
49
module sdrc_bank_ctl (clk,
50
                     reset_n,
51 4 dinesha
                     a2b_req_depth,  // Number of requests we can buffer
52 3 dinesha
 
53
                     /* Req from req_gen */
54
                     r2b_req,      // request
55
                     r2b_req_id,   // ID
56
                     r2b_start,    // First chunk of burst
57
                     r2b_last,     // Last chunk of burst
58
                     r2b_wrap,
59 4 dinesha
                     r2b_ba,       // bank address
60 3 dinesha
                     r2b_raddr,    // row address
61
                     r2b_caddr,    // col address
62
                     r2b_len,      // length
63
                     r2b_write,    // write request
64 4 dinesha
                     b2r_arb_ok,   // OK to arbitrate for next xfr
65 3 dinesha
                     b2r_ack,
66
 
67
                     /* Transfer request to xfr_ctl */
68 4 dinesha
                     b2x_idle,     // All banks are idle
69 3 dinesha
                     b2x_req,      // Request to xfr_ctl
70
                     b2x_start,    // first chunk of transfer
71
                     b2x_last,     // last chunk of transfer
72
                     b2x_wrap,
73
                     b2x_id,       // Transfer ID
74 4 dinesha
                     b2x_ba,       // bank address
75 3 dinesha
                     b2x_addr,     // row/col address
76
                     b2x_len,      // transfer length
77
                     b2x_cmd,      // transfer command
78
                     x2b_ack,      // command accepted
79
 
80
                     /* Status to/from xfr_ctl */
81 4 dinesha
                     b2x_tras_ok,  // TRAS OK for all banks
82 3 dinesha
                     x2b_refresh,  // We did a refresh
83
                     x2b_pre_ok,   // OK to do a precharge (per bank)
84
                     x2b_act_ok,   // OK to do an activate
85
                     x2b_rdok,     // OK to do a read
86
                     x2b_wrok,     // OK to do a write
87
 
88 4 dinesha
                     /* xfr msb address */
89
                     xfr_bank_sel,
90
                     sdr_req_norm_dma_last,
91 3 dinesha
 
92
                     /* SDRAM Timing */
93
                     tras_delay,   // Active to precharge delay
94
                     trp_delay,    // Precharge to active delay
95
                     trcd_delay);  // Active to R/W delay
96
 
97
parameter  APP_AW   = 30;  // Application Address Width
98
parameter  APP_DW   = 32;  // Application Data Width 
99
parameter  APP_BW   = 4;   // Application Byte Width
100
parameter  APP_RW   = 9;   // Application Request Width
101
 
102
parameter  SDR_DW   = 16;  // SDR Data Width 
103
parameter  SDR_BW   = 2;   // SDR Byte Width
104
   input                        clk, reset_n;
105
 
106 4 dinesha
   input [1:0]                   a2b_req_depth;
107
 
108 3 dinesha
   /* Req from bank_ctl */
109
   input                        r2b_req, r2b_start, r2b_last,
110
                                r2b_write, r2b_wrap;
111
   input [`SDR_REQ_ID_W-1:0]     r2b_req_id;
112 4 dinesha
   input [1:0]                   r2b_ba;
113 3 dinesha
   input [11:0]          r2b_raddr;
114
   input [11:0]          r2b_caddr;
115 4 dinesha
   input [APP_RW-1:0]            r2b_len;
116
   output                       b2r_arb_ok, b2r_ack;
117
   input                        sdr_req_norm_dma_last;
118 3 dinesha
 
119
   /* Req to xfr_ctl */
120 4 dinesha
   output                       b2x_idle, b2x_req, b2x_start, b2x_last,
121
                                b2x_tras_ok, b2x_wrap;
122 3 dinesha
   output [`SDR_REQ_ID_W-1:0]    b2x_id;
123 4 dinesha
   output [1:0]          b2x_ba;
124 3 dinesha
   output [11:0]                 b2x_addr;
125
   output [APP_RW-1:0]   b2x_len;
126
   output [1:0]          b2x_cmd;
127
   input                        x2b_ack;
128
 
129
   /* Status from xfr_ctl */
130 4 dinesha
   input [3:0]                   x2b_pre_ok;
131 3 dinesha
   input                        x2b_refresh, x2b_act_ok, x2b_rdok,
132 4 dinesha
                                x2b_wrok;
133 3 dinesha
 
134
   input [3:0]                   tras_delay, trp_delay, trcd_delay;
135
 
136 4 dinesha
   input [1:0] xfr_bank_sel;
137 3 dinesha
 
138
   /****************************************************************************/
139
   // Internal Nets
140
 
141 4 dinesha
   wire [3:0]                    r2i_req, i2r_ack, i2x_req,
142
                                i2x_start, i2x_last, i2x_wrap, tras_ok;
143
   wire [11:0]                   i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
144
   wire [APP_RW-1:0]     i2x_len0, i2x_len1, i2x_len2, i2x_len3;
145
   wire [1:0]                    i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
146
   wire [`SDR_REQ_ID_W-1:0]      i2x_id0, i2x_id1, i2x_id2, i2x_id3;
147 3 dinesha
 
148 4 dinesha
   reg                          b2x_req;
149
   wire                         b2x_idle, b2x_start, b2x_last, b2x_wrap;
150 3 dinesha
   wire [`SDR_REQ_ID_W-1:0]      b2x_id;
151 4 dinesha
   wire [11:0]                   b2x_addr;
152 3 dinesha
   wire [APP_RW-1:0]     b2x_len;
153 4 dinesha
   wire [1:0]                    b2x_cmd;
154
   wire [3:0]                    x2i_ack;
155
   reg [1:0]                     b2x_ba;
156 3 dinesha
 
157 4 dinesha
   reg [`SDR_REQ_ID_W-1:0]       curr_id;
158
 
159
   wire [1:0]                    xfr_ba;
160
   wire                         xfr_ba_last;
161
   wire [3:0]                    xfr_ok;
162
 
163
   // This 8 bit register stores the bank addresses for upto 4 requests.
164
   reg [7:0]                     rank_ba;
165
   reg [3:0]                     rank_ba_last;
166
   // This 3 bit counter counts the number of requests we have
167
   // buffered so far, legal values are 0, 1, 2, 3, or 4.
168
   reg [2:0]                     rank_cnt;
169
   wire [3:0]                    rank_req, rank_wr_sel;
170
   wire                         rank_fifo_wr, rank_fifo_rd;
171
   wire                         rank_fifo_full, rank_fifo_mt;
172 3 dinesha
 
173 4 dinesha
   wire [11:0] bank0_row, bank1_row, bank2_row, bank3_row;
174 3 dinesha
 
175 4 dinesha
   assign b2x_tras_ok = &tras_ok;
176
 
177
   // Distribute the request from req_gen
178
 
179
   assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
180
   assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
181
   assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
182
   assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
183
 
184
   assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
185
                    (r2b_ba == 2'b01) ? i2r_ack[1] :
186
                    (r2b_ba == 2'b10) ? i2r_ack[2] :
187
                    (r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
188
 
189
   assign b2r_arb_ok = ~rank_fifo_full;
190
 
191
   // Put the requests from the 4 bank_fsms into a 4 deep shift
192
   // register file. The earliest request is prioritized over the
193
   // later requests. Also the number of requests we are allowed to
194
   // buffer is limited by a 2 bit external input
195
 
196
   // Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
197
   // rank0, allow only PR/ACT commands from the requests in other ranks
198
   // If the rank_fifo is empty, send the request from the bank addressed by
199
   // r2b_ba 
200
 
201
   assign xfr_ba = (rank_fifo_mt) ? r2b_ba : rank_ba[1:0];
202
   assign xfr_ba_last = (rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0];
203
 
204
   assign rank_req[0] = i2x_req[xfr_ba];     // each rank generates requests
205
 
206
   assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
207
                        (rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
208
                        (rank_ba[3:2] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
209
                        (rank_ba[3:2] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
210
                        i2x_req[3] & ~i2x_cmd3[1];
211
 
212
   assign rank_req[2] = (rank_cnt < 3'h3) ? 1'b0 :
213
                        (rank_ba[5:4] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
214
                        (rank_ba[5:4] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
215
                        (rank_ba[5:4] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
216
                        i2x_req[3] & ~i2x_cmd3[1];
217
 
218
   assign rank_req[3] = (rank_cnt < 3'h4) ? 1'b0 :
219
                        (rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
220
                        (rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
221
                        (rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
222
                        i2x_req[3] & ~i2x_cmd3[1];
223
 
224
   always @ (rank_req or rank_ba or xfr_ba or xfr_ba_last) begin
225
 
226
      if (rank_req[0]) begin
227
         b2x_req = 1'b1;
228
         b2x_ba = xfr_ba;
229
      end // if (rank_req[0])
230
 
231
      else if (rank_req[1]) begin
232
         b2x_req = 1'b1;
233
         b2x_ba = rank_ba[3:2];
234
      end // if (rank_req[1])
235
 
236
      else if (rank_req[2]) begin
237
         b2x_req = 1'b1;
238
         b2x_ba = rank_ba[5:4];
239
      end // if (rank_req[2])
240
 
241
      else if (rank_req[3]) begin
242
         b2x_req = 1'b1;
243
         b2x_ba = rank_ba[7:6];
244
      end // if (rank_req[3])
245
 
246
      else begin
247
         b2x_req = 1'b0;
248
         b2x_ba = 2'b00;
249
      end // else: !if(rank_req[3])
250
 
251
   end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
252
 
253
   assign b2x_idle = rank_fifo_mt;
254
   assign b2x_start = i2x_start[b2x_ba];
255
   assign b2x_last = i2x_last[b2x_ba];
256
   assign b2x_wrap = i2x_wrap[b2x_ba];
257
 
258
   assign b2x_addr = (b2x_ba == 2'b11) ? i2x_addr3 :
259
                     (b2x_ba == 2'b10) ? i2x_addr2 :
260
                     (b2x_ba == 2'b01) ? i2x_addr1 : i2x_addr0;
261
 
262
   assign b2x_len = (b2x_ba == 2'b11) ? i2x_len3 :
263
                    (b2x_ba == 2'b10) ? i2x_len2 :
264
                    (b2x_ba == 2'b01) ? i2x_len1 : i2x_len0;
265
 
266
   assign b2x_cmd = (b2x_ba == 2'b11) ? i2x_cmd3 :
267
                    (b2x_ba == 2'b10) ? i2x_cmd2 :
268
                    (b2x_ba == 2'b01) ? i2x_cmd1 : i2x_cmd0;
269
 
270
   assign b2x_id = (b2x_ba == 2'b11) ? i2x_id3 :
271
                   (b2x_ba == 2'b10) ? i2x_id2 :
272
                   (b2x_ba == 2'b01) ? i2x_id1 : i2x_id0;
273
 
274
   assign x2i_ack[0] = (b2x_ba == 2'b00) ? x2b_ack : 1'b0;
275
   assign x2i_ack[1] = (b2x_ba == 2'b01) ? x2b_ack : 1'b0;
276
   assign x2i_ack[2] = (b2x_ba == 2'b10) ? x2b_ack : 1'b0;
277
   assign x2i_ack[3] = (b2x_ba == 2'b11) ? x2b_ack : 1'b0;
278
 
279
   // Rank Fifo
280
   // On a write write to selected rank and increment rank_cnt
281
   // On a read shift rank_ba right 2 bits and decrement rank_cnt
282
 
283
   assign rank_fifo_wr = b2r_ack;
284
 
285
   assign rank_fifo_rd = b2x_req & b2x_cmd[1] & x2b_ack;
286
 
287
   assign rank_wr_sel[0] = (rank_cnt == 3'h0) ? rank_fifo_wr :
288
                           (rank_cnt == 3'h1) ? rank_fifo_wr & rank_fifo_rd :
289
                           1'b0;
290
 
291
   assign rank_wr_sel[1] = (rank_cnt == 3'h1) ? rank_fifo_wr & ~rank_fifo_rd :
292
                           (rank_cnt == 3'h2) ? rank_fifo_wr & rank_fifo_rd :
293
                           1'b0;
294
 
295
   assign rank_wr_sel[2] = (rank_cnt == 3'h2) ? rank_fifo_wr & ~rank_fifo_rd :
296
                           (rank_cnt == 3'h3) ? rank_fifo_wr & rank_fifo_rd :
297
                           1'b0;
298
 
299
   assign rank_wr_sel[3] = (rank_cnt == 3'h3) ? rank_fifo_wr & ~rank_fifo_rd :
300
                           (rank_cnt == 3'h4) ? rank_fifo_wr & rank_fifo_rd :
301
                           1'b0;
302
 
303
   assign rank_fifo_mt = (rank_cnt == 3'b0) ? 1'b1 : 1'b0;
304
 
305
   assign rank_fifo_full = (rank_cnt[2]) ? 1'b1 :
306
                           (rank_cnt[1:0] == a2b_req_depth) ? 1'b1 : 1'b0;
307
 
308
   // FIFO Check
309
 
310
   // synopsys translate_off
311
 
312
   always @ (posedge clk) begin
313
 
314
      if (~rank_fifo_wr & rank_fifo_rd && rank_cnt == 3'h0) begin
315
         $display ("%t: %m: ERROR!!! Read from empty Fifo", $time);
316
         $stop;
317
      end // if (rank_fifo_rd && rank_cnt == 3'h0)
318
 
319
      if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) begin
320
         $display ("%t: %m: ERROR!!! Write to full Fifo", $time);
321
         $stop;
322
      end // if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4)
323
 
324
   end // always @ (posedge clk)
325
 
326
   // synopsys translate_on
327
 
328 3 dinesha
   always @ (posedge clk)
329
      if (~reset_n) begin
330 4 dinesha
         rank_cnt <= 3'b0;
331
         rank_ba <= 8'b0;
332
         rank_ba_last <= 4'b0;
333
 
334 3 dinesha
      end // if (~reset_n)
335
      else begin
336
 
337 4 dinesha
         rank_cnt <= (rank_fifo_wr & ~rank_fifo_rd) ? rank_cnt + 3'b1 :
338
                     (~rank_fifo_wr & rank_fifo_rd) ? rank_cnt - 3'b1 :
339
                     rank_cnt;
340 3 dinesha
 
341 4 dinesha
         rank_ba[1:0] <= (rank_wr_sel[0]) ? r2b_ba :
342
                         (rank_fifo_rd) ? rank_ba[3:2] : rank_ba[1:0];
343 3 dinesha
 
344 4 dinesha
         rank_ba[3:2] <= (rank_wr_sel[1]) ? r2b_ba :
345
                         (rank_fifo_rd) ? rank_ba[5:4] : rank_ba[3:2];
346 3 dinesha
 
347 4 dinesha
         rank_ba[5:4] <= (rank_wr_sel[2]) ? r2b_ba :
348
                         (rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
349
 
350
         rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
351
                         (rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
352 3 dinesha
 
353 4 dinesha
         rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
354
                            (rank_fifo_rd) ?  rank_ba_last[1] : rank_ba_last[0];
355 3 dinesha
 
356 4 dinesha
         rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
357
                            (rank_fifo_rd) ?  rank_ba_last[2] : rank_ba_last[1];
358 3 dinesha
 
359 4 dinesha
         rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
360
                            (rank_fifo_rd) ?  rank_ba_last[3] : rank_ba_last[2];
361 3 dinesha
 
362 4 dinesha
         rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
363
                            (rank_fifo_rd) ?  1'b0 : rank_ba_last[3];
364 3 dinesha
 
365 4 dinesha
      end // else: !if(~reset_n)
366 3 dinesha
 
367 4 dinesha
   assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
368
   assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
369
   assign xfr_ok[2] = (xfr_ba == 2'b10) ? 1'b1 : 1'b0;
370
   assign xfr_ok[3] = (xfr_ba == 2'b11) ? 1'b1 : 1'b0;
371
 
372
   /****************************************************************************/
373
   // Instantiate Bank Ctl FSM 0
374 3 dinesha
 
375 4 dinesha
   sdrc_bank_fsm bank0_fsm (.clk (clk),
376
                           .reset_n (reset_n),
377 3 dinesha
 
378 4 dinesha
                           /* Req from req_gen */
379
                           .r2b_req (r2i_req[0]),
380
                           .r2b_req_id (r2b_req_id),
381
                           .r2b_start (r2b_start),
382
                           .r2b_last (r2b_last),
383
                           .r2b_wrap (r2b_wrap),
384
                           .r2b_raddr (r2b_raddr),
385
                           .r2b_caddr (r2b_caddr),
386
                           .r2b_len (r2b_len),
387
                           .r2b_write (r2b_write),
388
                           .b2r_ack (i2r_ack[0]),
389
                           .sdr_dma_last(rank_ba_last[0]),
390 3 dinesha
 
391 4 dinesha
                           /* Transfer request to xfr_ctl */
392
                           .b2x_req (i2x_req[0]),
393
                           .b2x_start (i2x_start[0]),
394
                           .b2x_last (i2x_last[0]),
395
                           .b2x_wrap (i2x_wrap[0]),
396
                           .b2x_id (i2x_id0),
397
                           .b2x_addr (i2x_addr0),
398
                           .b2x_len (i2x_len0),
399
                           .b2x_cmd (i2x_cmd0),
400
                           .x2b_ack (x2i_ack[0]),
401
 
402
                           /* Status to/from xfr_ctl */
403
                           .tras_ok (tras_ok[0]),
404
                           .xfr_ok (xfr_ok[0]),
405
                           .x2b_refresh (x2b_refresh),
406
                           .x2b_pre_ok (x2b_pre_ok[0]),
407
                           .x2b_act_ok (x2b_act_ok),
408
                           .x2b_rdok (x2b_rdok),
409
                           .x2b_wrok (x2b_wrok),
410 3 dinesha
 
411 4 dinesha
                           .bank_row(bank0_row),
412 3 dinesha
 
413 4 dinesha
                           /* SDRAM Timing */
414
                           .tras_delay (tras_delay),
415
                           .trp_delay (trp_delay),
416
                           .trcd_delay (trcd_delay));
417 3 dinesha
 
418 4 dinesha
   /****************************************************************************/
419
   // Instantiate Bank Ctl FSM 1
420 3 dinesha
 
421 4 dinesha
   sdrc_bank_fsm bank1_fsm (.clk (clk),
422
                           .reset_n (reset_n),
423 3 dinesha
 
424 4 dinesha
                           /* Req from req_gen */
425
                           .r2b_req (r2i_req[1]),
426
                           .r2b_req_id (r2b_req_id),
427
                           .r2b_start (r2b_start),
428
                           .r2b_last (r2b_last),
429
                           .r2b_wrap (r2b_wrap),
430
                           .r2b_raddr (r2b_raddr),
431
                           .r2b_caddr (r2b_caddr),
432
                           .r2b_len (r2b_len),
433
                           .r2b_write (r2b_write),
434
                           .b2r_ack (i2r_ack[1]),
435
                           .sdr_dma_last(rank_ba_last[1]),
436 3 dinesha
 
437 4 dinesha
                           /* Transfer request to xfr_ctl */
438
                           .b2x_req (i2x_req[1]),
439
                           .b2x_start (i2x_start[1]),
440
                           .b2x_last (i2x_last[1]),
441
                           .b2x_wrap (i2x_wrap[1]),
442
                           .b2x_id (i2x_id1),
443
                           .b2x_addr (i2x_addr1),
444
                           .b2x_len (i2x_len1),
445
                           .b2x_cmd (i2x_cmd1),
446
                           .x2b_ack (x2i_ack[1]),
447
 
448
                           /* Status to/from xfr_ctl */
449
                           .tras_ok (tras_ok[1]),
450
                           .xfr_ok (xfr_ok[1]),
451
                           .x2b_refresh (x2b_refresh),
452
                           .x2b_pre_ok (x2b_pre_ok[1]),
453
                           .x2b_act_ok (x2b_act_ok),
454
                           .x2b_rdok (x2b_rdok),
455
                           .x2b_wrok (x2b_wrok),
456 3 dinesha
 
457 4 dinesha
                           .bank_row(bank1_row),
458 3 dinesha
 
459 4 dinesha
                           /* SDRAM Timing */
460
                           .tras_delay (tras_delay),
461
                           .trp_delay (trp_delay),
462
                           .trcd_delay (trcd_delay));
463
 
464
   /****************************************************************************/
465
   // Instantiate Bank Ctl FSM 2
466 3 dinesha
 
467 4 dinesha
   sdrc_bank_fsm bank2_fsm (.clk (clk),
468
                           .reset_n (reset_n),
469 3 dinesha
 
470 4 dinesha
                           /* Req from req_gen */
471
                           .r2b_req (r2i_req[2]),
472
                           .r2b_req_id (r2b_req_id),
473
                           .r2b_start (r2b_start),
474
                           .r2b_last (r2b_last),
475
                           .r2b_wrap (r2b_wrap),
476
                           .r2b_raddr (r2b_raddr),
477
                           .r2b_caddr (r2b_caddr),
478
                           .r2b_len (r2b_len),
479
                           .r2b_write (r2b_write),
480
                           .b2r_ack (i2r_ack[2]),
481
                           .sdr_dma_last(rank_ba_last[2]),
482 3 dinesha
 
483 4 dinesha
                           /* Transfer request to xfr_ctl */
484
                           .b2x_req (i2x_req[2]),
485
                           .b2x_start (i2x_start[2]),
486
                           .b2x_last (i2x_last[2]),
487
                           .b2x_wrap (i2x_wrap[2]),
488
                           .b2x_id (i2x_id2),
489
                           .b2x_addr (i2x_addr2),
490
                           .b2x_len (i2x_len2),
491
                           .b2x_cmd (i2x_cmd2),
492
                           .x2b_ack (x2i_ack[2]),
493
 
494
                           /* Status to/from xfr_ctl */
495
                           .tras_ok (tras_ok[2]),
496
                           .xfr_ok (xfr_ok[2]),
497
                           .x2b_refresh (x2b_refresh),
498
                           .x2b_pre_ok (x2b_pre_ok[2]),
499
                           .x2b_act_ok (x2b_act_ok),
500
                           .x2b_rdok (x2b_rdok),
501
                           .x2b_wrok (x2b_wrok),
502 3 dinesha
 
503 4 dinesha
                           .bank_row(bank2_row),
504 3 dinesha
 
505 4 dinesha
                           /* SDRAM Timing */
506
                           .tras_delay (tras_delay),
507
                           .trp_delay (trp_delay),
508
                           .trcd_delay (trcd_delay));
509
 
510
   /****************************************************************************/
511
   // Instantiate Bank Ctl FSM 3
512 3 dinesha
 
513 4 dinesha
   sdrc_bank_fsm bank3_fsm (.clk (clk),
514
                           .reset_n (reset_n),
515 3 dinesha
 
516 4 dinesha
                           /* Req from req_gen */
517
                           .r2b_req (r2i_req[3]),
518
                           .r2b_req_id (r2b_req_id),
519
                           .r2b_start (r2b_start),
520
                           .r2b_last (r2b_last),
521
                           .r2b_wrap (r2b_wrap),
522
                           .r2b_raddr (r2b_raddr),
523
                           .r2b_caddr (r2b_caddr),
524
                           .r2b_len (r2b_len),
525
                           .r2b_write (r2b_write),
526
                           .b2r_ack (i2r_ack[3]),
527
                           .sdr_dma_last(rank_ba_last[3]),
528 3 dinesha
 
529 4 dinesha
                           /* Transfer request to xfr_ctl */
530
                           .b2x_req (i2x_req[3]),
531
                           .b2x_start (i2x_start[3]),
532
                           .b2x_last (i2x_last[3]),
533
                           .b2x_wrap (i2x_wrap[3]),
534
                           .b2x_id (i2x_id3),
535
                           .b2x_addr (i2x_addr3),
536
                           .b2x_len (i2x_len3),
537
                           .b2x_cmd (i2x_cmd3),
538
                           .x2b_ack (x2i_ack[3]),
539
 
540
                           /* Status to/from xfr_ctl */
541
                           .tras_ok (tras_ok[3]),
542
                           .xfr_ok (xfr_ok[3]),
543
                           .x2b_refresh (x2b_refresh),
544
                           .x2b_pre_ok (x2b_pre_ok[3]),
545
                           .x2b_act_ok (x2b_act_ok),
546
                           .x2b_rdok (x2b_rdok),
547
                           .x2b_wrok (x2b_wrok),
548 3 dinesha
 
549 4 dinesha
                           .bank_row(bank3_row),
550
 
551
                           /* SDRAM Timing */
552
                           .tras_delay (tras_delay),
553
                           .trp_delay (trp_delay),
554
                           .trcd_delay (trcd_delay));
555 3 dinesha
 
556 4 dinesha
 
557
/* address for current xfr, debug only */
558
wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
559
                        (xfr_bank_sel==2) ? bank2_row:
560
                        (xfr_bank_sel==1) ? bank1_row: bank0_row;
561
 
562
 
563
 
564
endmodule // sdr_bank_ctl

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