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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Blame information for rev 21

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1 3 dinesha
/*********************************************************************
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  SDRAM Controller buswidth converter
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  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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  Description: SDRAM Controller Buswidth converter
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  This module does write/read data transalation between
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     application data to SDRAM bus width
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  To Do:
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    nothing
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16
  Author(s):
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      - Dinesh Annayya, dinesha@opencores.org
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  Version  :  1.0  - 8th Jan 2012
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 Copyright (C) 2000 Authors and OPENCORES.ORG
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 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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`include "sdrc.def"
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module sdrc_bs_convert (
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                    clk,
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                    reset_n,
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                    sdr_width,
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                    app_req_addr,
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                    app_req_addr_int,
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                    app_req_len,
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                    app_req_len_int,
57 4 dinesha
                    app_sdr_req,
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                    app_sdr_req_int,
59 3 dinesha
                    app_req_dma_last,
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                    app_req_dma_last_int,
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                    app_req_wr_n,
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                    app_req_ack,
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                    app_req_ack_int,
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                    app_wr_data,
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                    app_wr_data_int,
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                    app_wr_en_n,
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                    app_wr_en_n_int,
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                    app_wr_next_int,
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                    app_wr_next,
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                    app_rd_data_int,
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                    app_rd_data,
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                    app_rd_valid_int,
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                    app_rd_valid
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                );
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parameter  APP_AW   = 30;  // Application Address Width
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parameter  APP_DW   = 32;  // Application Data Width 
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parameter  APP_BW   = 4;   // Application Byte Width
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parameter  APP_RW   = 9;   // Application Request Width
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parameter  SDR_DW   = 16;  // SDR Data Width 
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parameter  SDR_BW   = 2;   // SDR Byte Width
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input                    clk;
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input                    reset_n ;
87 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
88 3 dinesha
 
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input [APP_AW-1:0]       app_req_addr;
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output [APP_AW:0]        app_req_addr_int;
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input  [APP_RW-1:0]      app_req_len ;
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output [APP_RW-1:0]      app_req_len_int;
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input                    app_req_wr_n;
94 4 dinesha
input                    app_sdr_req;
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output                   app_sdr_req_int;
96 3 dinesha
input                    app_req_dma_last;
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output                   app_req_dma_last_int;
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input                    app_req_ack_int;
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output                   app_req_ack;
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input  [APP_DW-1:0]      app_wr_data;
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output [SDR_DW-1:0]      app_wr_data_int;
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input  [APP_BW-1:0]      app_wr_en_n;
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output [SDR_BW-1:0]      app_wr_en_n_int;
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input                    app_wr_next_int;
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output                   app_wr_next;
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input [SDR_DW-1:0]       app_rd_data_int;
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output [APP_DW-1:0]      app_rd_data;
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input                    app_rd_valid_int;
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output                   app_rd_valid;
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reg [APP_AW:0]           app_req_addr_int;
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reg [APP_RW-1:0]         app_req_len_int;
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reg                      app_req_dma_last_int;
117 4 dinesha
reg                      app_sdr_req_int;
118 3 dinesha
reg                      app_req_ack;
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reg [APP_DW-1:0]         app_rd_data;
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reg                      app_rd_valid;
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reg [SDR_DW-1:0]         app_wr_data_int;
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reg [SDR_BW-1:0]         app_wr_en_n_int;
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reg                      app_wr_next;
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126 16 dinesha
reg [23:0]               saved_rd_data;
127 3 dinesha
reg [7:0]                rd_xfr_count;
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reg [7:0]                wr_xfr_count;
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wire                  ok_to_req;
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133 16 dinesha
assign ok_to_req = ((wr_xfr_count == 0) && (rd_xfr_count == 0));
134 3 dinesha
 
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always @(*) begin
136 16 dinesha
        if(sdr_width == 2'b00) // 32 Bit SDR Mode
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          begin
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            app_req_addr_int = {1'b0,app_req_addr};
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            app_req_len_int = app_req_len;
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            app_wr_data_int = app_wr_data;
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            app_wr_en_n_int = app_wr_en_n;
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            app_req_dma_last_int = app_req_dma_last;
143 4 dinesha
            app_sdr_req_int = app_sdr_req;
144 3 dinesha
            app_wr_next = app_wr_next_int;
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            app_rd_data = app_rd_data_int;
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            app_rd_valid = app_rd_valid_int;
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            app_req_ack = app_req_ack_int;
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          end
149 16 dinesha
        else if(sdr_width == 2'b01) // 16 Bit SDR Mode
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        begin
151 3 dinesha
           // Changed the address and length to match the 16 bit SDR Mode
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            app_req_addr_int = {app_req_addr,1'b0};
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            app_req_len_int = {app_req_len,1'b0};
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            app_req_dma_last_int = app_req_dma_last;
155 4 dinesha
            app_sdr_req_int = app_sdr_req && ok_to_req;
156 3 dinesha
            app_req_ack = app_req_ack_int;
157 16 dinesha
            app_wr_next = (app_wr_next_int & wr_xfr_count[0]);
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            app_rd_valid = (rd_xfr_count & rd_xfr_count[0]);
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            if(wr_xfr_count[0] == 1'b1)
160 3 dinesha
              begin
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                app_wr_en_n_int = app_wr_en_n[3:2];
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                app_wr_data_int = app_wr_data[31:16];
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              end
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            else
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              begin
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                app_wr_en_n_int = app_wr_en_n[1:0];
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                app_wr_data_int = app_wr_data[15:0];
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              end
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170 16 dinesha
            app_rd_data = {app_rd_data_int,saved_rd_data[15:0]};
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        end else  // 8 Bit SDR Mode
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        begin
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           // Changed the address and length to match the 16 bit SDR Mode
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            app_req_addr_int = {app_req_addr,2'b0};
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            app_req_len_int = {app_req_len,2'b0};
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            app_req_dma_last_int = app_req_dma_last;
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            app_sdr_req_int = app_sdr_req && ok_to_req;
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            app_req_ack = app_req_ack_int;
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            app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b01));
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            app_rd_valid = (rd_xfr_count &   (rd_xfr_count[1:0]== 2'b01));
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            // Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00
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            if(wr_xfr_count[1:0] == 2'b01)
183 3 dinesha
            begin
184 16 dinesha
                app_wr_en_n_int = app_wr_en_n[3];
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                app_wr_data_int = app_wr_data[31:24];
186 3 dinesha
            end
187 16 dinesha
            else if(wr_xfr_count[1:0] == 2'b10)
188 3 dinesha
            begin
189 16 dinesha
                app_wr_en_n_int = app_wr_en_n[2];
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                app_wr_data_int = app_wr_data[23:16];
191 3 dinesha
            end
192 16 dinesha
            else if(wr_xfr_count[1:0] == 2'b11)
193 3 dinesha
            begin
194 16 dinesha
                app_wr_en_n_int = app_wr_en_n[1];
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                app_wr_data_int = app_wr_data[15:8];
196 3 dinesha
            end
197 16 dinesha
            else begin
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                app_wr_en_n_int = app_wr_en_n[0];
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                app_wr_data_int = app_wr_data[7:0];
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            end
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            app_rd_data = {app_rd_data_int,saved_rd_data[23:0]};
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          end
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     end
205 3 dinesha
 
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reg lcl_mc_req_wr_n;
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always @(posedge clk)
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  begin
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    if(!reset_n)
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      begin
213 16 dinesha
        rd_xfr_count    <= 8'b0;
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        wr_xfr_count    <= 8'b0;
215 3 dinesha
        lcl_mc_req_wr_n <= 1'b1;
216 16 dinesha
        saved_rd_data   <= 24'h0;
217 3 dinesha
      end
218 16 dinesha
    else begin
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        lcl_mc_req_wr_n <= app_req_wr_n;
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        // During Write Phase
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        if(app_req_ack && (app_req_wr_n == 0)) begin
223
           wr_xfr_count    <= app_req_len_int;
224 3 dinesha
        end
225 16 dinesha
        else if(app_wr_next_int & !lcl_mc_req_wr_n) begin
226 3 dinesha
           wr_xfr_count <= wr_xfr_count - 1'b1;
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        end
228 16 dinesha
 
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        // During Read Phase
230
        if(app_req_ack && app_req_wr_n) begin
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           rd_xfr_count    <= app_req_len_int;
232
        end
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        else if(app_rd_valid_int & lcl_mc_req_wr_n) begin
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           rd_xfr_count   <= rd_xfr_count - 1'b1;
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           if(sdr_width == 2'b01) // 16 Bit SDR Mode
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              saved_rd_data[15:0]  <= app_rd_data_int;
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            else begin// 8 bit SDR Mode - 
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                      // Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00
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               if(rd_xfr_count[1:0] == 2'b00)      saved_rd_data[7:0]   <= app_rd_data_int[7:0];
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               else if(rd_xfr_count[1:0] == 2'b11) saved_rd_data[15:8]  <= app_rd_data_int[7:0];
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               else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= app_rd_data_int[7:0];
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            end
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        end
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    end
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end
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247 3 dinesha
endmodule // sdr_bs_convert

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