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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Blame information for rev 4

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/*********************************************************************
 
  SDRAM Controller buswidth converter
 
  This file is part of the sdram controller project
  http://www.opencores.org/cores/sdr_ctrl/
 
  Description: SDRAM Controller Buswidth converter
 
  This module does write/read data transalation between
     application data to SDRAM bus width
 
  To Do:
    nothing
 
  Author(s):
      - Dinesh Annayya, dinesha@opencores.org
  Version  :  1.0  - 8th Jan 2012
 
 
 
 Copyright (C) 2000 Authors and OPENCORES.ORG
 
 This source file may be used and distributed without
 restriction provided that this copyright statement is not
 removed from the file and that any derivative work contains
 the original copyright notice and the associated disclaimer.
 
 This source file is free software; you can redistribute it
 and/or modify it under the terms of the GNU Lesser General
 Public License as published by the Free Software Foundation;
 either version 2.1 of the License, or (at your option) any
later version.
 
 This source is distributed in the hope that it will be
 useful, but WITHOUT ANY WARRANTY; without even the implied
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 PURPOSE.  See the GNU Lesser General Public License for more
 details.
 
 You should have received a copy of the GNU Lesser General
 Public License along with this source; if not, download it
 from http://www.opencores.org/lgpl.shtml
 
*******************************************************************/
 
`include "sdrc.def"
module sdrc_bs_convert (
                    clk,
                    reset_n,
                    sdr_width,
 
                    app_req_addr,
                    app_req_addr_int,
                    app_req_len,
                    app_req_len_int,
                    app_sdr_req,
                    app_sdr_req_int,
                    app_req_dma_last,
                    app_req_dma_last_int,
                    app_req_wr_n,
                    app_req_ack,
                    app_req_ack_int,
 
                    app_wr_data,
                    app_wr_data_int,
                    app_wr_en_n,
                    app_wr_en_n_int,
                    app_wr_next_int,
                    app_wr_next,
 
                    app_rd_data_int,
                    app_rd_data,
                    app_rd_valid_int,
                    app_rd_valid
                );
parameter  APP_AW   = 30;  // Application Address Width
parameter  APP_DW   = 32;  // Application Data Width 
parameter  APP_BW   = 4;   // Application Byte Width
parameter  APP_RW   = 9;   // Application Request Width
 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_BW   = 2;   // SDR Byte Width
 
input                    clk;
input                    reset_n ;
input                    sdr_width;
 
input [APP_AW-1:0]       app_req_addr;
output [APP_AW:0]        app_req_addr_int;
input  [APP_RW-1:0]      app_req_len ;
output [APP_RW-1:0]      app_req_len_int;
input                    app_req_wr_n;
input                    app_sdr_req;
output                   app_sdr_req_int;
input                    app_req_dma_last;
output                   app_req_dma_last_int;
input                    app_req_ack_int;
output                   app_req_ack;
 
input  [APP_DW-1:0]      app_wr_data;
output [SDR_DW-1:0]      app_wr_data_int;
input  [APP_BW-1:0]      app_wr_en_n;
output [SDR_BW-1:0]      app_wr_en_n_int;
input                    app_wr_next_int;
output                   app_wr_next;
 
input [SDR_DW-1:0]       app_rd_data_int;
output [APP_DW-1:0]      app_rd_data;
input                    app_rd_valid_int;
output                   app_rd_valid;
 
reg [APP_AW:0]           app_req_addr_int;
reg [APP_RW-1:0]         app_req_len_int;
 
reg                      app_req_dma_last_int;
reg                      app_sdr_req_int;
reg                      app_req_ack;
 
reg [APP_DW-1:0]         app_rd_data;
reg                      app_rd_valid;
reg [SDR_DW-1:0]         app_wr_data_int;
reg [SDR_BW-1:0]         app_wr_en_n_int;
reg                      app_wr_next;
 
reg                      lcl_rd_valid;
reg                      lcl_wr_next;
reg [15:0]               saved_rd_data;
reg                      save_lower;
reg                      upper_word;
reg                      write_upper;
reg [7:0]                rd_xfr_count;
reg [7:0]                wr_xfr_count;
 
reg [3:0]               rd_state,next_rd_state;
reg [3:0]               wr_state,next_wr_state;
 
parameter            SDR16_IDLE = 0,
                     SDR16_RD_LO = 1,
                     SDR16_RD_HI = 2,
                     SDR16_WR_LO = 3,
                     SDR16_WR_HI = 4;
wire                  ok_to_req;
 
assign ok_to_req = ((wr_state == SDR16_IDLE) && (rd_state == SDR16_IDLE));
 
always @(*) begin
        if(!sdr_width) // 32 Bit SDR Mode
          begin
            app_req_addr_int = {1'b0,app_req_addr};
            app_req_len_int = app_req_len;
            app_wr_data_int = app_wr_data;
            app_wr_en_n_int = app_wr_en_n;
            app_req_dma_last_int = app_req_dma_last;
            app_sdr_req_int = app_sdr_req;
            app_wr_next = app_wr_next_int;
            app_rd_data = app_rd_data_int;
            app_rd_valid = app_rd_valid_int;
            app_req_ack = app_req_ack_int;
          end
        else   // 16 Bit SDR Mode
          begin
           // Changed the address and length to match the 16 bit SDR Mode
            app_req_addr_int = {app_req_addr,1'b0};
            app_req_len_int = {app_req_len,1'b0};
            app_req_dma_last_int = app_req_dma_last;
            app_sdr_req_int = app_sdr_req && ok_to_req;
            app_req_ack = app_req_ack_int;
            app_wr_next = lcl_wr_next;
            app_rd_valid = lcl_rd_valid;
            if(write_upper)
              begin
                app_wr_en_n_int = app_wr_en_n[3:2];
                app_wr_data_int = app_wr_data[31:16];
              end
            else
              begin
                app_wr_en_n_int = app_wr_en_n[1:0];
                app_wr_data_int = app_wr_data[15:0];
              end
 
            app_rd_data = {app_rd_data_int[15:0],saved_rd_data};
          end
        end
 
//
// WRITES
//
always @(*) begin
 
        lcl_wr_next = 1'b0;
        upper_word = 1'b0;
        next_wr_state = wr_state;
 
        case(wr_state)
          SDR16_IDLE:
            begin
              if(app_req_ack_int && sdr_width)
                begin
                  if(~app_req_wr_n)
                    begin
                      next_wr_state = SDR16_WR_LO;
                    end
                end
              else
                begin
                  next_wr_state = SDR16_IDLE;
                end
            end
          SDR16_WR_LO:
            begin
              if(app_wr_next_int)
                begin
                  upper_word = 1'b1;
                  next_wr_state = SDR16_WR_HI;
                end
             end
          SDR16_WR_HI:
            begin
              if(app_wr_next_int)
                if(~(|wr_xfr_count))
                  begin
                    lcl_wr_next = 1'b1;
                    next_wr_state = SDR16_IDLE;
                  end
                else
                  begin
                    lcl_wr_next = 1'b1;
                    next_wr_state = SDR16_WR_LO;
                  end
            end
          default:
            begin
              next_wr_state = SDR16_IDLE;
            end
        endcase
        end
//
// READS
//
always @(*) begin
 
        lcl_rd_valid = 1'b0;
        save_lower = 1'b0;
        next_rd_state = rd_state;
 
        case(rd_state)
          SDR16_IDLE:
            begin
              if(app_req_ack_int && sdr_width)
                begin
                  if(app_req_wr_n)
                    begin
                      next_rd_state = SDR16_RD_LO;
                    end
                end
              else
                begin
                  next_rd_state = SDR16_IDLE;
                end
            end
          SDR16_RD_LO:
            begin
              if(app_rd_valid_int)
                begin
                  save_lower = 1'b1;
                  next_rd_state = SDR16_RD_HI;
                end
            end
          SDR16_RD_HI:
            begin
              if(app_rd_valid_int)
                if(~(|rd_xfr_count))
                  begin
                    lcl_rd_valid = 1'b1;
                    next_rd_state = SDR16_IDLE;
                  end
                else
                  begin
                    lcl_rd_valid = 1'b1;
                    next_rd_state = SDR16_RD_LO;
                  end
            end
          default:
            begin
              next_rd_state = SDR16_IDLE;
            end
        endcase
        end
 
reg lcl_mc_req_wr_n;
 
always @(posedge clk)
  begin
    if(!reset_n)
      begin
        rd_xfr_count <= 8'b0;
        wr_xfr_count <= 8'b0;
        lcl_mc_req_wr_n <= 1'b1;
      end
    else
      begin
        if(app_req_ack) begin
           wr_xfr_count    <= app_req_len - 1'b1;
           rd_xfr_count    <= app_req_len - 1'b1;
           lcl_mc_req_wr_n <= app_req_wr_n;
        end
        else if((lcl_wr_next & !lcl_mc_req_wr_n) || (lcl_rd_valid & lcl_mc_req_wr_n)) begin
           wr_xfr_count <= wr_xfr_count - 1'b1;
           rd_xfr_count <= rd_xfr_count - 1'b1;
        end
      end
  end
//
//
always @(posedge clk)
  begin
    if(!reset_n)
      begin
        rd_state      <= SDR16_IDLE;
        wr_state      <= SDR16_IDLE;
        saved_rd_data <= 16'b0;
        write_upper   <= 1'b0;
      end
    else
      begin
        rd_state        <= next_rd_state;
        wr_state        <= next_wr_state;
        if(save_lower)
          saved_rd_data <= app_rd_data_int[15:0];
        write_upper <= upper_word;
      end
  end
 
endmodule // sdr_bs_convert

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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	3	dinesha	`/*********************************************************************`
2
3			`SDRAM Controller buswidth converter`
4
5			`This file is part of the sdram controller project`
6			`http://www.opencores.org/cores/sdr_ctrl/`
7
8			`Description: SDRAM Controller Buswidth converter`
9
10			`This module does write/read data transalation between`
11			`application data to SDRAM bus width`
12
13			`To Do:`
14			`nothing`
15
16			`Author(s):`
17			`- Dinesh Annayya, dinesha@opencores.org`
18			`Version : 1.0 - 8th Jan 2012`
19
20
21
22			`Copyright (C) 2000 Authors and OPENCORES.ORG`
23
24			`This source file may be used and distributed without`
25			`restriction provided that this copyright statement is not`
26			`removed from the file and that any derivative work contains`
27			`the original copyright notice and the associated disclaimer.`
28
29			`This source file is free software; you can redistribute it`
30			`and/or modify it under the terms of the GNU Lesser General`
31			`Public License as published by the Free Software Foundation;`
32			`either version 2.1 of the License, or (at your option) any`
33			`later version.`
34
35			`This source is distributed in the hope that it will be`
36			`useful, but WITHOUT ANY WARRANTY; without even the implied`
37			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
38			`PURPOSE. See the GNU Lesser General Public License for more`
39			`details.`
40
41			`You should have received a copy of the GNU Lesser General`
42			`Public License along with this source; if not, download it`
43			`from http://www.opencores.org/lgpl.shtml`
44
45			`*******************************************************************/`
46
47			`include "sdrc.def"
48			`module sdrc_bs_convert (`
49			`clk,`
50			`reset_n,`
51			`sdr_width,`
52
53			`app_req_addr,`
54			`app_req_addr_int,`
55			`app_req_len,`
56			`app_req_len_int,`
57	4	dinesha	`app_sdr_req,`
58			`app_sdr_req_int,`
59	3	dinesha	`app_req_dma_last,`
60			`app_req_dma_last_int,`
61			`app_req_wr_n,`
62			`app_req_ack,`
63			`app_req_ack_int,`
64
65			`app_wr_data,`
66			`app_wr_data_int,`
67			`app_wr_en_n,`
68			`app_wr_en_n_int,`
69			`app_wr_next_int,`
70			`app_wr_next,`
71
72			`app_rd_data_int,`
73			`app_rd_data,`
74			`app_rd_valid_int,`
75			`app_rd_valid`
76			`);`
77			`parameter APP_AW = 30; // Application Address Width`
78			`parameter APP_DW = 32; // Application Data Width`
79			`parameter APP_BW = 4; // Application Byte Width`
80			`parameter APP_RW = 9; // Application Request Width`
81
82			`parameter SDR_DW = 16; // SDR Data Width`
83			`parameter SDR_BW = 2; // SDR Byte Width`
84
85			`input clk;`
86			`input reset_n ;`
87			`input sdr_width;`
88
89			`input [APP_AW-1:0] app_req_addr;`
90			`output [APP_AW:0] app_req_addr_int;`
91			`input [APP_RW-1:0] app_req_len ;`
92			`output [APP_RW-1:0] app_req_len_int;`
93			`input app_req_wr_n;`
94	4	dinesha	`input app_sdr_req;`
95			`output app_sdr_req_int;`
96	3	dinesha	`input app_req_dma_last;`
97			`output app_req_dma_last_int;`
98			`input app_req_ack_int;`
99			`output app_req_ack;`
100
101			`input [APP_DW-1:0] app_wr_data;`
102			`output [SDR_DW-1:0] app_wr_data_int;`
103			`input [APP_BW-1:0] app_wr_en_n;`
104			`output [SDR_BW-1:0] app_wr_en_n_int;`
105			`input app_wr_next_int;`
106			`output app_wr_next;`
107
108			`input [SDR_DW-1:0] app_rd_data_int;`
109			`output [APP_DW-1:0] app_rd_data;`
110			`input app_rd_valid_int;`
111			`output app_rd_valid;`
112
113			`reg [APP_AW:0] app_req_addr_int;`
114			`reg [APP_RW-1:0] app_req_len_int;`
115
116			`reg app_req_dma_last_int;`
117	4	dinesha	`reg app_sdr_req_int;`
118	3	dinesha	`reg app_req_ack;`
119
120			`reg [APP_DW-1:0] app_rd_data;`
121			`reg app_rd_valid;`
122			`reg [SDR_DW-1:0] app_wr_data_int;`
123			`reg [SDR_BW-1:0] app_wr_en_n_int;`
124			`reg app_wr_next;`
125
126			`reg lcl_rd_valid;`
127			`reg lcl_wr_next;`
128			`reg [15:0] saved_rd_data;`
129			`reg save_lower;`
130			`reg upper_word;`
131			`reg write_upper;`
132			`reg [7:0] rd_xfr_count;`
133			`reg [7:0] wr_xfr_count;`
134
135			`reg [3:0] rd_state,next_rd_state;`
136			`reg [3:0] wr_state,next_wr_state;`
137
138			`parameter SDR16_IDLE = 0,`
139			`SDR16_RD_LO = 1,`
140			`SDR16_RD_HI = 2,`
141			`SDR16_WR_LO = 3,`
142			`SDR16_WR_HI = 4;`
143			`wire ok_to_req;`
144
145			`assign ok_to_req = ((wr_state == SDR16_IDLE) && (rd_state == SDR16_IDLE));`
146
147			`always @(*) begin`
148			`if(!sdr_width) // 32 Bit SDR Mode`
149			`begin`
150			`app_req_addr_int = {1'b0,app_req_addr};`
151			`app_req_len_int = app_req_len;`
152			`app_wr_data_int = app_wr_data;`
153			`app_wr_en_n_int = app_wr_en_n;`
154			`app_req_dma_last_int = app_req_dma_last;`
155	4	dinesha	`app_sdr_req_int = app_sdr_req;`
156	3	dinesha	`app_wr_next = app_wr_next_int;`
157			`app_rd_data = app_rd_data_int;`
158			`app_rd_valid = app_rd_valid_int;`
159			`app_req_ack = app_req_ack_int;`
160			`end`
161			`else // 16 Bit SDR Mode`
162			`begin`
163			`// Changed the address and length to match the 16 bit SDR Mode`
164			`app_req_addr_int = {app_req_addr,1'b0};`
165			`app_req_len_int = {app_req_len,1'b0};`
166			`app_req_dma_last_int = app_req_dma_last;`
167	4	dinesha	`app_sdr_req_int = app_sdr_req && ok_to_req;`
168	3	dinesha	`app_req_ack = app_req_ack_int;`
169			`app_wr_next = lcl_wr_next;`
170			`app_rd_valid = lcl_rd_valid;`
171			`if(write_upper)`
172			`begin`
173			`app_wr_en_n_int = app_wr_en_n[3:2];`
174			`app_wr_data_int = app_wr_data[31:16];`
175			`end`
176			`else`
177			`begin`
178			`app_wr_en_n_int = app_wr_en_n[1:0];`
179			`app_wr_data_int = app_wr_data[15:0];`
180			`end`
181
182			`app_rd_data = {app_rd_data_int[15:0],saved_rd_data};`
183			`end`
184			`end`
185
186			`//`
187			`// WRITES`
188			`//`
189			`always @(*) begin`
190
191			`lcl_wr_next = 1'b0;`
192			`upper_word = 1'b0;`
193			`next_wr_state = wr_state;`
194
195			`case(wr_state)`
196			`SDR16_IDLE:`
197			`begin`
198			`if(app_req_ack_int && sdr_width)`
199			`begin`
200			`if(~app_req_wr_n)`
201			`begin`
202			`next_wr_state = SDR16_WR_LO;`
203			`end`
204			`end`
205			`else`
206			`begin`
207			`next_wr_state = SDR16_IDLE;`
208			`end`
209			`end`
210			`SDR16_WR_LO:`
211			`begin`
212	4	dinesha	`if(app_wr_next_int)`
213	3	dinesha	`begin`
214			`upper_word = 1'b1;`
215			`next_wr_state = SDR16_WR_HI;`
216			`end`
217			`end`
218			`SDR16_WR_HI:`
219			`begin`
220			`if(app_wr_next_int)`
221			`if(~(\|wr_xfr_count))`
222			`begin`
223			`lcl_wr_next = 1'b1;`
224			`next_wr_state = SDR16_IDLE;`
225			`end`
226			`else`
227			`begin`
228			`lcl_wr_next = 1'b1;`
229			`next_wr_state = SDR16_WR_LO;`
230			`end`
231			`end`
232			`default:`
233			`begin`
234			`next_wr_state = SDR16_IDLE;`
235			`end`
236			`endcase`
237			`end`
238			`//`
239			`// READS`
240			`//`
241			`always @(*) begin`
242
243			`lcl_rd_valid = 1'b0;`
244			`save_lower = 1'b0;`
245			`next_rd_state = rd_state;`
246
247			`case(rd_state)`
248			`SDR16_IDLE:`
249			`begin`
250			`if(app_req_ack_int && sdr_width)`
251			`begin`
252			`if(app_req_wr_n)`
253			`begin`
254			`next_rd_state = SDR16_RD_LO;`
255			`end`
256			`end`
257			`else`
258			`begin`
259			`next_rd_state = SDR16_IDLE;`
260			`end`
261			`end`
262			`SDR16_RD_LO:`
263			`begin`
264			`if(app_rd_valid_int)`
265			`begin`
266			`save_lower = 1'b1;`
267			`next_rd_state = SDR16_RD_HI;`
268			`end`
269			`end`
270			`SDR16_RD_HI:`
271			`begin`
272			`if(app_rd_valid_int)`
273			`if(~(\|rd_xfr_count))`
274			`begin`
275			`lcl_rd_valid = 1'b1;`
276			`next_rd_state = SDR16_IDLE;`
277			`end`
278			`else`
279			`begin`
280			`lcl_rd_valid = 1'b1;`
281			`next_rd_state = SDR16_RD_LO;`
282			`end`
283			`end`
284			`default:`
285			`begin`
286			`next_rd_state = SDR16_IDLE;`
287			`end`
288			`endcase`
289			`end`
290
291			`reg lcl_mc_req_wr_n;`
292
293			`always @(posedge clk)`
294			`begin`
295			`if(!reset_n)`
296			`begin`
297			`rd_xfr_count <= 8'b0;`
298			`wr_xfr_count <= 8'b0;`
299			`lcl_mc_req_wr_n <= 1'b1;`
300			`end`
301			`else`
302			`begin`
303			`if(app_req_ack) begin`
304			`wr_xfr_count <= app_req_len - 1'b1;`
305			`rd_xfr_count <= app_req_len - 1'b1;`
306			`lcl_mc_req_wr_n <= app_req_wr_n;`
307			`end`
308			`else if((lcl_wr_next & !lcl_mc_req_wr_n) \|\| (lcl_rd_valid & lcl_mc_req_wr_n)) begin`
309			`wr_xfr_count <= wr_xfr_count - 1'b1;`
310			`rd_xfr_count <= rd_xfr_count - 1'b1;`
311			`end`
312			`end`
313			`end`
314			`//`
315			`//`
316			`always @(posedge clk)`
317			`begin`
318			`if(!reset_n)`
319			`begin`
320			`rd_state <= SDR16_IDLE;`
321			`wr_state <= SDR16_IDLE;`
322			`saved_rd_data <= 16'b0;`
323			`write_upper <= 1'b0;`
324			`end`
325			`else`
326			`begin`
327			`rd_state <= next_rd_state;`
328			`wr_state <= next_wr_state;`
329			`if(save_lower)`
330			`saved_rd_data <= app_rd_data_int[15:0];`
331			`write_upper <= upper_word;`
332			`end`
333			`end`
334
335			`endmodule // sdr_bs_convert`