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/*********************************************************************
 
  SDRAM Controller buswidth converter
 
  This file is part of the sdram controller project
  http://www.opencores.org/cores/sdr_ctrl/
 
  Description: SDRAM Controller Buswidth converter
 
  This module does write/read data transalation between
     application data to SDRAM bus width
 
  To Do:
    nothing
 
  Author(s):
      - Dinesh Annayya, dinesha@opencores.org
  Version  :  0.0  - 8th Jan 2012 - Initial structure
              0.2 - 2nd Feb 2012
                 Improved the command pipe structure to accept up-to 4 command of different bank.
              0.3 - 6th Feb 2012
                 Bug fix on read valid generation
 
 
 
 Copyright (C) 2000 Authors and OPENCORES.ORG
 
 This source file may be used and distributed without
 restriction provided that this copyright statement is not
 removed from the file and that any derivative work contains
 the original copyright notice and the associated disclaimer.
 
 This source file is free software; you can redistribute it
 and/or modify it under the terms of the GNU Lesser General
 Public License as published by the Free Software Foundation;
 either version 2.1 of the License, or (at your option) any
later version.
 
 This source is distributed in the hope that it will be
 useful, but WITHOUT ANY WARRANTY; without even the implied
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 PURPOSE.  See the GNU Lesser General Public License for more
 details.
 
 You should have received a copy of the GNU Lesser General
 Public License along with this source; if not, download it
 from http://www.opencores.org/lgpl.shtml
 
*******************************************************************/
 
`include "sdrc_define.v"
module sdrc_bs_convert (
                    clk                 ,
                    reset_n             ,
                    sdr_width           ,
 
        /* Control Signal from xfr ctrl */
                    x2a_rdstart         ,
                    x2a_wrstart         ,
                    x2a_rdlast          ,
                    x2a_wrlast          ,
                    x2a_rddt            ,
                    x2a_rdok            ,
                    a2x_wrdt            ,
                    a2x_wren_n          ,
                    x2a_wrnext          ,
 
   /*  Control Signal from/to to application i/f  */
                    app_wr_data         ,
                    app_wr_en_n         ,
                    app_wr_next         ,
                    app_last_wr         ,
                    app_rd_data         ,
                    app_rd_valid        ,
                    app_last_rd
                );
 
 
parameter  APP_AW   = 30;  // Application Address Width
parameter  APP_DW   = 32;  // Application Data Width 
parameter  APP_BW   = 4;   // Application Byte Width
 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_BW   = 2;   // SDR Byte Width
 
input                    clk              ;
input                    reset_n          ;
input [1:0]              sdr_width        ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 
/* Control Signal from xfr ctrl Read Transaction*/
input                    x2a_rdstart      ; // read start indication
input                    x2a_rdlast       ; //  read last burst access
input [SDR_DW-1:0]       x2a_rddt         ;
input                    x2a_rdok         ;
 
/* Control Signal from xfr ctrl Write Transaction*/
input                    x2a_wrstart      ; // writ start indication
input                    x2a_wrlast       ; // write last transfer
input                    x2a_wrnext       ;
output [SDR_DW-1:0]      a2x_wrdt         ;
output [SDR_BW-1:0]      a2x_wren_n       ;
 
// Application Write Transaction
input  [APP_DW-1:0]      app_wr_data      ;
input  [APP_BW-1:0]      app_wr_en_n      ;
output                   app_wr_next      ;
output                   app_last_wr      ; // Indicate last Write Transfer for a given burst size
 
// Application Read Transaction
output [APP_DW-1:0]      app_rd_data      ;
output                   app_rd_valid     ;
output                   app_last_rd      ; // Indicate last Read Transfer for a given burst size
 
//----------------------------------------------
// Local Decleration
// ----------------------------------------
 
reg [APP_DW-1:0]         app_rd_data      ;
reg                      app_rd_valid     ;
reg [SDR_DW-1:0]         a2x_wrdt         ;
reg [SDR_BW-1:0]         a2x_wren_n       ;
reg                      app_wr_next      ;
 
reg [23:0]               saved_rd_data    ;
reg [1:0]                rd_xfr_count     ;
reg [1:0]                wr_xfr_count     ;
 
 
assign  app_last_wr = x2a_wrlast;
assign  app_last_rd = x2a_rdlast;
 
always @(*) begin
        if(sdr_width == 2'b00) // 32 Bit SDR Mode
          begin
            a2x_wrdt             = app_wr_data;
            a2x_wren_n           = app_wr_en_n;
            app_wr_next          = x2a_wrnext;
            app_rd_data          = x2a_rddt;
            app_rd_valid         = x2a_rdok;
          end
        else if(sdr_width == 2'b01) // 16 Bit SDR Mode
        begin
           // Changed the address and length to match the 16 bit SDR Mode
            app_wr_next          = (x2a_wrnext & wr_xfr_count[0]);
            app_rd_valid         = (x2a_rdok & rd_xfr_count[0]);
            if(wr_xfr_count[0] == 1'b1)
              begin
                a2x_wren_n      = app_wr_en_n[3:2];
                a2x_wrdt        = app_wr_data[31:16];
              end
            else
              begin
                a2x_wren_n      = app_wr_en_n[1:0];
                a2x_wrdt        = app_wr_data[15:0];
              end
 
            app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
        end else  // 8 Bit SDR Mode
        begin
           // Changed the address and length to match the 16 bit SDR Mode
            app_wr_next         = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
            app_rd_valid        = (x2a_rdok &   (rd_xfr_count[1:0]== 2'b11));
            if(wr_xfr_count[1:0] == 2'b11)
            begin
                a2x_wren_n      = app_wr_en_n[3];
                a2x_wrdt        = app_wr_data[31:24];
            end
            else if(wr_xfr_count[1:0] == 2'b10)
            begin
                a2x_wren_n      = app_wr_en_n[2];
                a2x_wrdt        = app_wr_data[23:16];
            end
            else if(wr_xfr_count[1:0] == 2'b01)
            begin
                a2x_wren_n      = app_wr_en_n[1];
                a2x_wrdt        = app_wr_data[15:8];
            end
            else begin
                a2x_wren_n      = app_wr_en_n[0];
                a2x_wrdt        = app_wr_data[7:0];
            end
 
            app_rd_data         = {x2a_rddt,saved_rd_data[23:0]};
          end
     end
 
 
 
always @(posedge clk)
  begin
    if(!reset_n)
      begin
        rd_xfr_count    <= 8'b0;
        wr_xfr_count    <= 8'b0;
        saved_rd_data   <= 24'h0;
      end
    else begin
 
        // During Write Phase
        if(x2a_wrlast) begin
           wr_xfr_count    <= 0;
        end
        else if(x2a_wrnext) begin
           wr_xfr_count <= wr_xfr_count + 1'b1;
        end
 
        // During Read Phase
        if(x2a_rdlast) begin
           rd_xfr_count    <= 0;
        end
        else if(x2a_rdok) begin
           rd_xfr_count   <= rd_xfr_count + 1'b1;
        end
 
        // Save Previous Data
        if(x2a_rdok) begin
           if(sdr_width == 2'b01) // 16 Bit SDR Mode
              saved_rd_data[15:0]  <= x2a_rddt;
            else begin// 8 bit SDR Mode - 
               if(rd_xfr_count[1:0] == 2'b00)      saved_rd_data[7:0]   <= x2a_rddt[7:0];
               else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8]  <= x2a_rddt[7:0];
               else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
            end
        end
    end
end
 
endmodule // sdr_bs_convert

Line No.	Rev	Author	Line
1	3	dinesha	`/*********************************************************************`
2
3			`SDRAM Controller buswidth converter`
4
5			`This file is part of the sdram controller project`
6			`http://www.opencores.org/cores/sdr_ctrl/`
7
8			`Description: SDRAM Controller Buswidth converter`
9
10			`This module does write/read data transalation between`
11			`application data to SDRAM bus width`
12
13			`To Do:`
14			`nothing`
15
16			`Author(s):`
17			`- Dinesh Annayya, dinesha@opencores.org`
18	44	dinesha	`Version : 0.0 - 8th Jan 2012 - Initial structure`
19			`0.2 - 2nd Feb 2012`
20			`Improved the command pipe structure to accept up-to 4 command of different bank.`
21	47	dinesha	`0.3 - 6th Feb 2012`
22			`Bug fix on read valid generation`
23	3	dinesha
24
25
26			`Copyright (C) 2000 Authors and OPENCORES.ORG`
27
28			`This source file may be used and distributed without`
29			`restriction provided that this copyright statement is not`
30			`removed from the file and that any derivative work contains`
31			`the original copyright notice and the associated disclaimer.`
32
33			`This source file is free software; you can redistribute it`
34			`and/or modify it under the terms of the GNU Lesser General`
35			`Public License as published by the Free Software Foundation;`
36			`either version 2.1 of the License, or (at your option) any`
37			`later version.`
38
39			`This source is distributed in the hope that it will be`
40			`useful, but WITHOUT ANY WARRANTY; without even the implied`
41			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
42			`PURPOSE. See the GNU Lesser General Public License for more`
43			`details.`
44
45			`You should have received a copy of the GNU Lesser General`
46			`Public License along with this source; if not, download it`
47			`from http://www.opencores.org/lgpl.shtml`
48
49			`*******************************************************************/`
50
51	37	dinesha	`include "sdrc_define.v"
52	3	dinesha	`module sdrc_bs_convert (`
53	45	dinesha	`clk ,`
54			`reset_n ,`
55			`sdr_width ,`
56	3	dinesha
57	44	dinesha	`/* Control Signal from xfr ctrl */`
58	45	dinesha	`x2a_rdstart ,`
59			`x2a_wrstart ,`
60			`x2a_rdlast ,`
61			`x2a_wrlast ,`
62			`x2a_rddt ,`
63			`x2a_rdok ,`
64			`a2x_wrdt ,`
65			`a2x_wren_n ,`
66			`x2a_wrnext ,`
67	44	dinesha
68	45	dinesha	`/* Control Signal from/to to application i/f */`
69			`app_wr_data ,`
70			`app_wr_en_n ,`
71			`app_wr_next ,`
72			`app_last_wr ,`
73			`app_rd_data ,`
74			`app_rd_valid ,`
75			`app_last_rd`
76			`);`
77	44	dinesha
78
79	3	dinesha	`parameter APP_AW = 30; // Application Address Width`
80			`parameter APP_DW = 32; // Application Data Width`
81			`parameter APP_BW = 4; // Application Byte Width`
82
83			`parameter SDR_DW = 16; // SDR Data Width`
84			`parameter SDR_BW = 2; // SDR Byte Width`
85
86	45	dinesha	`input clk ;`
87			`input reset_n ;`
88			`input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit`
89	3	dinesha
90	45	dinesha	`/* Control Signal from xfr ctrl Read Transaction*/`
91			`input x2a_rdstart ; // read start indication`
92			`input x2a_rdlast ; // read last burst access`
93			`input [SDR_DW-1:0] x2a_rddt ;`
94			`input x2a_rdok ;`
95	44	dinesha
96	45	dinesha	`/* Control Signal from xfr ctrl Write Transaction*/`
97			`input x2a_wrstart ; // writ start indication`
98			`input x2a_wrlast ; // write last transfer`
99			`input x2a_wrnext ;`
100			`output [SDR_DW-1:0] a2x_wrdt ;`
101			`output [SDR_BW-1:0] a2x_wren_n ;`
102	44	dinesha
103	45	dinesha	`// Application Write Transaction`
104			`input [APP_DW-1:0] app_wr_data ;`
105			`input [APP_BW-1:0] app_wr_en_n ;`
106			`output app_wr_next ;`
107			`output app_last_wr ; // Indicate last Write Transfer for a given burst size`
108	44	dinesha
109	45	dinesha	`// Application Read Transaction`
110			`output [APP_DW-1:0] app_rd_data ;`
111			`output app_rd_valid ;`
112			`output app_last_rd ; // Indicate last Read Transfer for a given burst size`
113	44	dinesha
114	45	dinesha	`//----------------------------------------------`
115			`// Local Decleration`
116			`// ----------------------------------------`
117	3	dinesha
118	45	dinesha	`reg [APP_DW-1:0] app_rd_data ;`
119			`reg app_rd_valid ;`
120			`reg [SDR_DW-1:0] a2x_wrdt ;`
121			`reg [SDR_BW-1:0] a2x_wren_n ;`
122			`reg app_wr_next ;`
123	3	dinesha
124	45	dinesha	`reg [23:0] saved_rd_data ;`
125			`reg [1:0] rd_xfr_count ;`
126			`reg [1:0] wr_xfr_count ;`
127	3	dinesha
128
129	45	dinesha	`assign app_last_wr = x2a_wrlast;`
130			`assign app_last_rd = x2a_rdlast;`
131	3	dinesha
132			`always @(*) begin`
133	16	dinesha	`if(sdr_width == 2'b00) // 32 Bit SDR Mode`
134	3	dinesha	`begin`
135	45	dinesha	`a2x_wrdt = app_wr_data;`
136			`a2x_wren_n = app_wr_en_n;`
137			`app_wr_next = x2a_wrnext;`
138			`app_rd_data = x2a_rddt;`
139			`app_rd_valid = x2a_rdok;`
140	3	dinesha	`end`
141	16	dinesha	`else if(sdr_width == 2'b01) // 16 Bit SDR Mode`
142			`begin`
143	3	dinesha	`// Changed the address and length to match the 16 bit SDR Mode`
144	45	dinesha	`app_wr_next = (x2a_wrnext & wr_xfr_count[0]);`
145	47	dinesha	`app_rd_valid = (x2a_rdok & rd_xfr_count[0]);`
146	16	dinesha	`if(wr_xfr_count[0] == 1'b1)`
147	3	dinesha	`begin`
148	45	dinesha	`a2x_wren_n = app_wr_en_n[3:2];`
149			`a2x_wrdt = app_wr_data[31:16];`
150	3	dinesha	`end`
151			`else`
152			`begin`
153	45	dinesha	`a2x_wren_n = app_wr_en_n[1:0];`
154			`a2x_wrdt = app_wr_data[15:0];`
155	3	dinesha	`end`
156
157	45	dinesha	`app_rd_data = {x2a_rddt,saved_rd_data[15:0]};`
158	16	dinesha	`end else // 8 Bit SDR Mode`
159			`begin`
160			`// Changed the address and length to match the 16 bit SDR Mode`
161	45	dinesha	`app_wr_next = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));`
162	47	dinesha	`app_rd_valid = (x2a_rdok & (rd_xfr_count[1:0]== 2'b11));`
163	44	dinesha	`if(wr_xfr_count[1:0] == 2'b11)`
164	3	dinesha	`begin`
165	45	dinesha	`a2x_wren_n = app_wr_en_n[3];`
166			`a2x_wrdt = app_wr_data[31:24];`
167	3	dinesha	`end`
168	16	dinesha	`else if(wr_xfr_count[1:0] == 2'b10)`
169	3	dinesha	`begin`
170	45	dinesha	`a2x_wren_n = app_wr_en_n[2];`
171			`a2x_wrdt = app_wr_data[23:16];`
172	3	dinesha	`end`
173	44	dinesha	`else if(wr_xfr_count[1:0] == 2'b01)`
174	3	dinesha	`begin`
175	45	dinesha	`a2x_wren_n = app_wr_en_n[1];`
176			`a2x_wrdt = app_wr_data[15:8];`
177	3	dinesha	`end`
178	16	dinesha	`else begin`
179	45	dinesha	`a2x_wren_n = app_wr_en_n[0];`
180			`a2x_wrdt = app_wr_data[7:0];`
181	16	dinesha	`end`
182
183	45	dinesha	`app_rd_data = {x2a_rddt,saved_rd_data[23:0]};`
184	16	dinesha	`end`
185			`end`
186	3	dinesha
187
188
189			`always @(posedge clk)`
190			`begin`
191			`if(!reset_n)`
192			`begin`
193	16	dinesha	`rd_xfr_count <= 8'b0;`
194			`wr_xfr_count <= 8'b0;`
195			`saved_rd_data <= 24'h0;`
196	3	dinesha	`end`
197	16	dinesha	`else begin`
198
199			`// During Write Phase`
200	44	dinesha	`if(x2a_wrlast) begin`
201			`wr_xfr_count <= 0;`
202	3	dinesha	`end`
203	45	dinesha	`else if(x2a_wrnext) begin`
204	44	dinesha	`wr_xfr_count <= wr_xfr_count + 1'b1;`
205	3	dinesha	`end`
206	16	dinesha
207			`// During Read Phase`
208	44	dinesha	`if(x2a_rdlast) begin`
209			`rd_xfr_count <= 0;`
210	16	dinesha	`end`
211	45	dinesha	`else if(x2a_rdok) begin`
212	44	dinesha	`rd_xfr_count <= rd_xfr_count + 1'b1;`
213			`end`
214
215			`// Save Previous Data`
216	45	dinesha	`if(x2a_rdok) begin`
217	16	dinesha	`if(sdr_width == 2'b01) // 16 Bit SDR Mode`
218	45	dinesha	`saved_rd_data[15:0] <= x2a_rddt;`
219	16	dinesha	`else begin// 8 bit SDR Mode -`
220	45	dinesha	`if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= x2a_rddt[7:0];`
221			`else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= x2a_rddt[7:0];`
222			`else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];`
223	16	dinesha	`end`
224			`end`
225			`end`
226			`end`
227
228	3	dinesha	`endmodule // sdr_bs_convert`

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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Blame information for rev 58