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1 3 dinesha
/*********************************************************************
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  SDRAM Controller buswidth converter
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  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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  Description: SDRAM Controller Buswidth converter
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  This module does write/read data transalation between
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     application data to SDRAM bus width
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  To Do:
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    nothing
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  Author(s):
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      - Dinesh Annayya, dinesha@opencores.org
18 44 dinesha
  Version  :  0.0  - 8th Jan 2012 - Initial structure
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              0.2 - 2nd Feb 2012
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                 Improved the command pipe structure to accept up-to 4 command of different bank.
21 47 dinesha
              0.3 - 6th Feb 2012
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                 Bug fix on read valid generation
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 Copyright (C) 2000 Authors and OPENCORES.ORG
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 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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51 37 dinesha
`include "sdrc_define.v"
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module sdrc_bs_convert (
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                    clk                 ,
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                    reset_n             ,
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                    sdr_width           ,
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        /* Control Signal from xfr ctrl */
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                    x2a_rdstart         ,
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                    x2a_wrstart         ,
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                    x2a_rdlast          ,
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                    x2a_wrlast          ,
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                    x2a_rddt            ,
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                    x2a_rdok            ,
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                    a2x_wrdt            ,
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                    a2x_wren_n          ,
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                    x2a_wrnext          ,
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   /*  Control Signal from/to to application i/f  */
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                    app_wr_data         ,
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                    app_wr_en_n         ,
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                    app_wr_next         ,
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                    app_last_wr         ,
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                    app_rd_data         ,
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                    app_rd_valid        ,
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                    app_last_rd
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                );
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parameter  APP_AW   = 30;  // Application Address Width
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parameter  APP_DW   = 32;  // Application Data Width 
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parameter  APP_BW   = 4;   // Application Byte Width
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parameter  SDR_DW   = 16;  // SDR Data Width 
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parameter  SDR_BW   = 2;   // SDR Byte Width
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input                    clk              ;
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input                    reset_n          ;
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input [1:0]              sdr_width        ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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/* Control Signal from xfr ctrl Read Transaction*/
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input                    x2a_rdstart      ; // read start indication
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input                    x2a_rdlast       ; //  read last burst access
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input [SDR_DW-1:0]       x2a_rddt         ;
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input                    x2a_rdok         ;
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/* Control Signal from xfr ctrl Write Transaction*/
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input                    x2a_wrstart      ; // writ start indication
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input                    x2a_wrlast       ; // write last transfer
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input                    x2a_wrnext       ;
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output [SDR_DW-1:0]      a2x_wrdt         ;
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output [SDR_BW-1:0]      a2x_wren_n       ;
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// Application Write Transaction
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input  [APP_DW-1:0]      app_wr_data      ;
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input  [APP_BW-1:0]      app_wr_en_n      ;
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output                   app_wr_next      ;
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output                   app_last_wr      ; // Indicate last Write Transfer for a given burst size
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// Application Read Transaction
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output [APP_DW-1:0]      app_rd_data      ;
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output                   app_rd_valid     ;
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output                   app_last_rd      ; // Indicate last Read Transfer for a given burst size
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//----------------------------------------------
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// Local Decleration
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// ----------------------------------------
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reg [APP_DW-1:0]         app_rd_data      ;
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reg                      app_rd_valid     ;
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reg [SDR_DW-1:0]         a2x_wrdt         ;
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reg [SDR_BW-1:0]         a2x_wren_n       ;
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reg                      app_wr_next      ;
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reg [23:0]               saved_rd_data    ;
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reg [1:0]                rd_xfr_count     ;
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reg [1:0]                wr_xfr_count     ;
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assign  app_last_wr = x2a_wrlast;
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assign  app_last_rd = x2a_rdlast;
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always @(*) begin
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        if(sdr_width == 2'b00) // 32 Bit SDR Mode
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          begin
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            a2x_wrdt             = app_wr_data;
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            a2x_wren_n           = app_wr_en_n;
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            app_wr_next          = x2a_wrnext;
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            app_rd_data          = x2a_rddt;
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            app_rd_valid         = x2a_rdok;
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          end
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        else if(sdr_width == 2'b01) // 16 Bit SDR Mode
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        begin
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           // Changed the address and length to match the 16 bit SDR Mode
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            app_wr_next          = (x2a_wrnext & wr_xfr_count[0]);
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            app_rd_valid         = (x2a_rdok & rd_xfr_count[0]);
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            if(wr_xfr_count[0] == 1'b1)
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              begin
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                a2x_wren_n      = app_wr_en_n[3:2];
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                a2x_wrdt        = app_wr_data[31:16];
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              end
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            else
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              begin
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                a2x_wren_n      = app_wr_en_n[1:0];
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                a2x_wrdt        = app_wr_data[15:0];
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              end
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            app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
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        end else  // 8 Bit SDR Mode
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        begin
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           // Changed the address and length to match the 16 bit SDR Mode
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            app_wr_next         = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
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            app_rd_valid        = (x2a_rdok &   (rd_xfr_count[1:0]== 2'b11));
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            if(wr_xfr_count[1:0] == 2'b11)
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            begin
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                a2x_wren_n      = app_wr_en_n[3];
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                a2x_wrdt        = app_wr_data[31:24];
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            end
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            else if(wr_xfr_count[1:0] == 2'b10)
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            begin
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                a2x_wren_n      = app_wr_en_n[2];
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                a2x_wrdt        = app_wr_data[23:16];
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            end
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            else if(wr_xfr_count[1:0] == 2'b01)
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            begin
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                a2x_wren_n      = app_wr_en_n[1];
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                a2x_wrdt        = app_wr_data[15:8];
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            end
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            else begin
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                a2x_wren_n      = app_wr_en_n[0];
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                a2x_wrdt        = app_wr_data[7:0];
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            end
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            app_rd_data         = {x2a_rddt,saved_rd_data[23:0]};
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          end
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     end
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always @(posedge clk)
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  begin
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    if(!reset_n)
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      begin
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        rd_xfr_count    <= 8'b0;
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        wr_xfr_count    <= 8'b0;
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        saved_rd_data   <= 24'h0;
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      end
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    else begin
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        // During Write Phase
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        if(x2a_wrlast) begin
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           wr_xfr_count    <= 0;
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        end
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        else if(x2a_wrnext) begin
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           wr_xfr_count <= wr_xfr_count + 1'b1;
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        end
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        // During Read Phase
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        if(x2a_rdlast) begin
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           rd_xfr_count    <= 0;
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        end
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        else if(x2a_rdok) begin
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           rd_xfr_count   <= rd_xfr_count + 1'b1;
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        end
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        // Save Previous Data
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        if(x2a_rdok) begin
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           if(sdr_width == 2'b01) // 16 Bit SDR Mode
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              saved_rd_data[15:0]  <= x2a_rddt;
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            else begin// 8 bit SDR Mode - 
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               if(rd_xfr_count[1:0] == 2'b00)      saved_rd_data[7:0]   <= x2a_rddt[7:0];
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               else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8]  <= x2a_rddt[7:0];
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               else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
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            end
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        end
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    end
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end
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228 3 dinesha
endmodule // sdr_bs_convert

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