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dinesha |
/*********************************************************************
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SDRAM Controller Core File
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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Description: SDRAM Controller Core Module
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2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
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This block integrate following sub modules
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sdrc_bs_convert
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convert the system side 32 bit into equvailent 16/32 SDR format
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sdrc_req_gen
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This module takes requests from the app, chops them to burst booundaries
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if wrap=0, decodes the bank and passe the request to bank_ctl
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sdrc_xfr_ctl
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This module takes requests from sdr_bank_ctl, runs the transfer and
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controls data flow to/from the app. At the end of the transfer it issues a
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burst terminate if not at the end of a burst and another command to this
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bank is not available.
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sdrc_bank_ctl
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This module takes requests from sdr_req_gen, checks for page hit/miss and
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issues precharge/activate commands and then passes the request to
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sdr_xfr_ctl.
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Assumption: SDRAM Pads should be placed near to this module. else
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user should add a FF near the pads
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To Do:
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nothing
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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`include "sdrc.def"
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module sdrc_core
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(
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4 |
dinesha |
clk,
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pad_clk,
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3 |
dinesha |
reset_n,
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sdr_width,
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13 |
dinesha |
cfg_colbits,
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3 |
dinesha |
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/* Request from app */
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app_req, // Transfer Request
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app_req_addr, // SDRAM Address
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app_req_addr_mask, // Address mask for queue wrap
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app_req_len, // Burst Length (in 16 bit words)
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app_req_wrap, // Wrap mode request (xfr_len = 4)
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app_req_wr_n, // 0 => Write request, 1 => read req
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app_req_ack, // Request has been accepted
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sdr_core_busy_n, // OK to arbitrate next request
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cfg_req_depth, //how many req. buffer should hold
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app_wr_data,
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app_wr_en_n,
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app_rd_data,
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app_rd_valid,
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app_wr_next_req,
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sdr_init_done,
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app_req_dma_last,
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/* Interface to SDRAMs */
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sdr_cs_n,
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sdr_cke,
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sdr_ras_n,
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sdr_cas_n,
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sdr_we_n,
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sdr_dqm,
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sdr_ba,
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sdr_addr,
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pad_sdr_din,
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sdr_dout,
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sdr_den_n,
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/* Parameters */
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cfg_sdr_en,
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cfg_sdr_dev_config, // using 64M/4bank SDRAMs
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cfg_sdr_mode_reg,
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cfg_sdr_tras_d,
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cfg_sdr_trp_d,
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cfg_sdr_trcd_d,
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cfg_sdr_cas,
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cfg_sdr_trcar_d,
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cfg_sdr_twr_d,
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cfg_sdr_rfsh,
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cfg_sdr_rfmax);
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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//-----------------------------------------------
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// Global Variable
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// ----------------------------------------------
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4 |
dinesha |
input clk ; // SDRAM Clock
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input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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3 |
dinesha |
input reset_n ; // Reset Signal
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input sdr_width ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR
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13 |
dinesha |
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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3 |
dinesha |
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13 |
dinesha |
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3 |
dinesha |
//------------------------------------------------
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// Request from app
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//------------------------------------------------
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input app_req ; // Application Request
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input [APP_AW-1:0] app_req_addr ; // Address
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input [APP_AW-2:0] app_req_addr_mask ; // Address Mask
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input app_req_wr_n ; // 0 - Write, 1 - Read
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input app_req_wrap ; // Address Wrap
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output app_req_ack ; // Application Request Ack
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output sdr_core_busy_n ; // 0 - busy, 1 - free
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input [APP_DW-1:0] app_wr_data ; // Write Data
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output app_wr_next_req ; // Next Write Data Request
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input [APP_BW-1:0] app_wr_en_n ; // Byte wise Write Enable
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output [APP_DW-1:0] app_rd_data ; // Read Data
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output app_rd_valid ; // Read Valid
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//------------------------------------------------
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// Interface to SDRAMs
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//------------------------------------------------
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output sdr_cke ; // SDRAM CKE
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output sdr_cs_n ; // SDRAM Chip Select
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output sdr_ras_n ; // SDRAM ras
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output sdr_cas_n ; // SDRAM cas
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output sdr_we_n ; // SDRAM write enable
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [11:0] sdr_addr ; // SDRAM Address
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input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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//------------------------------------------------
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// Configuration Parameter
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//------------------------------------------------
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13 |
dinesha |
output sdr_init_done ; // Indicate SDRAM Initialisation Done
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input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
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input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input cfg_sdr_en ; // Enable SDRAM controller
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3 |
dinesha |
input [1:0] cfg_sdr_dev_config ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB
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13 |
dinesha |
input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
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3 |
dinesha |
input [11:0] cfg_sdr_mode_reg ;
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13 |
dinesha |
input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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3 |
dinesha |
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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input app_req_dma_last; // this signal should close the bank
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/****************************************************************************/
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// Internal Nets
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// SDR_REQ_GEN
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wire r2x_idle, app_req_ack,app_req_ack_int;
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wire app_req_dma_last_int;
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wire r2b_req, r2b_start, r2b_last, r2b_write;
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wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
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wire [1:0] r2b_ba;
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wire [11:0] r2b_raddr;
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wire [11:0] r2b_caddr;
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wire [APP_RW-1:0] r2b_len;
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// SDR BANK CTL
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wire b2r_ack, b2x_idle;
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wire b2x_req, b2x_start, b2x_last, b2x_tras_ok;
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wire [`SDR_REQ_ID_W-1:0]b2x_id;
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wire [1:0] b2x_ba;
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wire b2x_ba_last;
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wire [11:0] b2x_addr;
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wire [APP_RW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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// SDR_XFR_CTL
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wire x2b_ack;
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wire [3:0] x2b_pre_ok;
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wire x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
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wire xfr_rdstart, xfr_rdlast;
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wire xfr_wrstart, xfr_wrlast;
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wire [`SDR_REQ_ID_W-1:0]xfr_id;
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wire [13:0] xfr_addr_msb;
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wire [APP_DW-1:0] app_rd_data;
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wire app_wr_next_req, app_rd_valid;
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wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
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wire [SDR_BW-1:0] sdr_dqm;
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wire [1:0] sdr_ba;
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wire [11:0] sdr_addr;
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wire [SDR_DW-1:0] sdr_dout;
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wire [SDR_DW-1:0] sdr_dout_int;
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wire [SDR_BW-1:0] sdr_den_n;
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wire [SDR_BW-1:0] sdr_den_n_int;
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wire [1:0] xfr_bank_sel;
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wire [1:0] cfg_sdr_dev_config;
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wire [APP_AW:0] app_req_addr_int;
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wire [APP_AW-1:0] app_req_addr;
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wire [APP_RW-1:0] app_req_len_int;
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wire [APP_RW-1:0] app_req_len;
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wire [APP_DW-1:0] app_wr_data;
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wire [SDR_DW-1:0] add_wr_data_int;
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wire [APP_BW-1:0] app_wr_en_n;
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wire [SDR_BW-1:0] app_wr_en_n_int;
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//wire [31:0] app_rd_data;
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wire [SDR_DW-1:0] app_rd_data_int;
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//
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wire app_req_int;
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wire r2b_wrap;
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wire b2r_arb_ok;
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wire b2x_wrap;
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wire app_wr_next_int;
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wire app_rd_valid_int;
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// synopsys translate_off
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wire [3:0] sdr_cmd;
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assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
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// synopsys translate_on
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assign sdr_den_n = sdr_width ? {2'b00,sdr_den_n_int[1:0]} : sdr_den_n_int;
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assign sdr_dout = sdr_width ? {16'h0000,sdr_dout_int[15:0]} : sdr_dout_int;
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/****************************************************************************/
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// Instantiate sdr_req_gen
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// This module takes requests from the app, chops them to burst booundaries
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// if wrap=0, decodes the bank and passe the request to bank_ctl
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9 |
dinesha |
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
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4 |
dinesha |
.clk (clk ),
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3 |
dinesha |
.reset_n (reset_n ),
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.sdr_dev_config (cfg_sdr_dev_config ),
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13 |
dinesha |
.cfg_colbits (cfg_colbits ),
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3 |
dinesha |
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/* Request from app */
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.r2x_idle (r2x_idle ),
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.req (app_req_int ),
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.req_id (4'b0 ),
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.req_addr (app_req_addr_int ),
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.req_addr_mask (app_req_addr_mask ),
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.req_len (app_req_len_int ),
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.req_wrap (app_req_wrap ),
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.req_wr_n (app_req_wr_n ),
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.req_ack (app_req_ack_int ),
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.sdr_core_busy_n (sdr_core_busy_n ),
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/* Req to bank_ctl */
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.r2b_req (r2b_req ),
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.r2b_req_id (r2b_req_id ),
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.r2b_start (r2b_start ),
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.r2b_last (r2b_last ),
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.r2b_wrap (r2b_wrap ),
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.r2b_ba (r2b_ba ),
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.r2b_raddr (r2b_raddr ),
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.r2b_caddr (r2b_caddr ),
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.r2b_len (r2b_len ),
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.r2b_write (r2b_write ),
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.b2r_ack (b2r_ack ),
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.b2r_arb_ok (b2r_arb_ok ),
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.sdr_width (sdr_width ),
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.sdr_init_done (sdr_init_done )
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);
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/****************************************************************************/
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// Instantiate sdr_bank_ctl
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// This module takes requests from sdr_req_gen, checks for page hit/miss and
|
| 309 |
|
|
// issues precharge/activate commands and then passes the request to
|
| 310 |
|
|
// sdr_xfr_ctl.
|
| 311 |
|
|
|
| 312 |
9 |
dinesha |
sdrc_bank_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bank_ctl (
|
| 313 |
4 |
dinesha |
.clk (clk ),
|
| 314 |
3 |
dinesha |
.reset_n (reset_n ),
|
| 315 |
|
|
.a2b_req_depth (cfg_req_depth ),
|
| 316 |
|
|
|
| 317 |
|
|
/* Req from req_gen */
|
| 318 |
|
|
.r2b_req (r2b_req ),
|
| 319 |
|
|
.r2b_req_id (r2b_req_id ),
|
| 320 |
|
|
.r2b_start (r2b_start ),
|
| 321 |
|
|
.r2b_last (r2b_last ),
|
| 322 |
|
|
.r2b_wrap (r2b_wrap ),
|
| 323 |
|
|
.r2b_ba (r2b_ba ),
|
| 324 |
|
|
.r2b_raddr (r2b_raddr ),
|
| 325 |
|
|
.r2b_caddr (r2b_caddr ),
|
| 326 |
|
|
.r2b_len (r2b_len ),
|
| 327 |
|
|
.r2b_write (r2b_write ),
|
| 328 |
|
|
.b2r_arb_ok (b2r_arb_ok ),
|
| 329 |
|
|
.b2r_ack (b2r_ack ),
|
| 330 |
|
|
|
| 331 |
|
|
/* Transfer request to xfr_ctl */
|
| 332 |
|
|
.b2x_idle (b2x_idle ),
|
| 333 |
|
|
.b2x_req (b2x_req ),
|
| 334 |
|
|
.b2x_start (b2x_start ),
|
| 335 |
|
|
.b2x_last (b2x_last ),
|
| 336 |
|
|
.b2x_wrap (b2x_wrap ),
|
| 337 |
|
|
.b2x_id (b2x_id ),
|
| 338 |
|
|
.b2x_ba (b2x_ba ),
|
| 339 |
|
|
.b2x_addr (b2x_addr ),
|
| 340 |
|
|
.b2x_len (b2x_len ),
|
| 341 |
|
|
.b2x_cmd (b2x_cmd ),
|
| 342 |
|
|
.x2b_ack (x2b_ack ),
|
| 343 |
|
|
|
| 344 |
|
|
/* Status from xfr_ctl */
|
| 345 |
|
|
.b2x_tras_ok (b2x_tras_ok ),
|
| 346 |
|
|
.x2b_refresh (x2b_refresh ),
|
| 347 |
|
|
.x2b_pre_ok (x2b_pre_ok ),
|
| 348 |
|
|
.x2b_act_ok (x2b_act_ok ),
|
| 349 |
|
|
.x2b_rdok (x2b_rdok ),
|
| 350 |
|
|
.x2b_wrok (x2b_wrok ),
|
| 351 |
|
|
|
| 352 |
|
|
/* for generate cuurent xfr address msb */
|
| 353 |
|
|
.sdr_dev_config (cfg_sdr_dev_config ),
|
| 354 |
|
|
.sdr_req_norm_dma_last(app_req_dma_last_int),
|
| 355 |
|
|
.xfr_bank_sel (xfr_bank_sel ),
|
| 356 |
|
|
.xfr_addr_msb (xfr_addr_msb ),
|
| 357 |
|
|
|
| 358 |
|
|
/* SDRAM Timing */
|
| 359 |
|
|
.tras_delay (cfg_sdr_tras_d ),
|
| 360 |
|
|
.trp_delay (cfg_sdr_trp_d ),
|
| 361 |
|
|
.trcd_delay (cfg_sdr_trcd_d )
|
| 362 |
|
|
);
|
| 363 |
|
|
|
| 364 |
|
|
/****************************************************************************/
|
| 365 |
|
|
// Instantiate sdr_xfr_ctl
|
| 366 |
|
|
// This module takes requests from sdr_bank_ctl, runs the transfer and
|
| 367 |
|
|
// controls data flow to/from the app. At the end of the transfer it issues a
|
| 368 |
|
|
// burst terminate if not at the end of a burst and another command to this
|
| 369 |
|
|
// bank is not available.
|
| 370 |
|
|
|
| 371 |
9 |
dinesha |
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_xfr_ctl (
|
| 372 |
4 |
dinesha |
.clk (clk ),
|
| 373 |
3 |
dinesha |
.reset_n (reset_n ),
|
| 374 |
|
|
|
| 375 |
|
|
/* Transfer request from bank_ctl */
|
| 376 |
|
|
.r2x_idle (r2x_idle ),
|
| 377 |
|
|
.b2x_idle (b2x_idle ),
|
| 378 |
|
|
.b2x_req (b2x_req ),
|
| 379 |
|
|
.b2x_start (b2x_start ),
|
| 380 |
|
|
.b2x_last (b2x_last ),
|
| 381 |
|
|
.b2x_wrap (b2x_wrap ),
|
| 382 |
|
|
.b2x_id (b2x_id ),
|
| 383 |
|
|
.b2x_ba (b2x_ba ),
|
| 384 |
|
|
.b2x_addr (b2x_addr ),
|
| 385 |
|
|
.b2x_len (b2x_len ),
|
| 386 |
|
|
.b2x_cmd (b2x_cmd ),
|
| 387 |
|
|
.x2b_ack (x2b_ack ),
|
| 388 |
|
|
|
| 389 |
|
|
/* Status to bank_ctl, req_gen */
|
| 390 |
|
|
.b2x_tras_ok (b2x_tras_ok ),
|
| 391 |
|
|
.x2b_refresh (x2b_refresh ),
|
| 392 |
|
|
.x2b_pre_ok (x2b_pre_ok ),
|
| 393 |
|
|
.x2b_act_ok (x2b_act_ok ),
|
| 394 |
|
|
.x2b_rdok (x2b_rdok ),
|
| 395 |
|
|
.x2b_wrok (x2b_wrok ),
|
| 396 |
|
|
|
| 397 |
|
|
/* SDRAM I/O */
|
| 398 |
|
|
.sdr_cs_n (sdr_cs_n ),
|
| 399 |
|
|
.sdr_cke (sdr_cke ),
|
| 400 |
|
|
.sdr_ras_n (sdr_ras_n ),
|
| 401 |
|
|
.sdr_cas_n (sdr_cas_n ),
|
| 402 |
|
|
.sdr_we_n (sdr_we_n ),
|
| 403 |
|
|
.sdr_dqm (sdr_dqm ),
|
| 404 |
|
|
.sdr_ba (sdr_ba ),
|
| 405 |
|
|
.sdr_addr (sdr_addr ),
|
| 406 |
|
|
.sdr_din (pad_sdr_din ),
|
| 407 |
|
|
.sdr_dout (sdr_dout_int ),
|
| 408 |
|
|
.sdr_den_n (sdr_den_n_int ),
|
| 409 |
|
|
|
| 410 |
|
|
/* Data Flow to the app */
|
| 411 |
|
|
.x2a_rdstart (xfr_rdstart ),
|
| 412 |
|
|
.x2a_wrstart (xfr_wrstart ),
|
| 413 |
|
|
.x2a_id (xfr_id ),
|
| 414 |
|
|
.x2a_rdlast (xfr_rdlast ),
|
| 415 |
|
|
.x2a_wrlast (xfr_wrlast ),
|
| 416 |
|
|
.app_wrdt (add_wr_data_int ),
|
| 417 |
4 |
dinesha |
.app_wren_n (app_wr_en_n_int ),
|
| 418 |
3 |
dinesha |
.x2a_wrnext (app_wr_next_int ),
|
| 419 |
|
|
.x2a_rddt (app_rd_data_int ),
|
| 420 |
|
|
.x2a_rdok (app_rd_valid_int ),
|
| 421 |
|
|
.sdr_init_done (sdr_init_done ),
|
| 422 |
|
|
|
| 423 |
|
|
/* SDRAM Parameters */
|
| 424 |
|
|
.sdram_enable (cfg_sdr_en ),
|
| 425 |
|
|
.sdram_mode_reg (cfg_sdr_mode_reg ),
|
| 426 |
|
|
|
| 427 |
|
|
/* current xfr bank */
|
| 428 |
|
|
.xfr_bank_sel (xfr_bank_sel ),
|
| 429 |
|
|
|
| 430 |
|
|
/* SDRAM Timing */
|
| 431 |
|
|
.cas_latency (cfg_sdr_cas ),
|
| 432 |
|
|
.trp_delay (cfg_sdr_trp_d ),
|
| 433 |
|
|
.trcar_delay (cfg_sdr_trcar_d ),
|
| 434 |
|
|
.twr_delay (cfg_sdr_twr_d ),
|
| 435 |
|
|
.rfsh_time (cfg_sdr_rfsh ),
|
| 436 |
|
|
.rfsh_rmax (cfg_sdr_rfmax )
|
| 437 |
|
|
);
|
| 438 |
|
|
|
| 439 |
9 |
dinesha |
sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
|
| 440 |
4 |
dinesha |
.clk (clk ),
|
| 441 |
3 |
dinesha |
.reset_n (reset_n ),
|
| 442 |
|
|
.sdr_width (sdr_width ),
|
| 443 |
|
|
|
| 444 |
|
|
.app_req_addr (app_req_addr ),
|
| 445 |
|
|
.app_req_addr_int (app_req_addr_int ),
|
| 446 |
|
|
.app_req_len (app_req_len ),
|
| 447 |
|
|
.app_req_len_int (app_req_len_int ),
|
| 448 |
|
|
.app_sdr_req (app_req ),
|
| 449 |
|
|
.app_sdr_req_int (app_req_int ),
|
| 450 |
|
|
.app_req_dma_last (app_req_dma_last ),
|
| 451 |
|
|
.app_req_dma_last_int(app_req_dma_last_int),
|
| 452 |
|
|
.app_req_wr_n (app_req_wr_n ),
|
| 453 |
4 |
dinesha |
.app_req_ack_int (app_req_ack_int ),
|
| 454 |
3 |
dinesha |
.app_req_ack (app_req_ack ),
|
| 455 |
|
|
|
| 456 |
|
|
.app_wr_data (app_wr_data ),
|
| 457 |
|
|
.app_wr_data_int (add_wr_data_int ),
|
| 458 |
|
|
.app_wr_en_n (app_wr_en_n ),
|
| 459 |
|
|
.app_wr_en_n_int (app_wr_en_n_int ),
|
| 460 |
|
|
.app_wr_next_int (app_wr_next_int ),
|
| 461 |
|
|
.app_wr_next (app_wr_next_req ),
|
| 462 |
|
|
|
| 463 |
|
|
.app_rd_data_int (app_rd_data_int ),
|
| 464 |
|
|
.app_rd_data (app_rd_data ),
|
| 465 |
|
|
.app_rd_valid_int (app_rd_valid_int ),
|
| 466 |
|
|
.app_rd_valid (app_rd_valid )
|
| 467 |
|
|
);
|
| 468 |
|
|
|
| 469 |
|
|
endmodule // sdrc_core
|
