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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Blame information for rev 52

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`define SDR_REQ_ID_W       4
 
`define SDR_RFSH_TIMER_W    12
`define SDR_RFSH_ROW_CNT_W   3
 
// B2X Command
 
`define OP_PRE           2'b00
`define OP_ACT           2'b01
`define OP_RD            2'b10
`define OP_WR            2'b11
 
// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
 
`define SDR_DESEL        4'b1111
`define SDR_NOOP         4'b0111
`define SDR_ACTIVATE     4'b0011
`define SDR_READ         4'b0101
`define SDR_WRITE        4'b0100
`define SDR_BT           4'b0110
`define SDR_PRECHARGE    4'b0010
`define SDR_REFRESH      4'b0001
`define SDR_MODE         4'b0000
 
`define  ASIC            1'b1
`define  FPGA            1'b0
`define  TARGET_DESIGN   `FPGA
 

Line No.	Rev	Author	Line
1	3	dinesha
2			`define SDR_REQ_ID_W 4
3
4			`define SDR_RFSH_TIMER_W 12
5			`define SDR_RFSH_ROW_CNT_W 3
6
7			`// B2X Command`
8
9			`define OP_PRE 2'b00
10			`define OP_ACT 2'b01
11			`define OP_RD 2'b10
12			`define OP_WR 2'b11
13
14			`// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)`
15
16			`define SDR_DESEL 4'b1111
17			`define SDR_NOOP 4'b0111
18			`define SDR_ACTIVATE 4'b0011
19			`define SDR_READ 4'b0101
20			`define SDR_WRITE 4'b0100
21			`define SDR_BT 4'b0110
22			`define SDR_PRECHARGE 4'b0010
23			`define SDR_REFRESH 4'b0001
24			`define SDR_MODE 4'b0000
25
26	51	dinesha	`define ASIC 1'b1
27			`define FPGA 1'b0
28			`define TARGET_DESIGN `FPGA
29	3	dinesha

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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Blame information for rev 52