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[/] [sdr_ctrl/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Blame information for rev 45

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1 31 dinesha
/*********************************************************************
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  ASYNC FIFO
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  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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  Description: ASYNC FIFO
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  To Do:
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    nothing
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  Author(s):  Dinesh Annayya, dinesha@opencores.org
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 Copyright (C) 2000 Authors and OPENCORES.ORG
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 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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//-------------------------------------------
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// async FIFO
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//-----------------------------------------------
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`timescale  1ns/1ps
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module async_fifo (wr_clk,
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                   wr_reset_n,
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                   wr_en,
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                   wr_data,
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                   full,                 // sync'ed to wr_clk
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                   afull,                 // sync'ed to wr_clk
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                   rd_clk,
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                   rd_reset_n,
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                   rd_en,
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                   empty,                // sync'ed to rd_clk
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                   aempty,                // sync'ed to rd_clk
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                   rd_data);
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   parameter W = 4'd8;
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   parameter DP = 3'd4;
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   parameter WR_FAST = 1'b1;
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   parameter RD_FAST = 1'b1;
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   parameter FULL_DP = DP;
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   parameter EMPTY_DP = 1'b0;
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   parameter AW = (DP == 2)   ? 1 :
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                  (DP == 4)   ? 2 :
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                  (DP == 8)   ? 3 :
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                  (DP == 16)  ? 4 :
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                  (DP == 32)  ? 5 :
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                  (DP == 64)  ? 6 :
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                  (DP == 128) ? 7 :
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                  (DP == 256) ? 8 : 0;
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   output [W-1 : 0]  rd_data;
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   input [W-1 : 0]   wr_data;
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   input             wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
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                     rd_en;
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   output            full, empty;
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   output            afull, aempty;       // about full and about to empty
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   // synopsys translate_off
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   initial begin
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      if (AW == 0) begin
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         $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
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      end // if (AW == 0)
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   end // initial begin
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   // synopsys translate_on
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   reg [W-1 : 0]    mem[DP-1 : 0];
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   /*********************** write side ************************/
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   reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
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   wire [AW:0] sync_rd_ptr;
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   reg [AW:0] wr_ptr, grey_wr_ptr;
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   reg [AW:0] grey_rd_ptr;
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   reg full_q;
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   wire full_c;
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   wire afull_c;
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   wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
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   wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
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   assign full_c  = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
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   assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
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   always @(posedge wr_clk or negedge wr_reset_n) begin
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        if (!wr_reset_n) begin
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                wr_ptr <= 0;
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                grey_wr_ptr <= 0;
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                full_q <= 0;
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        end
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        else if (wr_en) begin
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                wr_ptr <= wr_ptr_inc;
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                grey_wr_ptr <= bin2grey(wr_ptr_inc);
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                if (wr_cnt == (FULL_DP-1)) begin
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                        full_q <= 1'b1;
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                end
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        end
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        else begin
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                if (full_q && (wr_cnt<FULL_DP)) begin
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                        full_q <= 1'b0;
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                end
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        end
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    end
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    assign full  = (WR_FAST == 1) ? full_c : full_q;
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    assign afull = afull_c;
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    always @(posedge wr_clk) begin
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        if (wr_en) begin
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                mem[wr_ptr[AW-1:0]] <= wr_data;
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        end
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    end
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    wire [AW:0] grey_rd_ptr_dly ;
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    assign #1 grey_rd_ptr_dly = grey_rd_ptr;
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    // read pointer synchronizer
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    always @(posedge wr_clk or negedge wr_reset_n) begin
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        if (!wr_reset_n) begin
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                sync_rd_ptr_0 <= 0;
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                sync_rd_ptr_1 <= 0;
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        end
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        else begin
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                sync_rd_ptr_0 <= grey_rd_ptr_dly;
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                sync_rd_ptr_1 <= sync_rd_ptr_0;
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        end
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    end
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    assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
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   /************************ read side *****************************/
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   reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
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   wire [AW:0] sync_wr_ptr;
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   reg [AW:0] rd_ptr;
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   reg empty_q;
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   wire empty_c;
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   wire aempty_c;
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   wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
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   wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
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   wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
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   assign empty_c  = (rd_cnt == 0) ? 1'b1 : 1'b0;
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   assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
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   always @(posedge rd_clk or negedge rd_reset_n) begin
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      if (!rd_reset_n) begin
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         rd_ptr <= 0;
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         grey_rd_ptr <= 0;
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         empty_q <= 1'b1;
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      end
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      else begin
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         if (rd_en) begin
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            rd_ptr <= rd_ptr_inc;
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            grey_rd_ptr <= bin2grey(rd_ptr_inc);
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            if (rd_cnt==(EMPTY_DP+1)) begin
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               empty_q <= 1'b1;
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            end
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         end
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         else begin
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            if (empty_q && (rd_cnt!=EMPTY_DP)) begin
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              empty_q <= 1'b0;
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            end
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         end
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       end
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    end
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    assign empty  = (RD_FAST == 1) ? empty_c : empty_q;
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    assign aempty = aempty_c;
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    assign rd_data = mem[rd_ptr[AW-1:0]];
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    wire [AW:0] grey_wr_ptr_dly ;
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    assign #1 grey_wr_ptr_dly =  grey_wr_ptr;
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    // write pointer synchronizer
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    always @(posedge rd_clk or negedge rd_reset_n) begin
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        if (!rd_reset_n) begin
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           sync_wr_ptr_0 <= 0;
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           sync_wr_ptr_1 <= 0;
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        end
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        else begin
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           sync_wr_ptr_0 <= grey_wr_ptr_dly;
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           sync_wr_ptr_1 <= sync_wr_ptr_0;
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        end
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    end
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    assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
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/************************ functions ******************************/
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function [AW:0] bin2grey;
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input [AW:0] bin;
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reg [8:0] bin_8;
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reg [8:0] grey_8;
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begin
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        bin_8 = bin;
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        grey_8[1:0] = do_grey(bin_8[2:0]);
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        grey_8[3:2] = do_grey(bin_8[4:2]);
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        grey_8[5:4] = do_grey(bin_8[6:4]);
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        grey_8[7:6] = do_grey(bin_8[8:6]);
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        grey_8[8] = bin_8[8];
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        bin2grey = grey_8;
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end
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endfunction
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function [AW:0] grey2bin;
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input [AW:0] grey;
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reg [8:0] grey_8;
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reg [8:0] bin_8;
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begin
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        grey_8 = grey;
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        bin_8[8] = grey_8[8];
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        bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
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        bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
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        bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
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        bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
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        grey2bin = bin_8;
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end
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endfunction
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function [1:0] do_grey;
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input [2:0] bin;
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begin
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        if (bin[2]) begin  // do reverse grey
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                case (bin[1:0])
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                        2'b00: do_grey = 2'b10;
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                        2'b01: do_grey = 2'b11;
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                        2'b10: do_grey = 2'b01;
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                        2'b11: do_grey = 2'b00;
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                endcase
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        end
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        else begin
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                case (bin[1:0])
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                        2'b00: do_grey = 2'b00;
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                        2'b01: do_grey = 2'b01;
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                        2'b10: do_grey = 2'b11;
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                        2'b11: do_grey = 2'b10;
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                endcase
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        end
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end
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endfunction
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function [1:0] do_bin;
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input [2:0] grey;
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begin
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        if (grey[2]) begin      // actually bin[2]
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                case (grey[1:0])
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                        2'b10: do_bin = 2'b00;
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                        2'b11: do_bin = 2'b01;
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                        2'b01: do_bin = 2'b10;
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                        2'b00: do_bin = 2'b11;
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                endcase
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        end
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        else begin
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                case (grey[1:0])
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                        2'b00: do_bin = 2'b00;
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                        2'b01: do_bin = 2'b01;
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                        2'b11: do_bin = 2'b10;
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                        2'b10: do_bin = 2'b11;
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                endcase
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        end
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end
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endfunction
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function [AW:0] get_cnt;
290
input [AW:0] wr_ptr, rd_ptr;
291
begin
292
        if (wr_ptr >= rd_ptr) begin
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                get_cnt = (wr_ptr - rd_ptr);
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        end
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        else begin
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                get_cnt = DP*2 - (rd_ptr - wr_ptr);
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        end
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end
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endfunction
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// synopsys translate_off
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always @(posedge wr_clk) begin
303
   if (wr_en && full) begin
304
      $display($time, "%m Error! afifo overflow!");
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      $stop;
306
   end
307
end
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309
always @(posedge rd_clk) begin
310
   if (rd_en && empty) begin
311
      $display($time, "%m error! afifo underflow!");
312
      $stop;
313
   end
314
end
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// synopsys translate_on
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endmodule

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