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/*********************************************************************
 
  SDRAM Controller top File
 
  This file is part of the sdram controller project
  http://www.opencores.org/cores/sdr_ctrl/
 
  Description: SDRAM Controller Top Module.
    Support 81/6/32 Bit SDRAM.
    Column Address is Programmable
    Bank Bit are 2 Bit
    Row Bits are 12 Bits
 
    This block integrate following sub modules
 
    sdrc_core
        SDRAM Controller file
    wb2sdrc
        This module transalate the bus protocl from wishbone to custome
        sdram controller
 
  To Do:
    nothing
 
  Author(s): Dinesh Annayya, dinesha@opencores.org
  Version  : 0.0 - 8th Jan 2012
                Initial version with 16/32 Bit SDRAM Support
           : 0.1 - 24th Jan 2012
                 8 Bit SDRAM Support is added
             0.2 - 31st Jan 2012
                 sdram_dq and sdram_pad_clk are internally generated
 
 
 Copyright (C) 2000 Authors and OPENCORES.ORG
 
 This source file may be used and distributed without
 restriction provided that this copyright statement is not
 removed from the file and that any derivative work contains
 the original copyright notice and the associated disclaimer.
 
 This source file is free software; you can redistribute it
 and/or modify it under the terms of the GNU Lesser General
 Public License as published by the Free Software Foundation;
 either version 2.1 of the License, or (at your option) any
later version.
 
 This source is distributed in the hope that it will be
 useful, but WITHOUT ANY WARRANTY; without even the implied
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 PURPOSE.  See the GNU Lesser General Public License for more
 details.
 
 You should have received a copy of the GNU Lesser General
 Public License along with this source; if not, download it
 from http://www.opencores.org/lgpl.shtml
 
*******************************************************************/
 
 
`include "sdrc_define.v"
module sdrc_top
           (
                    cfg_sdr_width       ,
                    cfg_colbits         ,
 
                // WB bus
                    wb_rst_i            ,
                    wb_clk_i            ,
 
                    wb_stb_i            ,
                    wb_ack_o            ,
                    wb_addr_i           ,
                    wb_we_i             ,
                    wb_dat_i            ,
                    wb_sel_i            ,
                    wb_dat_o            ,
                    wb_cyc_i            ,
                    wb_cti_i            ,
 
 
                /* Interface to SDRAMs */
                    sdram_clk           ,
                    sdram_resetn        ,
                    sdr_cs_n            ,
                    sdr_cke             ,
                    sdr_ras_n           ,
                    sdr_cas_n           ,
                    sdr_we_n            ,
                    sdr_dqm             ,
                    sdr_ba              ,
                    sdr_addr            ,
                    sdr_dq              ,
 
                /* Parameters */
                    sdr_init_done       ,
                    cfg_req_depth       ,               //how many req. buffer should hold
                    cfg_sdr_en          ,
                    cfg_sdr_mode_reg    ,
                    cfg_sdr_tras_d      ,
                    cfg_sdr_trp_d       ,
                    cfg_sdr_trcd_d      ,
                    cfg_sdr_cas         ,
                    cfg_sdr_trcar_d     ,
                    cfg_sdr_twr_d       ,
                    cfg_sdr_rfsh        ,
                    cfg_sdr_rfmax
            );
 
parameter      APP_AW   = 30;  // Application Address Width
parameter      APP_DW   = 32;  // Application Data Width 
parameter      APP_BW   = 4;   // Application Byte Width
parameter      APP_RW   = 9;   // Application Request Width
 
parameter      SDR_DW   = 16;  // SDR Data Width 
parameter      SDR_BW   = 2;   // SDR Byte Width
 
parameter      dw       = 32;  // data width
parameter      tw       = 8;   // tag id width
parameter      bl       = 9;   // burst_lenght_width 
 
//-----------------------------------------------
// Global Variable
// ----------------------------------------------
input                   sdram_clk          ; // SDRAM Clock 
input                   sdram_resetn       ; // Reset Signal
input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
                                             // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
//--------------------------------------
// Wish Bone Interface
// -------------------------------------      
input                   wb_rst_i           ;
input                   wb_clk_i           ;
 
input                   wb_stb_i           ;
output                  wb_ack_o           ;
input [29:0]            wb_addr_i          ;
input                   wb_we_i            ; // 1 - Write, 0 - Read
input [dw-1:0]          wb_dat_i           ;
input [dw/8-1:0]        wb_sel_i           ; // Byte enable
output [dw-1:0]         wb_dat_o           ;
input                   wb_cyc_i           ;
input  [2:0]            wb_cti_i           ;
 
//------------------------------------------------
// Interface to SDRAMs
//------------------------------------------------
output                  sdr_cke             ; // SDRAM CKE
output                  sdr_cs_n            ; // SDRAM Chip Select
output                  sdr_ras_n           ; // SDRAM ras
output                  sdr_cas_n           ; // SDRAM cas
output                  sdr_we_n            ; // SDRAM write enable
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
output [11:0]            sdr_addr            ; // SDRAM Address
inout [SDR_DW-1:0]       sdr_dq              ; // SDRA Data Input/output
 
//------------------------------------------------
// Configuration Parameter
//------------------------------------------------
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
input                   cfg_sdr_en          ; // Enable SDRAM controller
input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
input [11:0]             cfg_sdr_mode_reg    ;
input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
 
//--------------------------------------------
// SDRAM controller Interface 
//--------------------------------------------
wire                  app_req            ; // SDRAM request
wire [29:0]           app_req_addr       ; // SDRAM Request Address
wire [bl-1:0]         app_req_len        ;
wire                  app_req_wr_n       ; // 0 - Write, 1 -> Read
wire                  app_req_ack        ; // SDRAM request Accepted
wire                  app_busy_n         ; // 0 -> sdr busy
wire [dw/8-1:0]       app_wr_en_n        ; // Active low sdr byte-wise write data valid
wire                  app_wr_next_req    ; // Ready to accept the next write
wire                  app_rd_valid       ; // sdr read valid
wire                  app_last_rd        ; // Indicate last Read of Burst Transfer
wire [dw-1:0]         app_wr_data        ; // sdr write data
wire  [dw-1:0]        app_rd_data        ; // sdr read data
 
/****************************************
*  These logic has to be implemented using Pads
*  **************************************/
wire  [SDR_DW-1:0]    pad_sdr_din         ; // SDRA Data Input
wire  [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
wire  [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
 
 
assign   sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout :  {SDR_DW{1'bz}};
assign   pad_sdr_din = sdr_dq;
 
// sdram pad clock is routed back through pad
// SDRAM Clock from Pad, used for registering Read Data
wire #(1.0) sdram_pad_clk = sdram_clk;
 
/************** Ends Here **************************/
wb2sdrc u_wb2sdrc (
      // WB bus
          .wb_rst_i           (wb_rst_i           ) ,
          .wb_clk_i           (wb_clk_i           ) ,
 
          .wb_stb_i           (wb_stb_i           ) ,
          .wb_ack_o           (wb_ack_o           ) ,
          .wb_addr_i          (wb_addr_i          ) ,
          .wb_we_i            (wb_we_i            ) ,
          .wb_dat_i           (wb_dat_i           ) ,
          .wb_sel_i           (wb_sel_i           ) ,
          .wb_dat_o           (wb_dat_o           ) ,
          .wb_cyc_i           (wb_cyc_i           ) ,
          .wb_cti_i           (wb_cti_i           ) ,
 
 
      //SDRAM Controller Hand-Shake Signal 
          .sdram_clk          (sdram_clk          ) ,
          .sdram_resetn       (sdram_resetn       ) ,
          .sdr_req            (app_req            ) ,
          .sdr_req_addr       (app_req_addr       ) ,
          .sdr_req_len        (app_req_len        ) ,
          .sdr_req_wr_n       (app_req_wr_n       ) ,
          .sdr_req_ack        (app_req_ack        ) ,
          .sdr_busy_n         (app_busy_n         ) ,
          .sdr_wr_en_n        (app_wr_en_n        ) ,
          .sdr_wr_next        (app_wr_next_req    ) ,
          .sdr_rd_valid       (app_rd_valid       ) ,
          .sdr_last_rd        (app_last_rd        ) ,
          .sdr_wr_data        (app_wr_data        ) ,
          .sdr_rd_data        (app_rd_data        )
 
      );
 
 
sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
          .clk                (sdram_clk          ) ,
          .pad_clk            (sdram_pad_clk      ) ,
          .reset_n            (sdram_resetn       ) ,
          .sdr_width          (cfg_sdr_width      ) ,
          .cfg_colbits        (cfg_colbits        ) ,
 
                /* Request from app */
          .app_req            (app_req            ) ,// Transfer Request
          .app_req_addr       (app_req_addr       ) ,// SDRAM Address
          .app_req_addr_mask  (29'h0              ) ,// Address mask for queue wrap
          .app_req_len        (app_req_len        ) ,// Burst Length (in 16 bit words)
          .app_req_wrap       (1'b0               ) ,// Wrap mode request 
          .app_req_wr_n       (app_req_wr_n       ) ,// 0 => Write request, 1 => read req
          .app_req_ack        (app_req_ack        ) ,// Request has been accepted
          .sdr_core_busy_n    (app_core_busy_n    ) ,// OK to arbitrate next request
          .cfg_req_depth      (cfg_req_depth      ) ,//how many req. buffer should hold
 
          .app_wr_data        (app_wr_data        ) ,
          .app_wr_en_n        (app_wr_en_n        ) ,
          .app_rd_data        (app_rd_data        ) ,
          .app_rd_valid       (app_rd_valid       ) ,
          .app_last_rd        (app_last_rd        ) ,
          .app_wr_next_req    (app_wr_next_req    ) ,
          .sdr_init_done      (sdr_init_done      ) ,
          .app_req_dma_last   (app_req            ) ,
 
                /* Interface to SDRAMs */
          .sdr_cs_n           (sdr_cs_n           ) ,
          .sdr_cke            (sdr_cke            ) ,
          .sdr_ras_n          (sdr_ras_n          ) ,
          .sdr_cas_n          (sdr_cas_n          ) ,
          .sdr_we_n           (sdr_we_n           ) ,
          .sdr_dqm            (sdr_dqm            ) ,
          .sdr_ba             (sdr_ba             ) ,
          .sdr_addr           (sdr_addr           ) ,
          .pad_sdr_din        (pad_sdr_din        ) ,
          .sdr_dout           (sdr_dout           ) ,
          .sdr_den_n          (sdr_den_n          ) ,
 
                /* Parameters */
          .cfg_sdr_en         (cfg_sdr_en         ) ,
          .cfg_sdr_mode_reg   (cfg_sdr_mode_reg   ) ,
          .cfg_sdr_tras_d     (cfg_sdr_tras_d     ) ,
          .cfg_sdr_trp_d      (cfg_sdr_trp_d      ) ,
          .cfg_sdr_trcd_d     (cfg_sdr_trcd_d     ) ,
          .cfg_sdr_cas        (cfg_sdr_cas        ) ,
          .cfg_sdr_trcar_d    (cfg_sdr_trcar_d    ) ,
          .cfg_sdr_twr_d      (cfg_sdr_twr_d      ) ,
          .cfg_sdr_rfsh       (cfg_sdr_rfsh       ) ,
          .cfg_sdr_rfmax      (cfg_sdr_rfmax      )
               );
 
endmodule // sdrc_core

Line No.	Rev	Author	Line
1	31	dinesha	`/*********************************************************************`
2
3			`SDRAM Controller top File`
4
5			`This file is part of the sdram controller project`
6			`http://www.opencores.org/cores/sdr_ctrl/`
7
8	33	dinesha	`Description: SDRAM Controller Top Module.`
9			`Support 81/6/32 Bit SDRAM.`
10			`Column Address is Programmable`
11			`Bank Bit are 2 Bit`
12			`Row Bits are 12 Bits`
13
14	31	dinesha	`This block integrate following sub modules`
15
16			`sdrc_core`
17			`SDRAM Controller file`
18			`wb2sdrc`
19			`This module transalate the bus protocl from wishbone to custome`
20			`sdram controller`
21
22			`To Do:`
23			`nothing`
24
25			`Author(s): Dinesh Annayya, dinesha@opencores.org`
26	37	dinesha	`Version : 0.0 - 8th Jan 2012`
27	31	dinesha	`Initial version with 16/32 Bit SDRAM Support`
28	37	dinesha	`: 0.1 - 24th Jan 2012`
29	31	dinesha	`8 Bit SDRAM Support is added`
30	37	dinesha	`0.2 - 31st Jan 2012`
31			`sdram_dq and sdram_pad_clk are internally generated`
32	31	dinesha
33
34			`Copyright (C) 2000 Authors and OPENCORES.ORG`
35
36			`This source file may be used and distributed without`
37			`restriction provided that this copyright statement is not`
38			`removed from the file and that any derivative work contains`
39			`the original copyright notice and the associated disclaimer.`
40
41			`This source file is free software; you can redistribute it`
42			`and/or modify it under the terms of the GNU Lesser General`
43			`Public License as published by the Free Software Foundation;`
44			`either version 2.1 of the License, or (at your option) any`
45			`later version.`
46
47			`This source is distributed in the hope that it will be`
48			`useful, but WITHOUT ANY WARRANTY; without even the implied`
49			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
50			`PURPOSE. See the GNU Lesser General Public License for more`
51			`details.`
52
53			`You should have received a copy of the GNU Lesser General`
54			`Public License along with this source; if not, download it`
55			`from http://www.opencores.org/lgpl.shtml`
56
57			`*******************************************************************/`
58
59
60	37	dinesha	`include "sdrc_define.v"
61	31	dinesha	`module sdrc_top`
62			`(`
63	38	dinesha	`cfg_sdr_width ,`
64	33	dinesha	`cfg_colbits ,`
65
66	31	dinesha	`// WB bus`
67	33	dinesha	`wb_rst_i ,`
68			`wb_clk_i ,`
69
70			`wb_stb_i ,`
71			`wb_ack_o ,`
72			`wb_addr_i ,`
73			`wb_we_i ,`
74			`wb_dat_i ,`
75			`wb_sel_i ,`
76			`wb_dat_o ,`
77			`wb_cyc_i ,`
78			`wb_cti_i ,`
79	31	dinesha
80
81			`/* Interface to SDRAMs */`
82	33	dinesha	`sdram_clk ,`
83			`sdram_resetn ,`
84			`sdr_cs_n ,`
85			`sdr_cke ,`
86			`sdr_ras_n ,`
87			`sdr_cas_n ,`
88			`sdr_we_n ,`
89			`sdr_dqm ,`
90			`sdr_ba ,`
91			`sdr_addr ,`
92	37	dinesha	`sdr_dq ,`
93	33	dinesha
94	31	dinesha	`/* Parameters */`
95	33	dinesha	`sdr_init_done ,`
96			`cfg_req_depth , //how many req. buffer should hold`
97			`cfg_sdr_en ,`
98			`cfg_sdr_mode_reg ,`
99			`cfg_sdr_tras_d ,`
100			`cfg_sdr_trp_d ,`
101			`cfg_sdr_trcd_d ,`
102			`cfg_sdr_cas ,`
103			`cfg_sdr_trcar_d ,`
104			`cfg_sdr_twr_d ,`
105			`cfg_sdr_rfsh ,`
106			`cfg_sdr_rfmax`
107			`);`
108	31	dinesha
109	33	dinesha	`parameter APP_AW = 30; // Application Address Width`
110			`parameter APP_DW = 32; // Application Data Width`
111			`parameter APP_BW = 4; // Application Byte Width`
112			`parameter APP_RW = 9; // Application Request Width`
113	31	dinesha
114	33	dinesha	`parameter SDR_DW = 16; // SDR Data Width`
115			`parameter SDR_BW = 2; // SDR Byte Width`
116	31	dinesha
117	33	dinesha	`parameter dw = 32; // data width`
118			`parameter tw = 8; // tag id width`
119			`parameter bl = 9; // burst_lenght_width`
120	31	dinesha
121			`//-----------------------------------------------`
122			`// Global Variable`
123			`// ----------------------------------------------`
124	33	dinesha	`input sdram_clk ; // SDRAM Clock`
125			`input sdram_resetn ; // Reset Signal`
126	38	dinesha	`input [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit`
127	33	dinesha	`input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,`
128			`// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits`
129	31	dinesha
130			`//--------------------------------------`
131			`// Wish Bone Interface`
132			`// -------------------------------------`
133	33	dinesha	`input wb_rst_i ;`
134			`input wb_clk_i ;`
135	31	dinesha
136	33	dinesha	`input wb_stb_i ;`
137			`output wb_ack_o ;`
138			`input [29:0] wb_addr_i ;`
139			`input wb_we_i ; // 1 - Write, 0 - Read`
140			`input [dw-1:0] wb_dat_i ;`
141			`input [dw/8-1:0] wb_sel_i ; // Byte enable`
142			`output [dw-1:0] wb_dat_o ;`
143			`input wb_cyc_i ;`
144			`input [2:0] wb_cti_i ;`
145	31	dinesha
146			`//------------------------------------------------`
147			`// Interface to SDRAMs`
148			`//------------------------------------------------`
149			`output sdr_cke ; // SDRAM CKE`
150			`output sdr_cs_n ; // SDRAM Chip Select`
151			`output sdr_ras_n ; // SDRAM ras`
152			`output sdr_cas_n ; // SDRAM cas`
153			`output sdr_we_n ; // SDRAM write enable`
154			`output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask`
155			`output [1:0] sdr_ba ; // SDRAM Bank Enable`
156			`output [11:0] sdr_addr ; // SDRAM Address`
157	37	dinesha	`inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output`
158	31	dinesha
159			`//------------------------------------------------`
160			`// Configuration Parameter`
161			`//------------------------------------------------`
162			`output sdr_init_done ; // Indicate SDRAM Initialisation Done`
163			`input [3:0] cfg_sdr_tras_d ; // Active to precharge delay`
164			`input [3:0] cfg_sdr_trp_d ; // Precharge to active delay`
165			`input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay`
166			`input cfg_sdr_en ; // Enable SDRAM controller`
167			`input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller`
168			`input [11:0] cfg_sdr_mode_reg ;`
169			`input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency`
170			`input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period`
171			`input [3:0] cfg_sdr_twr_d ; // Write recovery delay`
172			input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
173			input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
174
175			`//--------------------------------------------`
176			`// SDRAM controller Interface`
177			`//--------------------------------------------`
178			`wire app_req ; // SDRAM request`
179			`wire [29:0] app_req_addr ; // SDRAM Request Address`
180			`wire [bl-1:0] app_req_len ;`
181			`wire app_req_wr_n ; // 0 - Write, 1 -> Read`
182			`wire app_req_ack ; // SDRAM request Accepted`
183			`wire app_busy_n ; // 0 -> sdr busy`
184			`wire [dw/8-1:0] app_wr_en_n ; // Active low sdr byte-wise write data valid`
185			`wire app_wr_next_req ; // Ready to accept the next write`
186			`wire app_rd_valid ; // sdr read valid`
187			`wire app_last_rd ; // Indicate last Read of Burst Transfer`
188			`wire [dw-1:0] app_wr_data ; // sdr write data`
189			`wire [dw-1:0] app_rd_data ; // sdr read data`
190
191	37	dinesha	`/****************************************`
192			`* These logic has to be implemented using Pads`
193			`* **************************************/`
194			`wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input`
195			`wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output`
196			`wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable`
197
198
199			`assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};`
200			`assign pad_sdr_din = sdr_dq;`
201
202			`// sdram pad clock is routed back through pad`
203			`// SDRAM Clock from Pad, used for registering Read Data`
204			`wire #(1.0) sdram_pad_clk = sdram_clk;`
205
206			`/************ Ends Here ************************/`
207	31	dinesha	`wb2sdrc u_wb2sdrc (`
208			`// WB bus`
209			`.wb_rst_i (wb_rst_i ) ,`
210			`.wb_clk_i (wb_clk_i ) ,`
211
212			`.wb_stb_i (wb_stb_i ) ,`
213			`.wb_ack_o (wb_ack_o ) ,`
214			`.wb_addr_i (wb_addr_i ) ,`
215			`.wb_we_i (wb_we_i ) ,`
216			`.wb_dat_i (wb_dat_i ) ,`
217			`.wb_sel_i (wb_sel_i ) ,`
218			`.wb_dat_o (wb_dat_o ) ,`
219			`.wb_cyc_i (wb_cyc_i ) ,`
220			`.wb_cti_i (wb_cti_i ) ,`
221
222
223			`//SDRAM Controller Hand-Shake Signal`
224			`.sdram_clk (sdram_clk ) ,`
225			`.sdram_resetn (sdram_resetn ) ,`
226			`.sdr_req (app_req ) ,`
227			`.sdr_req_addr (app_req_addr ) ,`
228			`.sdr_req_len (app_req_len ) ,`
229			`.sdr_req_wr_n (app_req_wr_n ) ,`
230			`.sdr_req_ack (app_req_ack ) ,`
231			`.sdr_busy_n (app_busy_n ) ,`
232			`.sdr_wr_en_n (app_wr_en_n ) ,`
233			`.sdr_wr_next (app_wr_next_req ) ,`
234			`.sdr_rd_valid (app_rd_valid ) ,`
235			`.sdr_last_rd (app_last_rd ) ,`
236			`.sdr_wr_data (app_wr_data ) ,`
237			`.sdr_rd_data (app_rd_data )`
238
239			`);`
240
241
242			`sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (`
243			`.clk (sdram_clk ) ,`
244			`.pad_clk (sdram_pad_clk ) ,`
245			`.reset_n (sdram_resetn ) ,`
246	38	dinesha	`.sdr_width (cfg_sdr_width ) ,`
247	31	dinesha	`.cfg_colbits (cfg_colbits ) ,`
248
249			`/* Request from app */`
250			`.app_req (app_req ) ,// Transfer Request`
251			`.app_req_addr (app_req_addr ) ,// SDRAM Address`
252			`.app_req_addr_mask (29'h0 ) ,// Address mask for queue wrap`
253			`.app_req_len (app_req_len ) ,// Burst Length (in 16 bit words)`
254			`.app_req_wrap (1'b0 ) ,// Wrap mode request`
255			`.app_req_wr_n (app_req_wr_n ) ,// 0 => Write request, 1 => read req`
256			`.app_req_ack (app_req_ack ) ,// Request has been accepted`
257			`.sdr_core_busy_n (app_core_busy_n ) ,// OK to arbitrate next request`
258			`.cfg_req_depth (cfg_req_depth ) ,//how many req. buffer should hold`
259
260			`.app_wr_data (app_wr_data ) ,`
261			`.app_wr_en_n (app_wr_en_n ) ,`
262			`.app_rd_data (app_rd_data ) ,`
263			`.app_rd_valid (app_rd_valid ) ,`
264			`.app_last_rd (app_last_rd ) ,`
265			`.app_wr_next_req (app_wr_next_req ) ,`
266			`.sdr_init_done (sdr_init_done ) ,`
267			`.app_req_dma_last (app_req ) ,`
268
269			`/* Interface to SDRAMs */`
270			`.sdr_cs_n (sdr_cs_n ) ,`
271			`.sdr_cke (sdr_cke ) ,`
272			`.sdr_ras_n (sdr_ras_n ) ,`
273			`.sdr_cas_n (sdr_cas_n ) ,`
274			`.sdr_we_n (sdr_we_n ) ,`
275			`.sdr_dqm (sdr_dqm ) ,`
276			`.sdr_ba (sdr_ba ) ,`
277			`.sdr_addr (sdr_addr ) ,`
278			`.pad_sdr_din (pad_sdr_din ) ,`
279			`.sdr_dout (sdr_dout ) ,`
280			`.sdr_den_n (sdr_den_n ) ,`
281
282			`/* Parameters */`
283			`.cfg_sdr_en (cfg_sdr_en ) ,`
284			`.cfg_sdr_mode_reg (cfg_sdr_mode_reg ) ,`
285			`.cfg_sdr_tras_d (cfg_sdr_tras_d ) ,`
286			`.cfg_sdr_trp_d (cfg_sdr_trp_d ) ,`
287			`.cfg_sdr_trcd_d (cfg_sdr_trcd_d ) ,`
288			`.cfg_sdr_cas (cfg_sdr_cas ) ,`
289			`.cfg_sdr_trcar_d (cfg_sdr_trcar_d ) ,`
290			`.cfg_sdr_twr_d (cfg_sdr_twr_d ) ,`
291			`.cfg_sdr_rfsh (cfg_sdr_rfsh ) ,`
292			`.cfg_sdr_rfmax (cfg_sdr_rfmax )`
293			`);`
294
295			`endmodule // sdrc_core`

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