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dinesha |
/*********************************************************************
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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Description: WISHBONE to SDRAM Controller Bus Transalator
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dinesha |
1. This module translate the WISHBONE protocol to custom sdram controller i/f
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2. Also Handle the clock domain change from Application layer to Sdram layer
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dinesha |
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To Do:
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nothing
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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module wb2sdrc (
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// WB bus
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dinesha |
wb_rst_i ,
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wb_clk_i ,
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dinesha |
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dinesha |
wb_stb_i ,
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wb_ack_o ,
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wb_addr_i ,
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wb_we_i ,
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wb_dat_i ,
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wb_sel_i ,
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wb_dat_o ,
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wb_cyc_i ,
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wb_cti_i ,
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dinesha |
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//SDRAM Controller Hand-Shake Signal
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dinesha |
sdram_clk ,
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sdram_resetn ,
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sdr_req ,
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sdr_req_addr ,
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sdr_req_len ,
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sdr_req_wr_n ,
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sdr_req_ack ,
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sdr_busy_n ,
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sdr_wr_en_n ,
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sdr_wr_next ,
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sdr_rd_valid ,
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sdr_last_rd ,
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sdr_wr_data ,
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sdr_rd_data
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dinesha |
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);
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parameter dw = 32; // data width
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parameter tw = 8; // tag id width
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parameter bl = 9; // burst_lenght_width
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//--------------------------------------
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// Wish Bone Interface
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// -------------------------------------
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dinesha |
input wb_rst_i ;
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input wb_clk_i ;
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input wb_stb_i ;
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output wb_ack_o ;
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input [29:0] wb_addr_i ;
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input wb_we_i ; // 1 - Write , 0 - Read
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input [dw-1:0] wb_dat_i ;
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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output [dw-1:0] wb_dat_o ;
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input wb_cyc_i ;
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input [2:0] wb_cti_i ;
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dinesha |
/***************************************************
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The Cycle Type Idenfier [CTI_IO()] Address Tag provides
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additional information about the current cycle.
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The MASTER sends this information to the SLAVE. The SLAVE can use this
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information to prepare the response for the next cycle.
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Table 4-2 Cycle Type Identifiers
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CTI_O(2:0) Description
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‘000’ Classic cycle.
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‘001’ Constant address burst cycle
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‘010’ Incrementing burst cycle
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‘011’ Reserved
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‘100’ Reserved
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‘101 Reserved
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‘110’ Reserved
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‘111’ End-of-Burst
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****************************************************/
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//--------------------------------------------
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// SDRAM controller Interface
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//--------------------------------------------
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dinesha |
input sdram_clk ; // sdram clock
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input sdram_resetn ; // sdram reset
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dinesha |
output sdr_req ; // SDRAM request
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output [29:0] sdr_req_addr ; // SDRAM Request Address
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output [bl-1:0] sdr_req_len ;
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output sdr_req_wr_n ; // 0 - Write, 1 -> Read
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input sdr_req_ack ; // SDRAM request Accepted
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input sdr_busy_n ; // 0 -> sdr busy
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output [dw/8-1:0] sdr_wr_en_n ; // Active low sdr byte-wise write data valid
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input sdr_wr_next ; // Ready to accept the next write
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input sdr_rd_valid ; // sdr read valid
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input sdr_last_rd ; // Indicate last Read of Burst Transfer
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output [dw-1:0] sdr_wr_data ; // sdr write data
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input [dw-1:0] sdr_rd_data ; // sdr read data
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//----------------------------------------------------
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// Wire Decleration
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// ---------------------------------------------------
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dinesha |
wire cmdfifo_full ;
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wire cmdfifo_empty ;
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wire wrdatafifo_full ;
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wire wrdatafifo_empty ;
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wire tagfifo_full ;
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wire tagfifo_empty ;
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wire rddatafifo_empty ;
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wire rddatafifo_full ;
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dinesha |
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dinesha |
reg pending_read ;
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dinesha |
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dinesha |
//-----------------------------------------------------------------------------
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// Ack Generaltion Logic
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// If Write Request - Acknowledge if the command and write FIFO are not full
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// If Read Request - Generate the Acknowledgment once read fifo has data
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// available
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//-----------------------------------------------------------------------------
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dinesha |
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assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase
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((!cmdfifo_full) && (!wrdatafifo_full)) :
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(wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase
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!rddatafifo_empty : 1'b0;
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dinesha |
//---------------------------------------------------------------------------
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// Command FIFO Write Generation
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// If Write Request - Generate write, when Write fifo and command fifo is
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// not full
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// If Read Request - Generate write, when command fifo not full and there
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// is no pending read request.
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//---------------------------------------------------------------------------
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wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i && (!cmdfifo_full) ) ? wb_ack_o :
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(wb_stb_i && wb_cyc_i && !wb_we_i && (!cmdfifo_full)) ? !pending_read: 1'b0 ;
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//---------------------------------------------------------------------------
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// command fifo read generation
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// Command FIFo read will be generated, whenever SDRAM Controller
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// Acknowldge the Request
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//----------------------------------------------------------------------------
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dinesha |
wire cmdfifo_rd = sdr_req_ack;
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dinesha |
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//---------------------------------------------------------------------------
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// Application layer request is generated towards the controller, whenever
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// Command FIFO is not full
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// --------------------------------------------------------------------------
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dinesha |
assign sdr_req = !cmdfifo_empty;
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dinesha |
//----------------------------------------------------------------------------
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// Since Burst length is not known at the start of the Burst, It's assumed as
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// Single Cycle Burst. We need to improvise this ...
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// --------------------------------------------------------------------------
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dinesha |
wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer
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dinesha |
//-----------------------------------------------------------------------------
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// In Wish Bone Spec, For Read Request has to be acked along with data.
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// We need to identify the pending read request.
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// Once we accept the read request, we should not accept one more read
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// request, untill we have transmitted the read data.
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// Pending Read will
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// set - with Read Request
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// reset - with Read Request + Ack
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// ----------------------------------------------------------------------------
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dinesha |
always @(posedge wb_rst_i or posedge wb_clk_i) begin
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if(wb_rst_i) begin
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pending_read <= 1'b0;
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end else begin
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pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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end
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end
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dinesha |
//---------------------------------------------------------------------
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// Async Command FIFO. This block handle the clock domain change from
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// Application layer to SDRAM Controller
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// ------------------------------------------------------------------
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dinesha |
// Address + Burst Length + W/R Request
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async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
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// Write Path Sys CLock Domain
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dinesha |
.wr_clk (wb_clk_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_en (cmdfifo_wr ),
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.wr_data ({burst_length,
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!wb_we_i,
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wb_addr_i} ),
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.afull ( ),
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.full (cmdfifo_full ),
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dinesha |
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// Read Path, SDRAM clock domain
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dinesha |
.rd_clk (sdram_clk ),
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.rd_reset_n (sdram_resetn ),
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.aempty ( ),
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.empty (cmdfifo_empty ),
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.rd_en (cmdfifo_rd ),
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.rd_data ({sdr_req_len,
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sdr_req_wr_n,
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sdr_req_addr} )
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dinesha |
);
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// synopsys translate_off
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always @(posedge wb_clk_i) begin
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if (cmdfifo_full == 1'b1 && cmdfifo_wr == 1'b1) begin
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$display("ERROR:%m COMMAND FIFO WRITE OVERFLOW");
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end
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end
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// synopsys translate_off
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always @(posedge sdram_clk) begin
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if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin
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$display("ERROR:%m COMMAND FIFO READ OVERFLOW");
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end
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end
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// synopsys translate_on
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dinesha |
//---------------------------------------------------------------------
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// Write Data FIFO Write Generation, when ever Acked + Write Request
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// Note: Ack signal generation already taking account of FIFO full condition
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// ---------------------------------------------------------------------
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31 |
dinesha |
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wire wrdatafifo_wr = wb_ack_o & wb_we_i ;
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dinesha |
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//------------------------------------------------------------------------
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// Write Data FIFO Read Generation, When ever Next Write request generated
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// from SDRAM Controller
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// ------------------------------------------------------------------------
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dinesha |
wire wrdatafifo_rd = sdr_wr_next;
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dinesha |
//------------------------------------------------------------------------
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// Async Write Data FIFO
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// This block handle the clock domain change over + Write Data + Byte mask
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// From Application layer to SDRAM controller layer
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//------------------------------------------------------------------------
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dinesha |
// Write DATA + Data Mask FIFO
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async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
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// Write Path , System clock domain
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dinesha |
.wr_clk (wb_clk_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_en (wrdatafifo_wr ),
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.wr_data ({~wb_sel_i,
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wb_dat_i} ),
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.afull ( ),
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.full (wrdatafifo_full ),
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31 |
dinesha |
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// Read Path , SDRAM clock domain
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33 |
dinesha |
.rd_clk (sdram_clk ),
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.rd_reset_n (sdram_resetn ),
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.aempty ( ),
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.empty (wrdatafifo_empty ),
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.rd_en (wrdatafifo_rd ),
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.rd_data ({sdr_wr_en_n,
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sdr_wr_data} )
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31 |
dinesha |
);
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// synopsys translate_off
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always @(posedge wb_clk_i) begin
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if (wrdatafifo_full == 1'b1 && wrdatafifo_wr == 1'b1) begin
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$display("ERROR:%m WRITE DATA FIFO WRITE OVERFLOW");
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end
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end
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always @(posedge sdram_clk) begin
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if (wrdatafifo_empty == 1'b1 && wrdatafifo_rd == 1'b1) begin
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$display("ERROR:%m WRITE DATA FIFO READ OVERFLOW");
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end
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end
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295 |
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// synopsys translate_on
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296 |
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297 |
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// -------------------------------------------------------------------
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298 |
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// READ DATA FIFO
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299 |
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// ------------------------------------------------------------------
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300 |
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wire rd_eop; // last read indication
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301 |
33 |
dinesha |
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302 |
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// Read FIFO write generation, when ever SDRAM controller issues the read
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303 |
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// valid signal
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304 |
31 |
dinesha |
wire rddatafifo_wr = sdr_rd_valid;
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305 |
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306 |
33 |
dinesha |
// Read FIFO read generation, when ever ack is generated along with read
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307 |
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// request.
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308 |
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// Note: Ack generation is already accounted the write FIFO Not Empty
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309 |
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// condition
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310 |
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wire rddatafifo_rd = wb_ack_o & !wb_we_i;
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311 |
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312 |
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//-------------------------------------------------------------------------
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313 |
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// Async Read FIFO
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314 |
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// This block handles the clock domain change over + Read data from SDRAM
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315 |
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// controller to Application layer.
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316 |
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// Note:
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317 |
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// 1. READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
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318 |
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// READ DATA + EOP
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319 |
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// 2. EOP indicate, last transfer of Burst Read Access. use-full for future
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320 |
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// Tag handling per burst
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321 |
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//
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322 |
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// ------------------------------------------------------------------------
|
323 |
31 |
dinesha |
async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
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324 |
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// Write Path , SDRAM clock domain
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325 |
33 |
dinesha |
.wr_clk (sdram_clk ),
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326 |
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.wr_reset_n (sdram_resetn ),
|
327 |
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.wr_en (rddatafifo_wr ),
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328 |
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.wr_data ({sdr_last_rd,
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329 |
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sdr_rd_data} ),
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330 |
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.afull ( ),
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331 |
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.full (rddatafifo_full ),
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332 |
31 |
dinesha |
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333 |
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334 |
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// Read Path , SYS clock domain
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335 |
33 |
dinesha |
.rd_clk (wb_clk_i ),
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336 |
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.rd_reset_n (!wb_rst_i ),
|
337 |
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.empty (rddatafifo_empty ),
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338 |
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.aempty ( ),
|
339 |
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.rd_en (rddatafifo_rd ),
|
340 |
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.rd_data ({rd_eop,
|
341 |
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wb_dat_o} )
|
342 |
31 |
dinesha |
);
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343 |
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344 |
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// synopsys translate_off
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345 |
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always @(posedge sdram_clk) begin
|
346 |
|
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if (rddatafifo_full == 1'b1 && rddatafifo_wr == 1'b1) begin
|
347 |
|
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$display("ERROR:%m READ DATA FIFO WRITE OVERFLOW");
|
348 |
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end
|
349 |
|
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end
|
350 |
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|
351 |
|
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always @(posedge wb_clk_i) begin
|
352 |
|
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if (rddatafifo_empty == 1'b1 && rddatafifo_rd == 1'b1) begin
|
353 |
|
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$display("ERROR:%m READ DATA FIFO READ OVERFLOW");
|
354 |
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end
|
355 |
|
|
end
|
356 |
|
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// synopsys translate_on
|
357 |
|
|
|
358 |
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|
|
359 |
|
|
endmodule
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