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27 |
dinesha |
Compiling with MODELSIM in core SDR_32BIT Mode
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Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010
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-- Compiling module tb_core
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-- Compiling module IS42VM16400K
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-- Compiling module mt48lc2m32b2
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-- Compiling module mt48lc8m8a2
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-- Compiling module sdrc_core
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-- Compiling module sdrc_bank_ctl
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-- Compiling module sdrc_bank_fsm
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-- Compiling module sdrc_bs_convert
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-- Compiling module sdrc_req_gen
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-- Compiling module sdrc_xfr_ctl
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Top level modules:
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tb_core
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IS42VM16400K
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mt48lc8m8a2
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#### Compile : PASSED
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###########################################
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Runing GMAC/SPI/UART test programs
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###########################################
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###########################################
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### Running test 1: basic_test1
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Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
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# 6.6d
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# vsim +basic_test1 -do run.do -c tb_core
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# // ModelSim ACTEL 6.6d Nov 2 2010
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# //
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# // Copyright 1991-2010 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // THIS WORK CONTAINS TRADE SECRET AND
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# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
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# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
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# // AND IS SUBJECT TO LICENSE TERMS.
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# //
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# Loading sv_std.std
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# Loading work.tb_core
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# Loading work.sdrc_core
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# Loading work.sdrc_req_gen
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# Loading work.sdrc_bank_ctl
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# Loading work.sdrc_bank_fsm
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# Loading work.sdrc_xfr_ctl
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# Loading work.sdrc_bs_convert
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# Loading work.mt48lc2m32b2
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28 |
dinesha |
# ** Warning: (vsim-3015) ../tb/tb_core.sv(195): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
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27 |
dinesha |
# Region: /tb_core/u_sdram32
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# do run.do
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# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 10247.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 10337.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 10427.0 ns AREF : Auto Refresh
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| 56 |
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# tb_core.u_sdram32 : at time 10517.0 ns AREF : Auto Refresh
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| 57 |
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# tb_core.u_sdram32 : at time 10607.0 ns AREF : Auto Refresh
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| 58 |
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# tb_core.u_sdram32 : at time 10697.0 ns AREF : Auto Refresh
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| 59 |
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# tb_core.u_sdram32 : at time 10787.0 ns AREF : Auto Refresh
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| 60 |
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# tb_core.u_sdram32 : at time 10877.0 ns AREF : Auto Refresh
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| 61 |
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# tb_core.u_sdram32 : at time 10967.0 ns AREF : Auto Refresh
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| 62 |
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# tb_core.u_sdram32 : at time 11057.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 11147.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 11237.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 11327.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 11417.0 ns AREF : Auto Refresh
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# tb_core.u_sdram32 : at time 11507.0 ns LMR : Load Mode Register
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# tb_core.u_sdram32 : CAS Latency = 3
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# tb_core.u_sdram32 : Burst Length = 8
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# tb_core.u_sdram32 : Burst Type = Sequential
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# tb_core.u_sdram32 : Write Burst Mode = Programmed Burst Length
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# Write Address: 00040000, Burst Size: 5
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# tb_core.u_sdram32 : at time 12647.0 ns ACT : Bank = 0 Row = 64
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# tb_core.u_sdram32 : at time 12677.0 ns WRITE: Bank = 0 Row = 64, Col = 0, Data = 11223344
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# Status: Burst-No: 0 Write Address: 00040000 WriteData: 11223344
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# tb_core.u_sdram32 : at time 12687.0 ns WRITE: Bank = 0 Row = 64, Col = 1, Data = 22334455
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# Status: Burst-No: 1 Write Address: 00040000 WriteData: 22334455
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# tb_core.u_sdram32 : at time 12697.0 ns WRITE: Bank = 0 Row = 64, Col = 2, Data = 33445566
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# Status: Burst-No: 2 Write Address: 00040000 WriteData: 33445566
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# tb_core.u_sdram32 : at time 12707.0 ns WRITE: Bank = 0 Row = 64, Col = 3, Data = 44556677
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# Status: Burst-No: 3 Write Address: 00040000 WriteData: 44556677
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# tb_core.u_sdram32 : at time 12717.0 ns WRITE: Bank = 0 Row = 64, Col = 4, Data = 55667788
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# Status: Burst-No: 4 Write Address: 00040000 WriteData: 55667788
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# tb_core.u_sdram32 : at time 12727.0 ns BST : Burst Terminate
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# tb_core.u_sdram32 : at time 13763.0 ns READ : Bank = 0 Row = 64, Col = 0, Data = 11223344
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# tb_core.u_sdram32 : at time 13773.0 ns READ : Bank = 0 Row = 64, Col = 1, Data = 22334455
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# READ STATUS: Burst-No: 0 Addr: 00040000 Rxd: 11223344
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# tb_core.u_sdram32 : at time 13783.0 ns READ : Bank = 0 Row = 64, Col = 2, Data = 33445566
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# tb_core.u_sdram32 : at time 13787.0 ns BST : Burst Terminate
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# READ STATUS: Burst-No: 1 Addr: 00040002 Rxd: 22334455
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# tb_core.u_sdram32 : at time 13793.0 ns READ : Bank = 0 Row = 64, Col = 3, Data = 44556677
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# READ STATUS: Burst-No: 2 Addr: 00040004 Rxd: 33445566
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| 93 |
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# tb_core.u_sdram32 : at time 13803.0 ns READ : Bank = 0 Row = 64, Col = 4, Data = 55667788
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# READ STATUS: Burst-No: 3 Addr: 00040006 Rxd: 44556677
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# READ STATUS: Burst-No: 4 Addr: 00040008 Rxd: 55667788
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# Write Address: 70000000, Burst Size: 5
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# tb_core.u_sdram32 : at time 14877.0 ns ACT : Bank = 0 Row = 0
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# tb_core.u_sdram32 : at time 14907.0 ns WRITE: Bank = 0 Row = 0, Col = 0, Data = 11223344
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# Status: Burst-No: 0 Write Address: 70000000 WriteData: 11223344
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# tb_core.u_sdram32 : at time 14917.0 ns WRITE: Bank = 0 Row = 0, Col = 1, Data = 22334455
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# Status: Burst-No: 1 Write Address: 70000000 WriteData: 22334455
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# tb_core.u_sdram32 : at time 14927.0 ns WRITE: Bank = 0 Row = 0, Col = 2, Data = 33445566
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# Status: Burst-No: 2 Write Address: 70000000 WriteData: 33445566
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# tb_core.u_sdram32 : at time 14937.0 ns WRITE: Bank = 0 Row = 0, Col = 3, Data = 44556677
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# Status: Burst-No: 3 Write Address: 70000000 WriteData: 44556677
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# tb_core.u_sdram32 : at time 14947.0 ns WRITE: Bank = 0 Row = 0, Col = 4, Data = 55667788
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# Status: Burst-No: 4 Write Address: 70000000 WriteData: 55667788
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# tb_core.u_sdram32 : at time 14957.0 ns BST : Burst Terminate
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# tb_core.u_sdram32 : at time 15993.0 ns READ : Bank = 0 Row = 0, Col = 0, Data = 11223344
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# tb_core.u_sdram32 : at time 16003.0 ns READ : Bank = 0 Row = 0, Col = 1, Data = 22334455
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# READ STATUS: Burst-No: 0 Addr: 70000000 Rxd: 11223344
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| 112 |
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# tb_core.u_sdram32 : at time 16013.0 ns READ : Bank = 0 Row = 0, Col = 2, Data = 33445566
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# tb_core.u_sdram32 : at time 16017.0 ns BST : Burst Terminate
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# READ STATUS: Burst-No: 1 Addr: 70000002 Rxd: 22334455
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| 115 |
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# tb_core.u_sdram32 : at time 16023.0 ns READ : Bank = 0 Row = 0, Col = 3, Data = 44556677
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| 116 |
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# READ STATUS: Burst-No: 2 Addr: 70000004 Rxd: 33445566
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| 117 |
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# tb_core.u_sdram32 : at time 16033.0 ns READ : Bank = 0 Row = 0, Col = 4, Data = 55667788
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| 118 |
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# READ STATUS: Burst-No: 3 Addr: 70000006 Rxd: 44556677
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| 119 |
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# READ STATUS: Burst-No: 4 Addr: 70000008 Rxd: 55667788
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# Write Address: 02153524, Burst Size: 5
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# tb_core.u_sdram32 : at time 16117.0 ns ACT : Bank = 1 Row = 339
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# tb_core.u_sdram32 : at time 16147.0 ns WRITE: Bank = 1 Row = 339, Col = 73, Data = 11223344
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# Status: Burst-No: 0 Write Address: 02153524 WriteData: 11223344
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# tb_core.u_sdram32 : at time 16157.0 ns WRITE: Bank = 1 Row = 339, Col = 74, Data = 22334455
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# Status: Burst-No: 1 Write Address: 02153524 WriteData: 22334455
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| 126 |
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# tb_core.u_sdram32 : at time 16167.0 ns WRITE: Bank = 1 Row = 339, Col = 75, Data = 33445566
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| 127 |
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# Status: Burst-No: 2 Write Address: 02153524 WriteData: 33445566
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| 128 |
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# tb_core.u_sdram32 : at time 16177.0 ns WRITE: Bank = 1 Row = 339, Col = 76, Data = 44556677
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| 129 |
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# Status: Burst-No: 3 Write Address: 02153524 WriteData: 44556677
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| 130 |
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# tb_core.u_sdram32 : at time 16187.0 ns WRITE: Bank = 1 Row = 339, Col = 77, Data = 55667788
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| 131 |
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# Status: Burst-No: 4 Write Address: 02153524 WriteData: 55667788
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| 132 |
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# tb_core.u_sdram32 : at time 16197.0 ns BST : Burst Terminate
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| 133 |
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# tb_core.u_sdram32 : at time 17233.0 ns READ : Bank = 1 Row = 339, Col = 73, Data = 11223344
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| 134 |
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# tb_core.u_sdram32 : at time 17243.0 ns READ : Bank = 1 Row = 339, Col = 74, Data = 22334455
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| 135 |
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# READ STATUS: Burst-No: 0 Addr: 02153524 Rxd: 11223344
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| 136 |
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# tb_core.u_sdram32 : at time 17253.0 ns READ : Bank = 1 Row = 339, Col = 75, Data = 33445566
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| 137 |
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# tb_core.u_sdram32 : at time 17257.0 ns BST : Burst Terminate
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| 138 |
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# READ STATUS: Burst-No: 1 Addr: 02153526 Rxd: 22334455
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| 139 |
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# tb_core.u_sdram32 : at time 17263.0 ns READ : Bank = 1 Row = 339, Col = 76, Data = 44556677
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| 140 |
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# READ STATUS: Burst-No: 2 Addr: 02153528 Rxd: 33445566
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| 141 |
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# tb_core.u_sdram32 : at time 17273.0 ns READ : Bank = 1 Row = 339, Col = 77, Data = 55667788
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| 142 |
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# READ STATUS: Burst-No: 3 Addr: 0215352a Rxd: 44556677
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| 143 |
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# READ STATUS: Burst-No: 4 Addr: 0215352c Rxd: 55667788
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| 144 |
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# Write Address: 00895e81, Burst Size: 5
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| 145 |
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# tb_core.u_sdram32 : at time 17357.0 ns ACT : Bank = 3 Row = 149
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| 146 |
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# tb_core.u_sdram32 : at time 17387.0 ns WRITE: Bank = 3 Row = 149, Col = 160, Data = 11223344
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| 147 |
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# Status: Burst-No: 0 Write Address: 00895e81 WriteData: 11223344
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| 148 |
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# tb_core.u_sdram32 : at time 17397.0 ns WRITE: Bank = 3 Row = 149, Col = 161, Data = 22334455
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| 149 |
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# Status: Burst-No: 1 Write Address: 00895e81 WriteData: 22334455
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| 150 |
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# tb_core.u_sdram32 : at time 17407.0 ns WRITE: Bank = 3 Row = 149, Col = 162, Data = 33445566
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| 151 |
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# Status: Burst-No: 2 Write Address: 00895e81 WriteData: 33445566
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| 152 |
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# tb_core.u_sdram32 : at time 17417.0 ns WRITE: Bank = 3 Row = 149, Col = 163, Data = 44556677
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| 153 |
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# Status: Burst-No: 3 Write Address: 00895e81 WriteData: 44556677
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| 154 |
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# tb_core.u_sdram32 : at time 17427.0 ns WRITE: Bank = 3 Row = 149, Col = 164, Data = 55667788
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| 155 |
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# Status: Burst-No: 4 Write Address: 00895e81 WriteData: 55667788
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| 156 |
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# tb_core.u_sdram32 : at time 17437.0 ns BST : Burst Terminate
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| 157 |
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# tb_core.u_sdram32 : at time 18473.0 ns READ : Bank = 3 Row = 149, Col = 160, Data = 11223344
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| 158 |
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# tb_core.u_sdram32 : at time 18483.0 ns READ : Bank = 3 Row = 149, Col = 161, Data = 22334455
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| 159 |
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# READ STATUS: Burst-No: 0 Addr: 00895e81 Rxd: 11223344
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| 160 |
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# tb_core.u_sdram32 : at time 18493.0 ns READ : Bank = 3 Row = 149, Col = 162, Data = 33445566
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| 161 |
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# tb_core.u_sdram32 : at time 18497.0 ns BST : Burst Terminate
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| 162 |
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# READ STATUS: Burst-No: 1 Addr: 00895e83 Rxd: 22334455
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| 163 |
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# tb_core.u_sdram32 : at time 18503.0 ns READ : Bank = 3 Row = 149, Col = 163, Data = 44556677
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| 164 |
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# READ STATUS: Burst-No: 2 Addr: 00895e85 Rxd: 33445566
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| 165 |
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# tb_core.u_sdram32 : at time 18513.0 ns READ : Bank = 3 Row = 149, Col = 164, Data = 55667788
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| 166 |
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# READ STATUS: Burst-No: 3 Addr: 00895e87 Rxd: 44556677
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| 167 |
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# READ STATUS: Burst-No: 4 Addr: 00895e89 Rxd: 55667788
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| 168 |
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# Write Address: 0484d609, Burst Size: 5
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| 169 |
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# tb_core.u_sdram32 : at time 18597.0 ns ACT : Bank = 1 Row = 77
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| 170 |
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# tb_core.u_sdram32 : at time 18627.0 ns WRITE: Bank = 1 Row = 77, Col = 130, Data = 11223344
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| 171 |
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# Status: Burst-No: 0 Write Address: 0484d609 WriteData: 11223344
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| 172 |
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# tb_core.u_sdram32 : at time 18637.0 ns WRITE: Bank = 1 Row = 77, Col = 131, Data = 22334455
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| 173 |
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# Status: Burst-No: 1 Write Address: 0484d609 WriteData: 22334455
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| 174 |
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# tb_core.u_sdram32 : at time 18647.0 ns WRITE: Bank = 1 Row = 77, Col = 132, Data = 33445566
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| 175 |
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# Status: Burst-No: 2 Write Address: 0484d609 WriteData: 33445566
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| 176 |
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# tb_core.u_sdram32 : at time 18657.0 ns WRITE: Bank = 1 Row = 77, Col = 133, Data = 44556677
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| 177 |
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# Status: Burst-No: 3 Write Address: 0484d609 WriteData: 44556677
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| 178 |
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# tb_core.u_sdram32 : at time 18667.0 ns WRITE: Bank = 1 Row = 77, Col = 134, Data = 55667788
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| 179 |
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# Status: Burst-No: 4 Write Address: 0484d609 WriteData: 55667788
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| 180 |
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# tb_core.u_sdram32 : at time 18677.0 ns BST : Burst Terminate
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| 181 |
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# tb_core.u_sdram32 : at time 19713.0 ns READ : Bank = 1 Row = 77, Col = 130, Data = 11223344
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| 182 |
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# tb_core.u_sdram32 : at time 19723.0 ns READ : Bank = 1 Row = 77, Col = 131, Data = 22334455
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| 183 |
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# READ STATUS: Burst-No: 0 Addr: 0484d609 Rxd: 11223344
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| 184 |
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# tb_core.u_sdram32 : at time 19733.0 ns READ : Bank = 1 Row = 77, Col = 132, Data = 33445566
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| 185 |
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# tb_core.u_sdram32 : at time 19737.0 ns BST : Burst Terminate
|
| 186 |
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# READ STATUS: Burst-No: 1 Addr: 0484d60b Rxd: 22334455
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| 187 |
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# tb_core.u_sdram32 : at time 19743.0 ns READ : Bank = 1 Row = 77, Col = 133, Data = 44556677
|
| 188 |
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# READ STATUS: Burst-No: 2 Addr: 0484d60d Rxd: 33445566
|
| 189 |
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# tb_core.u_sdram32 : at time 19753.0 ns READ : Bank = 1 Row = 77, Col = 134, Data = 55667788
|
| 190 |
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# READ STATUS: Burst-No: 3 Addr: 0484d60f Rxd: 44556677
|
| 191 |
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# READ STATUS: Burst-No: 4 Addr: 0484d611 Rxd: 55667788
|
| 192 |
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# Write Address: 01f05663, Burst Size: 5
|
| 193 |
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# tb_core.u_sdram32 : at time 19837.0 ns ACT : Bank = 1 Row = 1797
|
| 194 |
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# tb_core.u_sdram32 : at time 19867.0 ns WRITE: Bank = 1 Row = 1797, Col = 152, Data = 11223344
|
| 195 |
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# Status: Burst-No: 0 Write Address: 01f05663 WriteData: 11223344
|
| 196 |
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# tb_core.u_sdram32 : at time 19877.0 ns WRITE: Bank = 1 Row = 1797, Col = 153, Data = 22334455
|
| 197 |
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# Status: Burst-No: 1 Write Address: 01f05663 WriteData: 22334455
|
| 198 |
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# tb_core.u_sdram32 : at time 19887.0 ns WRITE: Bank = 1 Row = 1797, Col = 154, Data = 33445566
|
| 199 |
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# Status: Burst-No: 2 Write Address: 01f05663 WriteData: 33445566
|
| 200 |
|
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# tb_core.u_sdram32 : at time 19897.0 ns WRITE: Bank = 1 Row = 1797, Col = 155, Data = 44556677
|
| 201 |
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# Status: Burst-No: 3 Write Address: 01f05663 WriteData: 44556677
|
| 202 |
|
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# tb_core.u_sdram32 : at time 19907.0 ns WRITE: Bank = 1 Row = 1797, Col = 156, Data = 55667788
|
| 203 |
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# Status: Burst-No: 4 Write Address: 01f05663 WriteData: 55667788
|
| 204 |
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# tb_core.u_sdram32 : at time 19917.0 ns BST : Burst Terminate
|
| 205 |
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# tb_core.u_sdram32 : at time 20953.0 ns READ : Bank = 1 Row = 1797, Col = 152, Data = 11223344
|
| 206 |
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# tb_core.u_sdram32 : at time 20963.0 ns READ : Bank = 1 Row = 1797, Col = 153, Data = 22334455
|
| 207 |
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# READ STATUS: Burst-No: 0 Addr: 01f05663 Rxd: 11223344
|
| 208 |
|
|
# tb_core.u_sdram32 : at time 20973.0 ns READ : Bank = 1 Row = 1797, Col = 154, Data = 33445566
|
| 209 |
|
|
# tb_core.u_sdram32 : at time 20977.0 ns BST : Burst Terminate
|
| 210 |
|
|
# READ STATUS: Burst-No: 1 Addr: 01f05665 Rxd: 22334455
|
| 211 |
|
|
# tb_core.u_sdram32 : at time 20983.0 ns READ : Bank = 1 Row = 1797, Col = 155, Data = 44556677
|
| 212 |
|
|
# READ STATUS: Burst-No: 2 Addr: 01f05667 Rxd: 33445566
|
| 213 |
|
|
# tb_core.u_sdram32 : at time 20993.0 ns READ : Bank = 1 Row = 1797, Col = 156, Data = 55667788
|
| 214 |
|
|
# READ STATUS: Burst-No: 3 Addr: 01f05669 Rxd: 44556677
|
| 215 |
|
|
# READ STATUS: Burst-No: 4 Addr: 01f0566b Rxd: 55667788
|
| 216 |
|
|
# Write Address: 06b97b0d, Burst Size: 5
|
| 217 |
|
|
# tb_core.u_sdram32 : at time 21077.0 ns ACT : Bank = 2 Row = 919
|
| 218 |
|
|
# tb_core.u_sdram32 : at time 21107.0 ns WRITE: Bank = 2 Row = 919, Col = 195, Data = 11223344
|
| 219 |
|
|
# Status: Burst-No: 0 Write Address: 06b97b0d WriteData: 11223344
|
| 220 |
|
|
# tb_core.u_sdram32 : at time 21117.0 ns WRITE: Bank = 2 Row = 919, Col = 196, Data = 22334455
|
| 221 |
|
|
# Status: Burst-No: 1 Write Address: 06b97b0d WriteData: 22334455
|
| 222 |
|
|
# tb_core.u_sdram32 : at time 21127.0 ns WRITE: Bank = 2 Row = 919, Col = 197, Data = 33445566
|
| 223 |
|
|
# Status: Burst-No: 2 Write Address: 06b97b0d WriteData: 33445566
|
| 224 |
|
|
# tb_core.u_sdram32 : at time 21137.0 ns WRITE: Bank = 2 Row = 919, Col = 198, Data = 44556677
|
| 225 |
|
|
# Status: Burst-No: 3 Write Address: 06b97b0d WriteData: 44556677
|
| 226 |
|
|
# tb_core.u_sdram32 : at time 21147.0 ns WRITE: Bank = 2 Row = 919, Col = 199, Data = 55667788
|
| 227 |
|
|
# Status: Burst-No: 4 Write Address: 06b97b0d WriteData: 55667788
|
| 228 |
|
|
# tb_core.u_sdram32 : at time 21157.0 ns BST : Burst Terminate
|
| 229 |
|
|
# tb_core.u_sdram32 : at time 22193.0 ns READ : Bank = 2 Row = 919, Col = 195, Data = 11223344
|
| 230 |
|
|
# tb_core.u_sdram32 : at time 22203.0 ns READ : Bank = 2 Row = 919, Col = 196, Data = 22334455
|
| 231 |
|
|
# READ STATUS: Burst-No: 0 Addr: 06b97b0d Rxd: 11223344
|
| 232 |
|
|
# tb_core.u_sdram32 : at time 22213.0 ns READ : Bank = 2 Row = 919, Col = 197, Data = 33445566
|
| 233 |
|
|
# tb_core.u_sdram32 : at time 22217.0 ns BST : Burst Terminate
|
| 234 |
|
|
# READ STATUS: Burst-No: 1 Addr: 06b97b0f Rxd: 22334455
|
| 235 |
|
|
# tb_core.u_sdram32 : at time 22223.0 ns READ : Bank = 2 Row = 919, Col = 198, Data = 44556677
|
| 236 |
|
|
# READ STATUS: Burst-No: 2 Addr: 06b97b11 Rxd: 33445566
|
| 237 |
|
|
# tb_core.u_sdram32 : at time 22233.0 ns READ : Bank = 2 Row = 919, Col = 199, Data = 55667788
|
| 238 |
|
|
# READ STATUS: Burst-No: 3 Addr: 06b97b13 Rxd: 44556677
|
| 239 |
|
|
# READ STATUS: Burst-No: 4 Addr: 06b97b15 Rxd: 55667788
|
| 240 |
|
|
# Write Address: 06df998d, Burst Size: 5
|
| 241 |
|
|
# tb_core.u_sdram32 : at time 22317.0 ns ACT : Bank = 2 Row = 1529
|
| 242 |
|
|
# tb_core.u_sdram32 : at time 22347.0 ns WRITE: Bank = 2 Row = 1529, Col = 99, Data = 11223344
|
| 243 |
|
|
# Status: Burst-No: 0 Write Address: 06df998d WriteData: 11223344
|
| 244 |
|
|
# tb_core.u_sdram32 : at time 22357.0 ns WRITE: Bank = 2 Row = 1529, Col = 100, Data = 22334455
|
| 245 |
|
|
# Status: Burst-No: 1 Write Address: 06df998d WriteData: 22334455
|
| 246 |
|
|
# tb_core.u_sdram32 : at time 22367.0 ns WRITE: Bank = 2 Row = 1529, Col = 101, Data = 33445566
|
| 247 |
|
|
# Status: Burst-No: 2 Write Address: 06df998d WriteData: 33445566
|
| 248 |
|
|
# tb_core.u_sdram32 : at time 22377.0 ns WRITE: Bank = 2 Row = 1529, Col = 102, Data = 44556677
|
| 249 |
|
|
# Status: Burst-No: 3 Write Address: 06df998d WriteData: 44556677
|
| 250 |
|
|
# tb_core.u_sdram32 : at time 22387.0 ns WRITE: Bank = 2 Row = 1529, Col = 103, Data = 55667788
|
| 251 |
|
|
# Status: Burst-No: 4 Write Address: 06df998d WriteData: 55667788
|
| 252 |
|
|
# tb_core.u_sdram32 : at time 22397.0 ns BST : Burst Terminate
|
| 253 |
|
|
# tb_core.u_sdram32 : at time 23433.0 ns READ : Bank = 2 Row = 1529, Col = 99, Data = 11223344
|
| 254 |
|
|
# tb_core.u_sdram32 : at time 23443.0 ns READ : Bank = 2 Row = 1529, Col = 100, Data = 22334455
|
| 255 |
|
|
# READ STATUS: Burst-No: 0 Addr: 06df998d Rxd: 11223344
|
| 256 |
|
|
# tb_core.u_sdram32 : at time 23453.0 ns READ : Bank = 2 Row = 1529, Col = 101, Data = 33445566
|
| 257 |
|
|
# tb_core.u_sdram32 : at time 23457.0 ns BST : Burst Terminate
|
| 258 |
|
|
# READ STATUS: Burst-No: 1 Addr: 06df998f Rxd: 22334455
|
| 259 |
|
|
# tb_core.u_sdram32 : at time 23463.0 ns READ : Bank = 2 Row = 1529, Col = 102, Data = 44556677
|
| 260 |
|
|
# READ STATUS: Burst-No: 2 Addr: 06df9991 Rxd: 33445566
|
| 261 |
|
|
# tb_core.u_sdram32 : at time 23473.0 ns READ : Bank = 2 Row = 1529, Col = 103, Data = 55667788
|
| 262 |
|
|
# READ STATUS: Burst-No: 3 Addr: 06df9993 Rxd: 44556677
|
| 263 |
|
|
# READ STATUS: Burst-No: 4 Addr: 06df9995 Rxd: 55667788
|
| 264 |
|
|
# Write Address: 02c28465, Burst Size: 5
|
| 265 |
|
|
# tb_core.u_sdram32 : at time 23557.0 ns ACT : Bank = 1 Row = 1064
|
| 266 |
|
|
# tb_core.u_sdram32 : at time 23587.0 ns WRITE: Bank = 1 Row = 1064, Col = 25, Data = 11223344
|
| 267 |
|
|
# Status: Burst-No: 0 Write Address: 02c28465 WriteData: 11223344
|
| 268 |
|
|
# tb_core.u_sdram32 : at time 23597.0 ns WRITE: Bank = 1 Row = 1064, Col = 26, Data = 22334455
|
| 269 |
|
|
# Status: Burst-No: 1 Write Address: 02c28465 WriteData: 22334455
|
| 270 |
|
|
# tb_core.u_sdram32 : at time 23607.0 ns WRITE: Bank = 1 Row = 1064, Col = 27, Data = 33445566
|
| 271 |
|
|
# Status: Burst-No: 2 Write Address: 02c28465 WriteData: 33445566
|
| 272 |
|
|
# tb_core.u_sdram32 : at time 23617.0 ns WRITE: Bank = 1 Row = 1064, Col = 28, Data = 44556677
|
| 273 |
|
|
# Status: Burst-No: 3 Write Address: 02c28465 WriteData: 44556677
|
| 274 |
|
|
# tb_core.u_sdram32 : at time 23627.0 ns WRITE: Bank = 1 Row = 1064, Col = 29, Data = 55667788
|
| 275 |
|
|
# Status: Burst-No: 4 Write Address: 02c28465 WriteData: 55667788
|
| 276 |
|
|
# tb_core.u_sdram32 : at time 23637.0 ns BST : Burst Terminate
|
| 277 |
|
|
# tb_core.u_sdram32 : at time 24673.0 ns READ : Bank = 1 Row = 1064, Col = 25, Data = 11223344
|
| 278 |
|
|
# tb_core.u_sdram32 : at time 24683.0 ns READ : Bank = 1 Row = 1064, Col = 26, Data = 22334455
|
| 279 |
|
|
# READ STATUS: Burst-No: 0 Addr: 02c28465 Rxd: 11223344
|
| 280 |
|
|
# tb_core.u_sdram32 : at time 24693.0 ns READ : Bank = 1 Row = 1064, Col = 27, Data = 33445566
|
| 281 |
|
|
# tb_core.u_sdram32 : at time 24697.0 ns BST : Burst Terminate
|
| 282 |
|
|
# READ STATUS: Burst-No: 1 Addr: 02c28467 Rxd: 22334455
|
| 283 |
|
|
# tb_core.u_sdram32 : at time 24703.0 ns READ : Bank = 1 Row = 1064, Col = 28, Data = 44556677
|
| 284 |
|
|
# READ STATUS: Burst-No: 2 Addr: 02c28469 Rxd: 33445566
|
| 285 |
|
|
# tb_core.u_sdram32 : at time 24713.0 ns READ : Bank = 1 Row = 1064, Col = 29, Data = 55667788
|
| 286 |
|
|
# READ STATUS: Burst-No: 3 Addr: 02c2846b Rxd: 44556677
|
| 287 |
|
|
# READ STATUS: Burst-No: 4 Addr: 02c2846d Rxd: 55667788
|
| 288 |
|
|
# Write Address: 01375212, Burst Size: 5
|
| 289 |
|
|
# tb_core.u_sdram32 : at time 24797.0 ns ACT : Bank = 0 Row = 885
|
| 290 |
|
|
# tb_core.u_sdram32 : at time 24827.0 ns WRITE: Bank = 0 Row = 885, Col = 132, Data = 11223344
|
| 291 |
|
|
# Status: Burst-No: 0 Write Address: 01375212 WriteData: 11223344
|
| 292 |
|
|
# tb_core.u_sdram32 : at time 24837.0 ns WRITE: Bank = 0 Row = 885, Col = 133, Data = 22334455
|
| 293 |
|
|
# Status: Burst-No: 1 Write Address: 01375212 WriteData: 22334455
|
| 294 |
|
|
# tb_core.u_sdram32 : at time 24847.0 ns WRITE: Bank = 0 Row = 885, Col = 134, Data = 33445566
|
| 295 |
|
|
# Status: Burst-No: 2 Write Address: 01375212 WriteData: 33445566
|
| 296 |
|
|
# tb_core.u_sdram32 : at time 24857.0 ns WRITE: Bank = 0 Row = 885, Col = 135, Data = 44556677
|
| 297 |
|
|
# Status: Burst-No: 3 Write Address: 01375212 WriteData: 44556677
|
| 298 |
|
|
# tb_core.u_sdram32 : at time 24867.0 ns WRITE: Bank = 0 Row = 885, Col = 136, Data = 55667788
|
| 299 |
|
|
# Status: Burst-No: 4 Write Address: 01375212 WriteData: 55667788
|
| 300 |
|
|
# tb_core.u_sdram32 : at time 24877.0 ns BST : Burst Terminate
|
| 301 |
|
|
# tb_core.u_sdram32 : at time 25913.0 ns READ : Bank = 0 Row = 885, Col = 132, Data = 11223344
|
| 302 |
|
|
# tb_core.u_sdram32 : at time 25923.0 ns READ : Bank = 0 Row = 885, Col = 133, Data = 22334455
|
| 303 |
|
|
# READ STATUS: Burst-No: 0 Addr: 01375212 Rxd: 11223344
|
| 304 |
|
|
# tb_core.u_sdram32 : at time 25933.0 ns READ : Bank = 0 Row = 885, Col = 134, Data = 33445566
|
| 305 |
|
|
# tb_core.u_sdram32 : at time 25937.0 ns BST : Burst Terminate
|
| 306 |
|
|
# READ STATUS: Burst-No: 1 Addr: 01375214 Rxd: 22334455
|
| 307 |
|
|
# tb_core.u_sdram32 : at time 25943.0 ns READ : Bank = 0 Row = 885, Col = 135, Data = 44556677
|
| 308 |
|
|
# READ STATUS: Burst-No: 2 Addr: 01375216 Rxd: 33445566
|
| 309 |
|
|
# tb_core.u_sdram32 : at time 25953.0 ns READ : Bank = 0 Row = 885, Col = 136, Data = 55667788
|
| 310 |
|
|
# READ STATUS: Burst-No: 3 Addr: 01375218 Rxd: 44556677
|
| 311 |
|
|
# READ STATUS: Burst-No: 4 Addr: 0137521a Rxd: 55667788
|
| 312 |
|
|
# Write Address: 00f3e301, Burst Size: 5
|
| 313 |
|
|
# tb_core.u_sdram32 : at time 26037.0 ns ACT : Bank = 0 Row = 1854
|
| 314 |
|
|
# tb_core.u_sdram32 : at time 26067.0 ns WRITE: Bank = 0 Row = 1854, Col = 192, Data = 11223344
|
| 315 |
|
|
# Status: Burst-No: 0 Write Address: 00f3e301 WriteData: 11223344
|
| 316 |
|
|
# tb_core.u_sdram32 : at time 26077.0 ns WRITE: Bank = 0 Row = 1854, Col = 193, Data = 22334455
|
| 317 |
|
|
# Status: Burst-No: 1 Write Address: 00f3e301 WriteData: 22334455
|
| 318 |
|
|
# tb_core.u_sdram32 : at time 26087.0 ns WRITE: Bank = 0 Row = 1854, Col = 194, Data = 33445566
|
| 319 |
|
|
# Status: Burst-No: 2 Write Address: 00f3e301 WriteData: 33445566
|
| 320 |
|
|
# tb_core.u_sdram32 : at time 26097.0 ns WRITE: Bank = 0 Row = 1854, Col = 195, Data = 44556677
|
| 321 |
|
|
# Status: Burst-No: 3 Write Address: 00f3e301 WriteData: 44556677
|
| 322 |
|
|
# tb_core.u_sdram32 : at time 26107.0 ns WRITE: Bank = 0 Row = 1854, Col = 196, Data = 55667788
|
| 323 |
|
|
# Status: Burst-No: 4 Write Address: 00f3e301 WriteData: 55667788
|
| 324 |
|
|
# tb_core.u_sdram32 : at time 26117.0 ns BST : Burst Terminate
|
| 325 |
|
|
# tb_core.u_sdram32 : at time 27153.0 ns READ : Bank = 0 Row = 1854, Col = 192, Data = 11223344
|
| 326 |
|
|
# tb_core.u_sdram32 : at time 27163.0 ns READ : Bank = 0 Row = 1854, Col = 193, Data = 22334455
|
| 327 |
|
|
# READ STATUS: Burst-No: 0 Addr: 00f3e301 Rxd: 11223344
|
| 328 |
|
|
# tb_core.u_sdram32 : at time 27173.0 ns READ : Bank = 0 Row = 1854, Col = 194, Data = 33445566
|
| 329 |
|
|
# tb_core.u_sdram32 : at time 27177.0 ns BST : Burst Terminate
|
| 330 |
|
|
# READ STATUS: Burst-No: 1 Addr: 00f3e303 Rxd: 22334455
|
| 331 |
|
|
# tb_core.u_sdram32 : at time 27183.0 ns READ : Bank = 0 Row = 1854, Col = 195, Data = 44556677
|
| 332 |
|
|
# READ STATUS: Burst-No: 2 Addr: 00f3e305 Rxd: 33445566
|
| 333 |
|
|
# tb_core.u_sdram32 : at time 27193.0 ns READ : Bank = 0 Row = 1854, Col = 196, Data = 55667788
|
| 334 |
|
|
# READ STATUS: Burst-No: 3 Addr: 00f3e307 Rxd: 44556677
|
| 335 |
|
|
# READ STATUS: Burst-No: 4 Addr: 00f3e309 Rxd: 55667788
|
| 336 |
|
|
# Write Address: 06d7cd0d, Burst Size: 5
|
| 337 |
|
|
# tb_core.u_sdram32 : at time 27277.0 ns ACT : Bank = 3 Row = 1404
|
| 338 |
|
|
# tb_core.u_sdram32 : at time 27307.0 ns WRITE: Bank = 3 Row = 1404, Col = 67, Data = 11223344
|
| 339 |
|
|
# Status: Burst-No: 0 Write Address: 06d7cd0d WriteData: 11223344
|
| 340 |
|
|
# tb_core.u_sdram32 : at time 27317.0 ns WRITE: Bank = 3 Row = 1404, Col = 68, Data = 22334455
|
| 341 |
|
|
# Status: Burst-No: 1 Write Address: 06d7cd0d WriteData: 22334455
|
| 342 |
|
|
# tb_core.u_sdram32 : at time 27327.0 ns WRITE: Bank = 3 Row = 1404, Col = 69, Data = 33445566
|
| 343 |
|
|
# Status: Burst-No: 2 Write Address: 06d7cd0d WriteData: 33445566
|
| 344 |
|
|
# tb_core.u_sdram32 : at time 27337.0 ns WRITE: Bank = 3 Row = 1404, Col = 70, Data = 44556677
|
| 345 |
|
|
# Status: Burst-No: 3 Write Address: 06d7cd0d WriteData: 44556677
|
| 346 |
|
|
# tb_core.u_sdram32 : at time 27347.0 ns WRITE: Bank = 3 Row = 1404, Col = 71, Data = 55667788
|
| 347 |
|
|
# Status: Burst-No: 4 Write Address: 06d7cd0d WriteData: 55667788
|
| 348 |
|
|
# tb_core.u_sdram32 : at time 27357.0 ns BST : Burst Terminate
|
| 349 |
|
|
# tb_core.u_sdram32 : at time 28393.0 ns READ : Bank = 3 Row = 1404, Col = 67, Data = 11223344
|
| 350 |
|
|
# tb_core.u_sdram32 : at time 28403.0 ns READ : Bank = 3 Row = 1404, Col = 68, Data = 22334455
|
| 351 |
|
|
# READ STATUS: Burst-No: 0 Addr: 06d7cd0d Rxd: 11223344
|
| 352 |
|
|
# tb_core.u_sdram32 : at time 28413.0 ns READ : Bank = 3 Row = 1404, Col = 69, Data = 33445566
|
| 353 |
|
|
# tb_core.u_sdram32 : at time 28417.0 ns BST : Burst Terminate
|
| 354 |
|
|
# READ STATUS: Burst-No: 1 Addr: 06d7cd0f Rxd: 22334455
|
| 355 |
|
|
# tb_core.u_sdram32 : at time 28423.0 ns READ : Bank = 3 Row = 1404, Col = 70, Data = 44556677
|
| 356 |
|
|
# READ STATUS: Burst-No: 2 Addr: 06d7cd11 Rxd: 33445566
|
| 357 |
|
|
# tb_core.u_sdram32 : at time 28433.0 ns READ : Bank = 3 Row = 1404, Col = 71, Data = 55667788
|
| 358 |
|
|
# READ STATUS: Burst-No: 3 Addr: 06d7cd13 Rxd: 44556677
|
| 359 |
|
|
# READ STATUS: Burst-No: 4 Addr: 06d7cd15 Rxd: 55667788
|
| 360 |
|
|
# Write Address: 0323f176, Burst Size: 5
|
| 361 |
|
|
# tb_core.u_sdram32 : at time 28517.0 ns ACT : Bank = 0 Row = 575
|
| 362 |
|
|
# tb_core.u_sdram32 : at time 28547.0 ns WRITE: Bank = 0 Row = 575, Col = 93, Data = 11223344
|
| 363 |
|
|
# Status: Burst-No: 0 Write Address: 0323f176 WriteData: 11223344
|
| 364 |
|
|
# tb_core.u_sdram32 : at time 28557.0 ns WRITE: Bank = 0 Row = 575, Col = 94, Data = 22334455
|
| 365 |
|
|
# Status: Burst-No: 1 Write Address: 0323f176 WriteData: 22334455
|
| 366 |
|
|
# tb_core.u_sdram32 : at time 28567.0 ns WRITE: Bank = 0 Row = 575, Col = 95, Data = 33445566
|
| 367 |
|
|
# Status: Burst-No: 2 Write Address: 0323f176 WriteData: 33445566
|
| 368 |
|
|
# tb_core.u_sdram32 : at time 28577.0 ns WRITE: Bank = 0 Row = 575, Col = 96, Data = 44556677
|
| 369 |
|
|
# Status: Burst-No: 3 Write Address: 0323f176 WriteData: 44556677
|
| 370 |
|
|
# tb_core.u_sdram32 : at time 28587.0 ns WRITE: Bank = 0 Row = 575, Col = 97, Data = 55667788
|
| 371 |
|
|
# Status: Burst-No: 4 Write Address: 0323f176 WriteData: 55667788
|
| 372 |
|
|
# tb_core.u_sdram32 : at time 28597.0 ns BST : Burst Terminate
|
| 373 |
|
|
# tb_core.u_sdram32 : at time 29633.0 ns READ : Bank = 0 Row = 575, Col = 93, Data = 11223344
|
| 374 |
|
|
# tb_core.u_sdram32 : at time 29643.0 ns READ : Bank = 0 Row = 575, Col = 94, Data = 22334455
|
| 375 |
|
|
# READ STATUS: Burst-No: 0 Addr: 0323f176 Rxd: 11223344
|
| 376 |
|
|
# tb_core.u_sdram32 : at time 29653.0 ns READ : Bank = 0 Row = 575, Col = 95, Data = 33445566
|
| 377 |
|
|
# tb_core.u_sdram32 : at time 29657.0 ns BST : Burst Terminate
|
| 378 |
|
|
# READ STATUS: Burst-No: 1 Addr: 0323f178 Rxd: 22334455
|
| 379 |
|
|
# tb_core.u_sdram32 : at time 29663.0 ns READ : Bank = 0 Row = 575, Col = 96, Data = 44556677
|
| 380 |
|
|
# READ STATUS: Burst-No: 2 Addr: 0323f17a Rxd: 33445566
|
| 381 |
|
|
# tb_core.u_sdram32 : at time 29673.0 ns READ : Bank = 0 Row = 575, Col = 97, Data = 55667788
|
| 382 |
|
|
# READ STATUS: Burst-No: 3 Addr: 0323f17c Rxd: 44556677
|
| 383 |
|
|
# READ STATUS: Burst-No: 4 Addr: 0323f17e Rxd: 55667788
|
| 384 |
|
|
# Write Address: 068dcd3d, Burst Size: 5
|
| 385 |
|
|
# tb_core.u_sdram32 : at time 29757.0 ns ACT : Bank = 3 Row = 220
|
| 386 |
|
|
# tb_core.u_sdram32 : at time 29787.0 ns WRITE: Bank = 3 Row = 220, Col = 79, Data = 11223344
|
| 387 |
|
|
# Status: Burst-No: 0 Write Address: 068dcd3d WriteData: 11223344
|
| 388 |
|
|
# tb_core.u_sdram32 : at time 29797.0 ns WRITE: Bank = 3 Row = 220, Col = 80, Data = 22334455
|
| 389 |
|
|
# Status: Burst-No: 1 Write Address: 068dcd3d WriteData: 22334455
|
| 390 |
|
|
# tb_core.u_sdram32 : at time 29807.0 ns WRITE: Bank = 3 Row = 220, Col = 81, Data = 33445566
|
| 391 |
|
|
# Status: Burst-No: 2 Write Address: 068dcd3d WriteData: 33445566
|
| 392 |
|
|
# tb_core.u_sdram32 : at time 29817.0 ns WRITE: Bank = 3 Row = 220, Col = 82, Data = 44556677
|
| 393 |
|
|
# Status: Burst-No: 3 Write Address: 068dcd3d WriteData: 44556677
|
| 394 |
|
|
# tb_core.u_sdram32 : at time 29827.0 ns WRITE: Bank = 3 Row = 220, Col = 83, Data = 55667788
|
| 395 |
|
|
# Status: Burst-No: 4 Write Address: 068dcd3d WriteData: 55667788
|
| 396 |
|
|
# tb_core.u_sdram32 : at time 29837.0 ns BST : Burst Terminate
|
| 397 |
|
|
# tb_core.u_sdram32 : at time 30873.0 ns READ : Bank = 3 Row = 220, Col = 79, Data = 11223344
|
| 398 |
|
|
# tb_core.u_sdram32 : at time 30883.0 ns READ : Bank = 3 Row = 220, Col = 80, Data = 22334455
|
| 399 |
|
|
# READ STATUS: Burst-No: 0 Addr: 068dcd3d Rxd: 11223344
|
| 400 |
|
|
# tb_core.u_sdram32 : at time 30893.0 ns READ : Bank = 3 Row = 220, Col = 81, Data = 33445566
|
| 401 |
|
|
# tb_core.u_sdram32 : at time 30897.0 ns BST : Burst Terminate
|
| 402 |
|
|
# READ STATUS: Burst-No: 1 Addr: 068dcd3f Rxd: 22334455
|
| 403 |
|
|
# tb_core.u_sdram32 : at time 30903.0 ns READ : Bank = 3 Row = 220, Col = 82, Data = 44556677
|
| 404 |
|
|
# READ STATUS: Burst-No: 2 Addr: 068dcd41 Rxd: 33445566
|
| 405 |
|
|
# tb_core.u_sdram32 : at time 30913.0 ns READ : Bank = 3 Row = 220, Col = 83, Data = 55667788
|
| 406 |
|
|
# READ STATUS: Burst-No: 3 Addr: 068dcd43 Rxd: 44556677
|
| 407 |
|
|
# READ STATUS: Burst-No: 4 Addr: 068dcd45 Rxd: 55667788
|
| 408 |
|
|
# Write Address: 06d457ed, Burst Size: 5
|
| 409 |
|
|
# tb_core.u_sdram32 : at time 30997.0 ns ACT : Bank = 1 Row = 1349
|
| 410 |
|
|
# tb_core.u_sdram32 : at time 31027.0 ns WRITE: Bank = 1 Row = 1349, Col = 251, Data = 11223344
|
| 411 |
|
|
# Status: Burst-No: 0 Write Address: 06d457ed WriteData: 11223344
|
| 412 |
|
|
# tb_core.u_sdram32 : at time 31037.0 ns WRITE: Bank = 1 Row = 1349, Col = 252, Data = 22334455
|
| 413 |
|
|
# Status: Burst-No: 1 Write Address: 06d457ed WriteData: 22334455
|
| 414 |
|
|
# tb_core.u_sdram32 : at time 31047.0 ns WRITE: Bank = 1 Row = 1349, Col = 253, Data = 33445566
|
| 415 |
|
|
# Status: Burst-No: 2 Write Address: 06d457ed WriteData: 33445566
|
| 416 |
|
|
# tb_core.u_sdram32 : at time 31057.0 ns WRITE: Bank = 1 Row = 1349, Col = 254, Data = 44556677
|
| 417 |
|
|
# Status: Burst-No: 3 Write Address: 06d457ed WriteData: 44556677
|
| 418 |
|
|
# tb_core.u_sdram32 : at time 31067.0 ns WRITE: Bank = 1 Row = 1349, Col = 255, Data = 55667788
|
| 419 |
|
|
# Status: Burst-No: 4 Write Address: 06d457ed WriteData: 55667788
|
| 420 |
|
|
# tb_core.u_sdram32 : at time 31077.0 ns BST : Burst Terminate
|
| 421 |
|
|
# tb_core.u_sdram32 : at time 32113.0 ns READ : Bank = 1 Row = 1349, Col = 251, Data = 11223344
|
| 422 |
|
|
# tb_core.u_sdram32 : at time 32123.0 ns READ : Bank = 1 Row = 1349, Col = 252, Data = 22334455
|
| 423 |
|
|
# READ STATUS: Burst-No: 0 Addr: 06d457ed Rxd: 11223344
|
| 424 |
|
|
# tb_core.u_sdram32 : at time 32133.0 ns READ : Bank = 1 Row = 1349, Col = 253, Data = 33445566
|
| 425 |
|
|
# tb_core.u_sdram32 : at time 32137.0 ns BST : Burst Terminate
|
| 426 |
|
|
# READ STATUS: Burst-No: 1 Addr: 06d457ef Rxd: 22334455
|
| 427 |
|
|
# tb_core.u_sdram32 : at time 32143.0 ns READ : Bank = 1 Row = 1349, Col = 254, Data = 44556677
|
| 428 |
|
|
# READ STATUS: Burst-No: 2 Addr: 06d457f1 Rxd: 33445566
|
| 429 |
|
|
# tb_core.u_sdram32 : at time 32153.0 ns READ : Bank = 1 Row = 1349, Col = 255, Data = 55667788
|
| 430 |
|
|
# READ STATUS: Burst-No: 3 Addr: 06d457f3 Rxd: 44556677
|
| 431 |
|
|
# READ STATUS: Burst-No: 4 Addr: 06d457f5 Rxd: 55667788
|
| 432 |
|
|
# Write Address: 062df78c, Burst Size: 5
|
| 433 |
|
|
# tb_core.u_sdram32 : at time 32237.0 ns ACT : Bank = 1 Row = 735
|
| 434 |
|
|
# tb_core.u_sdram32 : at time 32267.0 ns WRITE: Bank = 1 Row = 735, Col = 227, Data = 11223344
|
| 435 |
|
|
# Status: Burst-No: 0 Write Address: 062df78c WriteData: 11223344
|
| 436 |
|
|
# tb_core.u_sdram32 : at time 32277.0 ns WRITE: Bank = 1 Row = 735, Col = 228, Data = 22334455
|
| 437 |
|
|
# Status: Burst-No: 1 Write Address: 062df78c WriteData: 22334455
|
| 438 |
|
|
# tb_core.u_sdram32 : at time 32287.0 ns WRITE: Bank = 1 Row = 735, Col = 229, Data = 33445566
|
| 439 |
|
|
# Status: Burst-No: 2 Write Address: 062df78c WriteData: 33445566
|
| 440 |
|
|
# tb_core.u_sdram32 : at time 32297.0 ns WRITE: Bank = 1 Row = 735, Col = 230, Data = 44556677
|
| 441 |
|
|
# Status: Burst-No: 3 Write Address: 062df78c WriteData: 44556677
|
| 442 |
|
|
# tb_core.u_sdram32 : at time 32307.0 ns WRITE: Bank = 1 Row = 735, Col = 231, Data = 55667788
|
| 443 |
|
|
# Status: Burst-No: 4 Write Address: 062df78c WriteData: 55667788
|
| 444 |
|
|
# tb_core.u_sdram32 : at time 32317.0 ns BST : Burst Terminate
|
| 445 |
|
|
# tb_core.u_sdram32 : at time 33353.0 ns READ : Bank = 1 Row = 735, Col = 227, Data = 11223344
|
| 446 |
|
|
# tb_core.u_sdram32 : at time 33363.0 ns READ : Bank = 1 Row = 735, Col = 228, Data = 22334455
|
| 447 |
|
|
# READ STATUS: Burst-No: 0 Addr: 062df78c Rxd: 11223344
|
| 448 |
|
|
# tb_core.u_sdram32 : at time 33373.0 ns READ : Bank = 1 Row = 735, Col = 229, Data = 33445566
|
| 449 |
|
|
# tb_core.u_sdram32 : at time 33377.0 ns BST : Burst Terminate
|
| 450 |
|
|
# READ STATUS: Burst-No: 1 Addr: 062df78e Rxd: 22334455
|
| 451 |
|
|
# tb_core.u_sdram32 : at time 33383.0 ns READ : Bank = 1 Row = 735, Col = 230, Data = 44556677
|
| 452 |
|
|
# READ STATUS: Burst-No: 2 Addr: 062df790 Rxd: 33445566
|
| 453 |
|
|
# tb_core.u_sdram32 : at time 33393.0 ns READ : Bank = 1 Row = 735, Col = 231, Data = 55667788
|
| 454 |
|
|
# READ STATUS: Burst-No: 3 Addr: 062df792 Rxd: 44556677
|
| 455 |
|
|
# READ STATUS: Burst-No: 4 Addr: 062df794 Rxd: 55667788
|
| 456 |
|
|
# Write Address: 04fde9f9, Burst Size: 5
|
| 457 |
|
|
# tb_core.u_sdram32 : at time 33477.0 ns ACT : Bank = 2 Row = 2014
|
| 458 |
|
|
# tb_core.u_sdram32 : at time 33507.0 ns WRITE: Bank = 2 Row = 2014, Col = 126, Data = 11223344
|
| 459 |
|
|
# Status: Burst-No: 0 Write Address: 04fde9f9 WriteData: 11223344
|
| 460 |
|
|
# tb_core.u_sdram32 : at time 33517.0 ns WRITE: Bank = 2 Row = 2014, Col = 127, Data = 22334455
|
| 461 |
|
|
# Status: Burst-No: 1 Write Address: 04fde9f9 WriteData: 22334455
|
| 462 |
|
|
# tb_core.u_sdram32 : at time 33527.0 ns WRITE: Bank = 2 Row = 2014, Col = 128, Data = 33445566
|
| 463 |
|
|
# Status: Burst-No: 2 Write Address: 04fde9f9 WriteData: 33445566
|
| 464 |
|
|
# tb_core.u_sdram32 : at time 33537.0 ns WRITE: Bank = 2 Row = 2014, Col = 129, Data = 44556677
|
| 465 |
|
|
# Status: Burst-No: 3 Write Address: 04fde9f9 WriteData: 44556677
|
| 466 |
|
|
# tb_core.u_sdram32 : at time 33547.0 ns WRITE: Bank = 2 Row = 2014, Col = 130, Data = 55667788
|
| 467 |
|
|
# Status: Burst-No: 4 Write Address: 04fde9f9 WriteData: 55667788
|
| 468 |
|
|
# tb_core.u_sdram32 : at time 33557.0 ns BST : Burst Terminate
|
| 469 |
|
|
# tb_core.u_sdram32 : at time 34593.0 ns READ : Bank = 2 Row = 2014, Col = 126, Data = 11223344
|
| 470 |
|
|
# tb_core.u_sdram32 : at time 34603.0 ns READ : Bank = 2 Row = 2014, Col = 127, Data = 22334455
|
| 471 |
|
|
# READ STATUS: Burst-No: 0 Addr: 04fde9f9 Rxd: 11223344
|
| 472 |
|
|
# tb_core.u_sdram32 : at time 34613.0 ns READ : Bank = 2 Row = 2014, Col = 128, Data = 33445566
|
| 473 |
|
|
# tb_core.u_sdram32 : at time 34617.0 ns BST : Burst Terminate
|
| 474 |
|
|
# READ STATUS: Burst-No: 1 Addr: 04fde9fb Rxd: 22334455
|
| 475 |
|
|
# tb_core.u_sdram32 : at time 34623.0 ns READ : Bank = 2 Row = 2014, Col = 129, Data = 44556677
|
| 476 |
|
|
# READ STATUS: Burst-No: 2 Addr: 04fde9fd Rxd: 33445566
|
| 477 |
|
|
# tb_core.u_sdram32 : at time 34633.0 ns READ : Bank = 2 Row = 2014, Col = 130, Data = 55667788
|
| 478 |
|
|
# READ STATUS: Burst-No: 3 Addr: 04fde9ff Rxd: 44556677
|
| 479 |
|
|
# READ STATUS: Burst-No: 4 Addr: 04fdea01 Rxd: 55667788
|
| 480 |
|
|
# Write Address: 033724c6, Burst Size: 5
|
| 481 |
|
|
# tb_core.u_sdram32 : at time 34717.0 ns ACT : Bank = 1 Row = 882
|
| 482 |
|
|
# tb_core.u_sdram32 : at time 34747.0 ns WRITE: Bank = 1 Row = 882, Col = 49, Data = 11223344
|
| 483 |
|
|
# Status: Burst-No: 0 Write Address: 033724c6 WriteData: 11223344
|
| 484 |
|
|
# tb_core.u_sdram32 : at time 34757.0 ns WRITE: Bank = 1 Row = 882, Col = 50, Data = 22334455
|
| 485 |
|
|
# Status: Burst-No: 1 Write Address: 033724c6 WriteData: 22334455
|
| 486 |
|
|
# tb_core.u_sdram32 : at time 34767.0 ns WRITE: Bank = 1 Row = 882, Col = 51, Data = 33445566
|
| 487 |
|
|
# Status: Burst-No: 2 Write Address: 033724c6 WriteData: 33445566
|
| 488 |
|
|
# tb_core.u_sdram32 : at time 34777.0 ns WRITE: Bank = 1 Row = 882, Col = 52, Data = 44556677
|
| 489 |
|
|
# Status: Burst-No: 3 Write Address: 033724c6 WriteData: 44556677
|
| 490 |
|
|
# tb_core.u_sdram32 : at time 34787.0 ns WRITE: Bank = 1 Row = 882, Col = 53, Data = 55667788
|
| 491 |
|
|
# Status: Burst-No: 4 Write Address: 033724c6 WriteData: 55667788
|
| 492 |
|
|
# tb_core.u_sdram32 : at time 34797.0 ns BST : Burst Terminate
|
| 493 |
|
|
# tb_core.u_sdram32 : at time 35833.0 ns READ : Bank = 1 Row = 882, Col = 49, Data = 11223344
|
| 494 |
|
|
# tb_core.u_sdram32 : at time 35843.0 ns READ : Bank = 1 Row = 882, Col = 50, Data = 22334455
|
| 495 |
|
|
# READ STATUS: Burst-No: 0 Addr: 033724c6 Rxd: 11223344
|
| 496 |
|
|
# tb_core.u_sdram32 : at time 35853.0 ns READ : Bank = 1 Row = 882, Col = 51, Data = 33445566
|
| 497 |
|
|
# tb_core.u_sdram32 : at time 35857.0 ns BST : Burst Terminate
|
| 498 |
|
|
# READ STATUS: Burst-No: 1 Addr: 033724c8 Rxd: 22334455
|
| 499 |
|
|
# tb_core.u_sdram32 : at time 35863.0 ns READ : Bank = 1 Row = 882, Col = 52, Data = 44556677
|
| 500 |
|
|
# READ STATUS: Burst-No: 2 Addr: 033724ca Rxd: 33445566
|
| 501 |
|
|
# tb_core.u_sdram32 : at time 35873.0 ns READ : Bank = 1 Row = 882, Col = 53, Data = 55667788
|
| 502 |
|
|
# READ STATUS: Burst-No: 3 Addr: 033724cc Rxd: 44556677
|
| 503 |
|
|
# READ STATUS: Burst-No: 4 Addr: 033724ce Rxd: 55667788
|
| 504 |
|
|
# Write Address: 02f784c5, Burst Size: 5
|
| 505 |
|
|
# tb_core.u_sdram32 : at time 35957.0 ns ACT : Bank = 1 Row = 1912
|
| 506 |
|
|
# tb_core.u_sdram32 : at time 35987.0 ns WRITE: Bank = 1 Row = 1912, Col = 49, Data = 11223344
|
| 507 |
|
|
# Status: Burst-No: 0 Write Address: 02f784c5 WriteData: 11223344
|
| 508 |
|
|
# tb_core.u_sdram32 : at time 35997.0 ns WRITE: Bank = 1 Row = 1912, Col = 50, Data = 22334455
|
| 509 |
|
|
# Status: Burst-No: 1 Write Address: 02f784c5 WriteData: 22334455
|
| 510 |
|
|
# tb_core.u_sdram32 : at time 36007.0 ns WRITE: Bank = 1 Row = 1912, Col = 51, Data = 33445566
|
| 511 |
|
|
# Status: Burst-No: 2 Write Address: 02f784c5 WriteData: 33445566
|
| 512 |
|
|
# tb_core.u_sdram32 : at time 36017.0 ns WRITE: Bank = 1 Row = 1912, Col = 52, Data = 44556677
|
| 513 |
|
|
# Status: Burst-No: 3 Write Address: 02f784c5 WriteData: 44556677
|
| 514 |
|
|
# tb_core.u_sdram32 : at time 36027.0 ns WRITE: Bank = 1 Row = 1912, Col = 53, Data = 55667788
|
| 515 |
|
|
# Status: Burst-No: 4 Write Address: 02f784c5 WriteData: 55667788
|
| 516 |
|
|
# tb_core.u_sdram32 : at time 36037.0 ns BST : Burst Terminate
|
| 517 |
|
|
# tb_core.u_sdram32 : at time 37073.0 ns READ : Bank = 1 Row = 1912, Col = 49, Data = 11223344
|
| 518 |
|
|
# tb_core.u_sdram32 : at time 37083.0 ns READ : Bank = 1 Row = 1912, Col = 50, Data = 22334455
|
| 519 |
|
|
# READ STATUS: Burst-No: 0 Addr: 02f784c5 Rxd: 11223344
|
| 520 |
|
|
# tb_core.u_sdram32 : at time 37093.0 ns READ : Bank = 1 Row = 1912, Col = 51, Data = 33445566
|
| 521 |
|
|
# tb_core.u_sdram32 : at time 37097.0 ns BST : Burst Terminate
|
| 522 |
|
|
# READ STATUS: Burst-No: 1 Addr: 02f784c7 Rxd: 22334455
|
| 523 |
|
|
# tb_core.u_sdram32 : at time 37103.0 ns READ : Bank = 1 Row = 1912, Col = 52, Data = 44556677
|
| 524 |
|
|
# READ STATUS: Burst-No: 2 Addr: 02f784c9 Rxd: 33445566
|
| 525 |
|
|
# tb_core.u_sdram32 : at time 37113.0 ns READ : Bank = 1 Row = 1912, Col = 53, Data = 55667788
|
| 526 |
|
|
# READ STATUS: Burst-No: 3 Addr: 02f784cb Rxd: 44556677
|
| 527 |
|
|
# READ STATUS: Burst-No: 4 Addr: 02f784cd Rxd: 55667788
|
| 528 |
|
|
# Write Address: 0513d2aa, Burst Size: 5
|
| 529 |
|
|
# tb_core.u_sdram32 : at time 37197.0 ns ACT : Bank = 0 Row = 317
|
| 530 |
|
|
# tb_core.u_sdram32 : at time 37227.0 ns WRITE: Bank = 0 Row = 317, Col = 170, Data = 11223344
|
| 531 |
|
|
# Status: Burst-No: 0 Write Address: 0513d2aa WriteData: 11223344
|
| 532 |
|
|
# tb_core.u_sdram32 : at time 37237.0 ns WRITE: Bank = 0 Row = 317, Col = 171, Data = 22334455
|
| 533 |
|
|
# Status: Burst-No: 1 Write Address: 0513d2aa WriteData: 22334455
|
| 534 |
|
|
# tb_core.u_sdram32 : at time 37247.0 ns WRITE: Bank = 0 Row = 317, Col = 172, Data = 33445566
|
| 535 |
|
|
# Status: Burst-No: 2 Write Address: 0513d2aa WriteData: 33445566
|
| 536 |
|
|
# tb_core.u_sdram32 : at time 37257.0 ns WRITE: Bank = 0 Row = 317, Col = 173, Data = 44556677
|
| 537 |
|
|
# Status: Burst-No: 3 Write Address: 0513d2aa WriteData: 44556677
|
| 538 |
|
|
# tb_core.u_sdram32 : at time 37267.0 ns WRITE: Bank = 0 Row = 317, Col = 174, Data = 55667788
|
| 539 |
|
|
# Status: Burst-No: 4 Write Address: 0513d2aa WriteData: 55667788
|
| 540 |
|
|
# tb_core.u_sdram32 : at time 37277.0 ns BST : Burst Terminate
|
| 541 |
|
|
# tb_core.u_sdram32 : at time 38313.0 ns READ : Bank = 0 Row = 317, Col = 170, Data = 11223344
|
| 542 |
|
|
# tb_core.u_sdram32 : at time 38323.0 ns READ : Bank = 0 Row = 317, Col = 171, Data = 22334455
|
| 543 |
|
|
# READ STATUS: Burst-No: 0 Addr: 0513d2aa Rxd: 11223344
|
| 544 |
|
|
# tb_core.u_sdram32 : at time 38333.0 ns READ : Bank = 0 Row = 317, Col = 172, Data = 33445566
|
| 545 |
|
|
# tb_core.u_sdram32 : at time 38337.0 ns BST : Burst Terminate
|
| 546 |
|
|
# READ STATUS: Burst-No: 1 Addr: 0513d2ac Rxd: 22334455
|
| 547 |
|
|
# tb_core.u_sdram32 : at time 38343.0 ns READ : Bank = 0 Row = 317, Col = 173, Data = 44556677
|
| 548 |
|
|
# READ STATUS: Burst-No: 2 Addr: 0513d2ae Rxd: 33445566
|
| 549 |
|
|
# tb_core.u_sdram32 : at time 38353.0 ns READ : Bank = 0 Row = 317, Col = 174, Data = 55667788
|
| 550 |
|
|
# READ STATUS: Burst-No: 3 Addr: 0513d2b0 Rxd: 44556677
|
| 551 |
|
|
# READ STATUS: Burst-No: 4 Addr: 0513d2b2 Rxd: 55667788
|
| 552 |
|
|
# Write Address: 02aff7e5, Burst Size: 5
|
| 553 |
|
|
# tb_core.u_sdram32 : at time 38437.0 ns ACT : Bank = 1 Row = 767
|
| 554 |
|
|
# tb_core.u_sdram32 : at time 38467.0 ns WRITE: Bank = 1 Row = 767, Col = 249, Data = 11223344
|
| 555 |
|
|
# Status: Burst-No: 0 Write Address: 02aff7e5 WriteData: 11223344
|
| 556 |
|
|
# tb_core.u_sdram32 : at time 38477.0 ns WRITE: Bank = 1 Row = 767, Col = 250, Data = 22334455
|
| 557 |
|
|
# Status: Burst-No: 1 Write Address: 02aff7e5 WriteData: 22334455
|
| 558 |
|
|
# tb_core.u_sdram32 : at time 38487.0 ns WRITE: Bank = 1 Row = 767, Col = 251, Data = 33445566
|
| 559 |
|
|
# Status: Burst-No: 2 Write Address: 02aff7e5 WriteData: 33445566
|
| 560 |
|
|
# tb_core.u_sdram32 : at time 38497.0 ns WRITE: Bank = 1 Row = 767, Col = 252, Data = 44556677
|
| 561 |
|
|
# Status: Burst-No: 3 Write Address: 02aff7e5 WriteData: 44556677
|
| 562 |
|
|
# tb_core.u_sdram32 : at time 38507.0 ns WRITE: Bank = 1 Row = 767, Col = 253, Data = 55667788
|
| 563 |
|
|
# Status: Burst-No: 4 Write Address: 02aff7e5 WriteData: 55667788
|
| 564 |
|
|
# tb_core.u_sdram32 : at time 38517.0 ns BST : Burst Terminate
|
| 565 |
|
|
# tb_core.u_sdram32 : at time 39553.0 ns READ : Bank = 1 Row = 767, Col = 249, Data = 11223344
|
| 566 |
|
|
# tb_core.u_sdram32 : at time 39563.0 ns READ : Bank = 1 Row = 767, Col = 250, Data = 22334455
|
| 567 |
|
|
# READ STATUS: Burst-No: 0 Addr: 02aff7e5 Rxd: 11223344
|
| 568 |
|
|
# tb_core.u_sdram32 : at time 39573.0 ns READ : Bank = 1 Row = 767, Col = 251, Data = 33445566
|
| 569 |
|
|
# tb_core.u_sdram32 : at time 39577.0 ns BST : Burst Terminate
|
| 570 |
|
|
# READ STATUS: Burst-No: 1 Addr: 02aff7e7 Rxd: 22334455
|
| 571 |
|
|
# tb_core.u_sdram32 : at time 39583.0 ns READ : Bank = 1 Row = 767, Col = 252, Data = 44556677
|
| 572 |
|
|
# READ STATUS: Burst-No: 2 Addr: 02aff7e9 Rxd: 33445566
|
| 573 |
|
|
# tb_core.u_sdram32 : at time 39593.0 ns READ : Bank = 1 Row = 767, Col = 253, Data = 55667788
|
| 574 |
|
|
# READ STATUS: Burst-No: 3 Addr: 02aff7eb Rxd: 44556677
|
| 575 |
|
|
# READ STATUS: Burst-No: 4 Addr: 02aff7ed Rxd: 55667788
|
| 576 |
|
|
# Write Address: 03d27277, Burst Size: 5
|
| 577 |
|
|
# tb_core.u_sdram32 : at time 39677.0 ns ACT : Bank = 0 Row = 1319
|
| 578 |
|
|
# tb_core.u_sdram32 : at time 39707.0 ns WRITE: Bank = 0 Row = 1319, Col = 157, Data = 11223344
|
| 579 |
|
|
# Status: Burst-No: 0 Write Address: 03d27277 WriteData: 11223344
|
| 580 |
|
|
# tb_core.u_sdram32 : at time 39717.0 ns WRITE: Bank = 0 Row = 1319, Col = 158, Data = 22334455
|
| 581 |
|
|
# Status: Burst-No: 1 Write Address: 03d27277 WriteData: 22334455
|
| 582 |
|
|
# tb_core.u_sdram32 : at time 39727.0 ns WRITE: Bank = 0 Row = 1319, Col = 159, Data = 33445566
|
| 583 |
|
|
# Status: Burst-No: 2 Write Address: 03d27277 WriteData: 33445566
|
| 584 |
|
|
# tb_core.u_sdram32 : at time 39737.0 ns WRITE: Bank = 0 Row = 1319, Col = 160, Data = 44556677
|
| 585 |
|
|
# Status: Burst-No: 3 Write Address: 03d27277 WriteData: 44556677
|
| 586 |
|
|
# tb_core.u_sdram32 : at time 39747.0 ns WRITE: Bank = 0 Row = 1319, Col = 161, Data = 55667788
|
| 587 |
|
|
# Status: Burst-No: 4 Write Address: 03d27277 WriteData: 55667788
|
| 588 |
|
|
# tb_core.u_sdram32 : at time 39757.0 ns BST : Burst Terminate
|
| 589 |
|
|
# tb_core.u_sdram32 : at time 40793.0 ns READ : Bank = 0 Row = 1319, Col = 157, Data = 11223344
|
| 590 |
|
|
# tb_core.u_sdram32 : at time 40803.0 ns READ : Bank = 0 Row = 1319, Col = 158, Data = 22334455
|
| 591 |
|
|
# READ STATUS: Burst-No: 0 Addr: 03d27277 Rxd: 11223344
|
| 592 |
|
|
# tb_core.u_sdram32 : at time 40813.0 ns READ : Bank = 0 Row = 1319, Col = 159, Data = 33445566
|
| 593 |
|
|
# tb_core.u_sdram32 : at time 40817.0 ns BST : Burst Terminate
|
| 594 |
|
|
# READ STATUS: Burst-No: 1 Addr: 03d27279 Rxd: 22334455
|
| 595 |
|
|
# tb_core.u_sdram32 : at time 40823.0 ns READ : Bank = 0 Row = 1319, Col = 160, Data = 44556677
|
| 596 |
|
|
# READ STATUS: Burst-No: 2 Addr: 03d2727b Rxd: 33445566
|
| 597 |
|
|
# tb_core.u_sdram32 : at time 40833.0 ns READ : Bank = 0 Row = 1319, Col = 161, Data = 55667788
|
| 598 |
|
|
# READ STATUS: Burst-No: 3 Addr: 03d2727d Rxd: 44556677
|
| 599 |
|
|
# READ STATUS: Burst-No: 4 Addr: 03d2727f Rxd: 55667788
|
| 600 |
|
|
###############################
|
| 601 |
|
|
# STATUS: SDRAM Write/Read TEST PASSED
|
| 602 |
|
|
###############################
|
| 603 |
28 |
dinesha |
# ** Note: $finish : ../tb/tb_core.sv(300)
|
| 604 |
27 |
dinesha |
# Time: 50860 ns Iteration: 0 Instance: /tb_core
|
| 605 |
|
|
### test 1: basic_test1 --> PASSED
|
| 606 |
|
|
###########################################
|
| 607 |
|
|
|
| 608 |
|
|
###########################################
|
| 609 |
|
|
### Test Logs
|
| 610 |
|
|
test 1: ../log/core_SDR_32BIT_basic_test1.log
|
| 611 |
|
|
###########################################
|
| 612 |
|
|
|
| 613 |
|
|
###########################################
|
| 614 |
|
|
### Test Summary
|
| 615 |
|
|
###
|
| 616 |
|
|
### Failed 0 of 1 SDR_32BIT tests
|
| 617 |
|
|
###########################################
|
