| 1 |
27 |
dinesha |
Compiling with MODELSIM in core SDR_32BIT Mode
|
| 2 |
|
|
Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010
|
| 3 |
|
|
-- Compiling module tb_core
|
| 4 |
|
|
-- Compiling module IS42VM16400K
|
| 5 |
|
|
-- Compiling module mt48lc2m32b2
|
| 6 |
|
|
-- Compiling module mt48lc8m8a2
|
| 7 |
|
|
-- Compiling module sdrc_core
|
| 8 |
|
|
-- Compiling module sdrc_bank_ctl
|
| 9 |
|
|
-- Compiling module sdrc_bank_fsm
|
| 10 |
|
|
-- Compiling module sdrc_bs_convert
|
| 11 |
|
|
-- Compiling module sdrc_req_gen
|
| 12 |
|
|
-- Compiling module sdrc_xfr_ctl
|
| 13 |
|
|
|
| 14 |
|
|
Top level modules:
|
| 15 |
|
|
tb_core
|
| 16 |
|
|
IS42VM16400K
|
| 17 |
|
|
mt48lc8m8a2
|
| 18 |
|
|
#### Compile : PASSED
|
| 19 |
|
|
|
| 20 |
|
|
###########################################
|
| 21 |
43 |
dinesha |
Runing test programs
|
| 22 |
27 |
dinesha |
###########################################
|
| 23 |
|
|
###########################################
|
| 24 |
|
|
### Running test 1: basic_test1
|
| 25 |
|
|
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
|
| 26 |
|
|
|
| 27 |
|
|
# 6.6d
|
| 28 |
|
|
|
| 29 |
|
|
# vsim +basic_test1 -do run.do -c tb_core
|
| 30 |
|
|
# // ModelSim ACTEL 6.6d Nov 2 2010
|
| 31 |
|
|
# //
|
| 32 |
|
|
# // Copyright 1991-2010 Mentor Graphics Corporation
|
| 33 |
|
|
# // All Rights Reserved.
|
| 34 |
|
|
# //
|
| 35 |
|
|
# // THIS WORK CONTAINS TRADE SECRET AND
|
| 36 |
|
|
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
|
| 37 |
|
|
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
|
| 38 |
|
|
# // AND IS SUBJECT TO LICENSE TERMS.
|
| 39 |
|
|
# //
|
| 40 |
|
|
# Loading sv_std.std
|
| 41 |
|
|
# Loading work.tb_core
|
| 42 |
|
|
# Loading work.sdrc_core
|
| 43 |
|
|
# Loading work.sdrc_req_gen
|
| 44 |
|
|
# Loading work.sdrc_bank_ctl
|
| 45 |
|
|
# Loading work.sdrc_bank_fsm
|
| 46 |
|
|
# Loading work.sdrc_xfr_ctl
|
| 47 |
|
|
# Loading work.sdrc_bs_convert
|
| 48 |
|
|
# Loading work.mt48lc2m32b2
|
| 49 |
48 |
dinesha |
# ** Warning: (vsim-3015) ../tb/tb_core.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
|
| 50 |
27 |
dinesha |
# Region: /tb_core/u_sdram32
|
| 51 |
|
|
# do run.do
|
| 52 |
|
|
# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
|
| 53 |
|
|
# tb_core.u_sdram32 : at time 10247.0 ns AREF : Auto Refresh
|
| 54 |
|
|
# tb_core.u_sdram32 : at time 10337.0 ns AREF : Auto Refresh
|
| 55 |
|
|
# tb_core.u_sdram32 : at time 10427.0 ns AREF : Auto Refresh
|
| 56 |
|
|
# tb_core.u_sdram32 : at time 10517.0 ns AREF : Auto Refresh
|
| 57 |
|
|
# tb_core.u_sdram32 : at time 10607.0 ns AREF : Auto Refresh
|
| 58 |
|
|
# tb_core.u_sdram32 : at time 10697.0 ns AREF : Auto Refresh
|
| 59 |
|
|
# tb_core.u_sdram32 : at time 10787.0 ns AREF : Auto Refresh
|
| 60 |
|
|
# tb_core.u_sdram32 : at time 10877.0 ns AREF : Auto Refresh
|
| 61 |
|
|
# tb_core.u_sdram32 : at time 10967.0 ns AREF : Auto Refresh
|
| 62 |
|
|
# tb_core.u_sdram32 : at time 11057.0 ns AREF : Auto Refresh
|
| 63 |
|
|
# tb_core.u_sdram32 : at time 11147.0 ns AREF : Auto Refresh
|
| 64 |
|
|
# tb_core.u_sdram32 : at time 11237.0 ns AREF : Auto Refresh
|
| 65 |
|
|
# tb_core.u_sdram32 : at time 11327.0 ns AREF : Auto Refresh
|
| 66 |
|
|
# tb_core.u_sdram32 : at time 11417.0 ns AREF : Auto Refresh
|
| 67 |
|
|
# tb_core.u_sdram32 : at time 11507.0 ns LMR : Load Mode Register
|
| 68 |
|
|
# tb_core.u_sdram32 : CAS Latency = 3
|
| 69 |
|
|
# tb_core.u_sdram32 : Burst Length = 8
|
| 70 |
|
|
# tb_core.u_sdram32 : Burst Type = Sequential
|
| 71 |
|
|
# tb_core.u_sdram32 : Write Burst Mode = Programmed Burst Length
|
| 72 |
46 |
dinesha |
# ----------------------------------------
|
| 73 |
|
|
# Case-3 Create a Page Cross Over
|
| 74 |
|
|
# ----------------------------------------
|
| 75 |
|
|
# Write Address: 00040ffc, Burst Size: 8
|
| 76 |
48 |
dinesha |
# tb_core.u_sdram32 : at time 12647.0 ns ACT : Bank = 3 Row = 64
|
| 77 |
|
|
# tb_core.u_sdram32 : at time 12677.0 ns WRITE: Bank = 3 Row = 64, Col = 255, Data = 12153524
|
| 78 |
|
|
# Status: Burst-No: 0 Write Address: 00040ffc WriteData: 12153524
|
| 79 |
|
|
# tb_core.u_sdram32 : at time 12687.0 ns BST : Burst Terminate
|
| 80 |
|
|
# tb_core.u_sdram32 : at time 12697.0 ns ACT : Bank = 0 Row = 65
|
| 81 |
|
|
# tb_core.u_sdram32 : at time 12727.0 ns WRITE: Bank = 0 Row = 65, Col = 0, Data = c0895e81
|
| 82 |
|
|
# Status: Burst-No: 1 Write Address: 00040ffc WriteData: c0895e81
|
| 83 |
|
|
# tb_core.u_sdram32 : at time 12737.0 ns WRITE: Bank = 0 Row = 65, Col = 1, Data = 8484d609
|
| 84 |
|
|
# Status: Burst-No: 2 Write Address: 00040ffc WriteData: 8484d609
|
| 85 |
|
|
# tb_core.u_sdram32 : at time 12747.0 ns WRITE: Bank = 0 Row = 65, Col = 2, Data = b1f05663
|
| 86 |
|
|
# Status: Burst-No: 3 Write Address: 00040ffc WriteData: b1f05663
|
| 87 |
|
|
# tb_core.u_sdram32 : at time 12757.0 ns WRITE: Bank = 0 Row = 65, Col = 3, Data = 06b97b0d
|
| 88 |
|
|
# Status: Burst-No: 4 Write Address: 00040ffc WriteData: 06b97b0d
|
| 89 |
|
|
# tb_core.u_sdram32 : at time 12767.0 ns WRITE: Bank = 0 Row = 65, Col = 4, Data = 46df998d
|
| 90 |
|
|
# Status: Burst-No: 5 Write Address: 00040ffc WriteData: 46df998d
|
| 91 |
|
|
# tb_core.u_sdram32 : at time 12777.0 ns WRITE: Bank = 0 Row = 65, Col = 5, Data = b2c28465
|
| 92 |
|
|
# Status: Burst-No: 6 Write Address: 00040ffc WriteData: b2c28465
|
| 93 |
|
|
# tb_core.u_sdram32 : at time 12787.0 ns WRITE: Bank = 0 Row = 65, Col = 6, Data = 89375212
|
| 94 |
|
|
# Status: Burst-No: 7 Write Address: 00040ffc WriteData: 89375212
|
| 95 |
|
|
# tb_core.u_sdram32 : at time 12797.0 ns BST : Burst Terminate
|
| 96 |
46 |
dinesha |
# Write Address: 00400ff8, Burst Size: 15
|
| 97 |
48 |
dinesha |
# tb_core.u_sdram32 : at time 12847.0 ns ACT : Bank = 3 Row = 1024
|
| 98 |
|
|
# tb_core.u_sdram32 : at time 12877.0 ns WRITE: Bank = 3 Row = 1024, Col = 254, Data = 00f3e301
|
| 99 |
|
|
# Status: Burst-No: 0 Write Address: 00400ff8 WriteData: 00f3e301
|
| 100 |
|
|
# tb_core.u_sdram32 : at time 12887.0 ns ACT : Bank = 0 Row = 1025
|
| 101 |
|
|
# tb_core.u_sdram32 : at time 12887.0 ns WRITE: Bank = 3 Row = 1024, Col = 255, Data = 06d7cd0d
|
| 102 |
|
|
# Status: Burst-No: 1 Write Address: 00400ff8 WriteData: 06d7cd0d
|
| 103 |
|
|
# tb_core.u_sdram32 : at time 12897.0 ns BST : Burst Terminate
|
| 104 |
|
|
# tb_core.u_sdram32 : at time 12917.0 ns WRITE: Bank = 0 Row = 1025, Col = 0, Data = 3b23f176
|
| 105 |
|
|
# Status: Burst-No: 2 Write Address: 00400ff8 WriteData: 3b23f176
|
| 106 |
|
|
# tb_core.u_sdram32 : at time 12927.0 ns WRITE: Bank = 0 Row = 1025, Col = 1, Data = 1e8dcd3d
|
| 107 |
|
|
# Status: Burst-No: 3 Write Address: 00400ff8 WriteData: 1e8dcd3d
|
| 108 |
|
|
# tb_core.u_sdram32 : at time 12937.0 ns WRITE: Bank = 0 Row = 1025, Col = 2, Data = 76d457ed
|
| 109 |
|
|
# Status: Burst-No: 4 Write Address: 00400ff8 WriteData: 76d457ed
|
| 110 |
|
|
# tb_core.u_sdram32 : at time 12947.0 ns WRITE: Bank = 0 Row = 1025, Col = 3, Data = 462df78c
|
| 111 |
|
|
# Status: Burst-No: 5 Write Address: 00400ff8 WriteData: 462df78c
|
| 112 |
|
|
# tb_core.u_sdram32 : at time 12957.0 ns WRITE: Bank = 0 Row = 1025, Col = 4, Data = 7cfde9f9
|
| 113 |
|
|
# Status: Burst-No: 6 Write Address: 00400ff8 WriteData: 7cfde9f9
|
| 114 |
|
|
# tb_core.u_sdram32 : at time 12967.0 ns WRITE: Bank = 0 Row = 1025, Col = 5, Data = e33724c6
|
| 115 |
|
|
# Status: Burst-No: 7 Write Address: 00400ff8 WriteData: e33724c6
|
| 116 |
|
|
# tb_core.u_sdram32 : at time 12977.0 ns WRITE: Bank = 0 Row = 1025, Col = 6, Data = e2f784c5
|
| 117 |
|
|
# Status: Burst-No: 8 Write Address: 00400ff8 WriteData: e2f784c5
|
| 118 |
|
|
# tb_core.u_sdram32 : at time 12987.0 ns WRITE: Bank = 0 Row = 1025, Col = 7, Data = d513d2aa
|
| 119 |
|
|
# Status: Burst-No: 9 Write Address: 00400ff8 WriteData: d513d2aa
|
| 120 |
|
|
# tb_core.u_sdram32 : at time 12997.0 ns WRITE: Bank = 0 Row = 1025, Col = 8, Data = 72aff7e5
|
| 121 |
|
|
# Status: Burst-No: 10 Write Address: 00400ff8 WriteData: 72aff7e5
|
| 122 |
|
|
# tb_core.u_sdram32 : at time 13007.0 ns WRITE: Bank = 0 Row = 1025, Col = 9, Data = bbd27277
|
| 123 |
|
|
# Status: Burst-No: 11 Write Address: 00400ff8 WriteData: bbd27277
|
| 124 |
|
|
# tb_core.u_sdram32 : at time 13017.0 ns WRITE: Bank = 0 Row = 1025, Col = 10, Data = 8932d612
|
| 125 |
|
|
# Status: Burst-No: 12 Write Address: 00400ff8 WriteData: 8932d612
|
| 126 |
|
|
# tb_core.u_sdram32 : at time 13027.0 ns WRITE: Bank = 0 Row = 1025, Col = 11, Data = 47ecdb8f
|
| 127 |
|
|
# Status: Burst-No: 13 Write Address: 00400ff8 WriteData: 47ecdb8f
|
| 128 |
|
|
# tb_core.u_sdram32 : at time 13037.0 ns WRITE: Bank = 0 Row = 1025, Col = 12, Data = 793069f2
|
| 129 |
|
|
# Status: Burst-No: 14 Write Address: 00400ff8 WriteData: 793069f2
|
| 130 |
|
|
# tb_core.u_sdram32 : at time 13047.0 ns BST : Burst Terminate
|
| 131 |
|
|
# tb_core.u_sdram32 : at time 13087.0 ns ACT : Bank = 3 Row = 64
|
| 132 |
|
|
# tb_core.u_sdram32 : at time 13127.0 ns BST : Burst Terminate
|
| 133 |
|
|
# tb_core.u_sdram32 : at time 13137.0 ns ACT : Bank = 0 Row = 65
|
| 134 |
|
|
# tb_core.u_sdram32 : at time 13143.0 ns READ : Bank = 3 Row = 64, Col = 255, Data = 12153524
|
| 135 |
|
|
# READ STATUS: Burst-No: 0 Addr: 00040ffc Rxd: 12153524
|
| 136 |
|
|
# tb_core.u_sdram32 : at time 13193.0 ns READ : Bank = 0 Row = 65, Col = 0, Data = c0895e81
|
| 137 |
|
|
# tb_core.u_sdram32 : at time 13203.0 ns READ : Bank = 0 Row = 65, Col = 1, Data = 8484d609
|
| 138 |
|
|
# READ STATUS: Burst-No: 1 Addr: 00040ffe Rxd: c0895e81
|
| 139 |
|
|
# tb_core.u_sdram32 : at time 13213.0 ns READ : Bank = 0 Row = 65, Col = 2, Data = b1f05663
|
| 140 |
|
|
# READ STATUS: Burst-No: 2 Addr: 00041000 Rxd: 8484d609
|
| 141 |
|
|
# tb_core.u_sdram32 : at time 13223.0 ns READ : Bank = 0 Row = 65, Col = 3, Data = 06b97b0d
|
| 142 |
|
|
# READ STATUS: Burst-No: 3 Addr: 00041002 Rxd: b1f05663
|
| 143 |
|
|
# tb_core.u_sdram32 : at time 13233.0 ns READ : Bank = 0 Row = 65, Col = 4, Data = 46df998d
|
| 144 |
|
|
# tb_core.u_sdram32 : at time 13237.0 ns BST : Burst Terminate
|
| 145 |
|
|
# READ STATUS: Burst-No: 4 Addr: 00041004 Rxd: 06b97b0d
|
| 146 |
|
|
# tb_core.u_sdram32 : at time 13243.0 ns READ : Bank = 0 Row = 65, Col = 5, Data = b2c28465
|
| 147 |
|
|
# READ STATUS: Burst-No: 5 Addr: 00041006 Rxd: 46df998d
|
| 148 |
|
|
# tb_core.u_sdram32 : at time 13253.0 ns READ : Bank = 0 Row = 65, Col = 6, Data = 89375212
|
| 149 |
|
|
# READ STATUS: Burst-No: 6 Addr: 00041008 Rxd: b2c28465
|
| 150 |
|
|
# READ STATUS: Burst-No: 7 Addr: 0004100a Rxd: 89375212
|
| 151 |
|
|
# tb_core.u_sdram32 : at time 13327.0 ns ACT : Bank = 3 Row = 1024
|
| 152 |
|
|
# tb_core.u_sdram32 : at time 13367.0 ns ACT : Bank = 0 Row = 1025
|
| 153 |
|
|
# tb_core.u_sdram32 : at time 13377.0 ns BST : Burst Terminate
|
| 154 |
|
|
# tb_core.u_sdram32 : at time 13383.0 ns READ : Bank = 3 Row = 1024, Col = 254, Data = 00f3e301
|
| 155 |
|
|
# tb_core.u_sdram32 : at time 13393.0 ns READ : Bank = 3 Row = 1024, Col = 255, Data = 06d7cd0d
|
| 156 |
|
|
# READ STATUS: Burst-No: 0 Addr: 00400ff8 Rxd: 00f3e301
|
| 157 |
|
|
# READ STATUS: Burst-No: 1 Addr: 00400ffa Rxd: 06d7cd0d
|
| 158 |
|
|
# tb_core.u_sdram32 : at time 13423.0 ns READ : Bank = 0 Row = 1025, Col = 0, Data = 3b23f176
|
| 159 |
|
|
# tb_core.u_sdram32 : at time 13433.0 ns READ : Bank = 0 Row = 1025, Col = 1, Data = 1e8dcd3d
|
| 160 |
|
|
# READ STATUS: Burst-No: 2 Addr: 00400ffc Rxd: 3b23f176
|
| 161 |
|
|
# tb_core.u_sdram32 : at time 13443.0 ns READ : Bank = 0 Row = 1025, Col = 2, Data = 76d457ed
|
| 162 |
|
|
# READ STATUS: Burst-No: 3 Addr: 00400ffe Rxd: 1e8dcd3d
|
| 163 |
|
|
# tb_core.u_sdram32 : at time 13453.0 ns READ : Bank = 0 Row = 1025, Col = 3, Data = 462df78c
|
| 164 |
|
|
# READ STATUS: Burst-No: 4 Addr: 00401000 Rxd: 76d457ed
|
| 165 |
|
|
# tb_core.u_sdram32 : at time 13463.0 ns READ : Bank = 0 Row = 1025, Col = 4, Data = 7cfde9f9
|
| 166 |
|
|
# READ STATUS: Burst-No: 5 Addr: 00401002 Rxd: 462df78c
|
| 167 |
|
|
# tb_core.u_sdram32 : at time 13473.0 ns READ : Bank = 0 Row = 1025, Col = 5, Data = e33724c6
|
| 168 |
|
|
# READ STATUS: Burst-No: 6 Addr: 00401004 Rxd: 7cfde9f9
|
| 169 |
|
|
# tb_core.u_sdram32 : at time 13483.0 ns READ : Bank = 0 Row = 1025, Col = 6, Data = e2f784c5
|
| 170 |
|
|
# READ STATUS: Burst-No: 7 Addr: 00401006 Rxd: e33724c6
|
| 171 |
|
|
# tb_core.u_sdram32 : at time 13493.0 ns READ : Bank = 0 Row = 1025, Col = 7, Data = d513d2aa
|
| 172 |
|
|
# READ STATUS: Burst-No: 8 Addr: 00401008 Rxd: e2f784c5
|
| 173 |
|
|
# tb_core.u_sdram32 : at time 13503.0 ns READ : Bank = 0 Row = 1025, Col = 8, Data = 72aff7e5
|
| 174 |
|
|
# READ STATUS: Burst-No: 9 Addr: 0040100a Rxd: d513d2aa
|
| 175 |
|
|
# tb_core.u_sdram32 : at time 13513.0 ns READ : Bank = 0 Row = 1025, Col = 9, Data = bbd27277
|
| 176 |
|
|
# READ STATUS: Burst-No: 10 Addr: 0040100c Rxd: 72aff7e5
|
| 177 |
|
|
# tb_core.u_sdram32 : at time 13523.0 ns READ : Bank = 0 Row = 1025, Col = 10, Data = 8932d612
|
| 178 |
|
|
# tb_core.u_sdram32 : at time 13527.0 ns BST : Burst Terminate
|
| 179 |
|
|
# READ STATUS: Burst-No: 11 Addr: 0040100e Rxd: bbd27277
|
| 180 |
|
|
# tb_core.u_sdram32 : at time 13533.0 ns READ : Bank = 0 Row = 1025, Col = 11, Data = 47ecdb8f
|
| 181 |
|
|
# READ STATUS: Burst-No: 12 Addr: 00401010 Rxd: 8932d612
|
| 182 |
|
|
# tb_core.u_sdram32 : at time 13543.0 ns READ : Bank = 0 Row = 1025, Col = 12, Data = 793069f2
|
| 183 |
|
|
# READ STATUS: Burst-No: 13 Addr: 00401012 Rxd: 47ecdb8f
|
| 184 |
|
|
# READ STATUS: Burst-No: 14 Addr: 00401014 Rxd: 793069f2
|
| 185 |
27 |
dinesha |
###############################
|
| 186 |
|
|
# STATUS: SDRAM Write/Read TEST PASSED
|
| 187 |
|
|
###############################
|
| 188 |
48 |
dinesha |
# ** Note: $finish : ../tb/tb_core.sv(382)
|
| 189 |
|
|
# Time: 23570 ns Iteration: 0 Instance: /tb_core
|
| 190 |
27 |
dinesha |
### test 1: basic_test1 --> PASSED
|
| 191 |
|
|
###########################################
|
| 192 |
|
|
|
| 193 |
|
|
###########################################
|
| 194 |
|
|
### Test Logs
|
| 195 |
|
|
test 1: ../log/core_SDR_32BIT_basic_test1.log
|
| 196 |
|
|
###########################################
|
| 197 |
|
|
|
| 198 |
|
|
###########################################
|
| 199 |
|
|
### Test Summary
|
| 200 |
|
|
###
|
| 201 |
|
|
### Failed 0 of 1 SDR_32BIT tests
|
| 202 |
|
|
###########################################
|
