OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_16BIT_complie.log] - Blame information for rev 48

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 dinesha
Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov  2 2010
2
-- Compiling module tb_top
3
-- Compiling module IS42VM16400K
4
-- Compiling module mt48lc2m32b2
5
-- Compiling module mt48lc8m8a2
6
-- Compiling module sdrc_top
7
-- Compiling module wb2sdrc
8
-- Compiling module async_fifo
9
-- Compiling module sdrc_core
10
-- Compiling module sdrc_bank_ctl
11
-- Compiling module sdrc_bank_fsm
12
-- Compiling module sdrc_bs_convert
13
-- Compiling module sdrc_req_gen
14
-- Compiling module sdrc_xfr_ctl
15
 
16
Top level modules:
17
        tb_top
18
        mt48lc2m32b2
19
        mt48lc8m8a2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.