OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [model/] [IS42VM16400K.V] - Blame information for rev 52

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 dinesha 
/************************************************************************
2 
*
3 
* Copyright(c) ISSI Inc., 2010
4 
*
5 
* == 64M Low power SDRAM behavioral Model by ESC ==
6 
*
7 
* Address : 1940 Zanker Road San Jose,CA95112-4216,U.S.A.
8 
* Tel : +1-408-969-6600, Fax : +1-408-969-7800
9 
*
10 
* Revision : Rev0.0 (2010.10.4)
11 
*
12 
* Running Options
13 
*  +S50     : Set AC timing parameter for -50(200MHz  )
14 
*  +S60     : Set AC timing parameter for -60(166MHz  )
15 
*  +S75     : Set AC timing parameter for -75(133MHz  )
16 
*  +VERBOSE : Display internal operation status
17 
*
18 
************************************************************************/
19 
 
20 
`timescale 1ns / 1ps
21 
 
22 
    module IS42VM16400K (dq, addr, ba, clk, cke, csb, rasb, casb, web, dqm);
23 
 
24 
    parameter no_of_bank =       2;
25 
    parameter no_of_addr =      12;
26 
    parameter no_of_data =      16;
27 
    parameter no_of_col  =       8;
28 
    parameter no_of_dqm  =       2;
29 
    parameter mem_sizes  = 1048575;
30 
 
31 
 
32 
    // Timing Parameters for -50 PC200
33 
    `ifdef S50
34 
    parameter tAC3 =   5.0;
35 
    parameter tHZ3 =   5.0;
36 
    parameter tAC2 =   8.0;
37 
    parameter tHZ2 =   8.0;
38 
    parameter tOH  =   2.0;
39 
    parameter tMRD =   2.0;
40 
    parameter tRAS =  40.0;
41 
    parameter tRC  =  55.0;
42 
    parameter tRCD =  18.0;
43 
    parameter tRFC =  60.0;
44 
    parameter tXSR =  60.0;
45 
    parameter tRP  =  15.0;
46 
    parameter tRRD =  10.0;
47 
    parameter tDPLa =  5.0;
48 
    parameter tDPLm =  12.0;
49 
    parameter tDPDX =  100000.0;
50 
    `endif
51 
 
52 
 
53 
    // Timing Parameters for -60 PC166
54 
    `ifdef S60
55 
    parameter tAC3 =   5.5;
56 
    parameter tHZ3 =   5.5;
57 
    parameter tAC2 =   8.0;
58 
    parameter tHZ2 =   8.0;
59 
    parameter tOH  =   2.5;
60 
    parameter tMRD =   2.0;
61 
    parameter tRAS =  42.0;
62 
    parameter tRC  =  60.0;
63 
    parameter tRCD =  18.0;
64 
    parameter tRFC =  66.0;
65 
    parameter tXSR =  66.0;
66 
    parameter tRP  =  18.0;
67 
    parameter tRRD =  12.0;
68 
    parameter tDPLa =  6.0;
69 
    parameter tDPLm =  12.0;
70 
    parameter tDPDX =  100000.0;
71 
    `endif
72 
 
73 
    // Timing Parameters for -75 PC133
74 
    `ifdef S75
75 
    parameter tAC3 =   6.0;
76 
    parameter tHZ3 =   6.0;
77 
    parameter tAC2 =   8.0;
78 
    parameter tHZ2 =   8.0;
79 
    parameter tOH  =   2.5;
80 
    parameter tMRD =   2.0;
81 
    parameter tRAS =  45.0;
82 
    parameter tRC  =  67.5;
83 
    parameter tRCD =  22.5;
84 
    parameter tRFC =  67.5;
85 
    parameter tXSR =  67.5;
86 
    parameter tRP  =  22.5;
87 
    parameter tRRD =  15.0;
88 
    parameter tDPLa =  7.5;
89 
    parameter tDPLm =  15.0;
90 
    parameter tDPDX =  100000.0;
91 
    `endif
92 
 
93 
 
94 
    inout     [no_of_data - 1 : 0] dq;
95 
    input     [no_of_addr - 1 : 0] addr;
96 
    input     [no_of_bank - 1 : 0] ba;
97 
    input                         clk;
98 
    input                         cke;
99 
    input                         csb;
100 
    input                         rasb;
101 
    input                         casb;
102 
    input                         web;
103 
    input     [no_of_dqm - 1 : 0]  dqm;
104 
 
105 
`protect
106 
 
107 
    reg       [no_of_data - 1 : 0] bank0 [0 : mem_sizes];
108 
    reg       [no_of_data - 1 : 0] bank1 [0 : mem_sizes];
109 
    reg       [no_of_data - 1 : 0] bank2 [0 : mem_sizes];
110 
    reg       [no_of_data - 1 : 0] bank3 [0 : mem_sizes];
111 
 
112 
    reg       [no_of_bank - 1 : 0] bank_addr [0 : 3];                 // bank address Pipeline
113 
    reg       [no_of_col - 1 : 0] Col_addr [0 : 3];                 // Column address Pipeline
114 
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
115 
    reg       [no_of_dqm - 1 : 0] dqm_reg0, dqm_reg1;               // DQM Operation Pipeline
116 
    reg       [no_of_dqm - 1 : 0] dqm_save [0 : 3];                 // DQM Operation Pipeline
117 
    reg       [no_of_addr - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
118 
 
119 
    reg       [no_of_addr - 1 : 0] Mode_reg;
120 
    reg       [no_of_addr - 1 : 0] EMode_reg;
121 
    reg       [no_of_data - 1 : 0] dq_reg, dq_dqm;
122 
    reg        [no_of_col - 1 : 0] Col_temp, Burst_counter;
123 
 
124 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;    // bank Activate
125 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;        // bank Precharge
126 
 
127 
    reg                   [1 : 0] bank_precharge       [0 : 3];     // Precharge Command
128 
    reg                           A10_precharge        [0 : 3];     // addr[10] = 1 (All banks)
129 
    reg                           Auto_precharge       [0 : 3];     // RW Auto Precharge (bank)
130 
    reg                           Read_precharge       [0 : 3];     // R  Auto Precharge
131 
    reg                           Write_precharge      [0 : 3];     //  W Auto Precharge
132 
    reg                           RW_interrupt_read    [0 : 3];     // RW Interrupt Read with Auto Precharge
133 
    reg                           RW_interrupt_write   [0 : 3];     // RW Interrupt Write with Auto Precharge
134 
    reg                   [1 : 0] RW_interrupt_bank;                // RW Interrupt bank
135 
    integer                       RW_interrupt_counter [0 : 3];     // RW Interrupt Counter
136 
    integer                       Count_precharge      [0 : 3];     // RW Auto Precharge Counter
137 
 
138 
    reg                           Data_in_enable;
139 
    reg                           Data_out_enable;
140 
 
141 
    reg       [no_of_bank - 1 : 0] bank, Prev_bank;
142 
    reg       [no_of_addr - 1 : 0] Row;
143 
    reg        [no_of_col - 1 : 0] Col, Col_brst;
144 
 
145 
    reg                 [19:0]    ccc;
146 
    reg                 [3:0]     bit;
147 
    reg                 [2:0]     CL;
148 
    reg                 [8:0]     BL;
149 
    reg             RIW_violate;
150 
    reg             Dout_Drive_Flag;
151 
    reg             Pre_Dout_Drive_Flag;
152 
    reg             [10:0] Count_at_Read;
153 
    reg             Read_cmd_received;
154 
    reg             Read_cmd_received_cke;
155 
    reg             Write_cmd_received_cke;
156 
    reg             state_act_pwrdn,state_pre_pwrdn,state_dpdn,state_self;
157 
    reg             dpdn_check_start;
158 
    reg             [10:0] Read_cmd_count;
159 
    reg             [10:0] Read_cmd_count_cke;
160 
    reg             [10:0] Write_cmd_count_cke;
161 
    reg             [3:0] cmp_count;
162 
    // Internal system clock
163 
    reg                           ckeZ, Sys_clk;
164 
 
165 
    // Commands Decode
166 
    wire      Active_enable    = ~csb & ~rasb &  casb &  web ;
167 
    wire      Aref_enable      = ~csb & ~rasb & ~casb &  web & cke;
168 
    wire      Sref_enable      = ~csb & ~rasb & ~casb &  web & ~cke;
169 
    wire      Burst_term       = ~csb &  rasb &  casb & ~web & cke;
170 
    wire      Deep_pwrdn       = ~csb &  rasb &  casb & ~web & ~cke;
171 
    wire      Mode_reg_enable  = ~csb & ~rasb & ~casb & ~web & ~ba[1] & ~ba[0];
172 
    wire      EMode_reg_enable = ~csb & ~rasb & ~casb & ~web & ba[1] & ~ba[0];
173 
    wire      Prech_enable     = ~csb & ~rasb &  casb & ~web ;
174 
    wire      Read_enable      = ~csb &  rasb & ~casb &  web ;
175 
    wire      Write_enable     = ~csb &  rasb & ~casb & ~web ;
176 
 
177 
    // Burst Length Decode
178 
    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
179 
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
180 
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
181 
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
182 
    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
183 
 
184 
    // CAS Latency Decode
185 
    wire      Cas_latency_1    = ~Mode_reg[6] & ~Mode_reg[5] &  Mode_reg[4];
186 
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
187 
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
188 
 
189 
    // Write Burst Mode
190 
    wire      Write_burst_mode = Mode_reg[9];
191 
 
192 
`ifdef VERBOSE
193 
    wire      Debug            = 1'b1;                          // Debug messages : 1 = On
194 
`else
195 
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
196 
`endif
197 
 
198 
    wire      dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
199 
 
200 
    // CKE function
201 
    wire      clk_suspend_write= (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Write_cmd_received_cke;
202 
    wire      clk_suspend_read = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Read_cmd_received_cke;
203 
    wire      act_pwrdn        = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & (~Read_cmd_received_cke & ~Write_cmd_received_cke);
204 
    wire      pch_pwrdn        = (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) & (~Read_cmd_received_cke | ~Write_cmd_received_cke);
205 
 
206 
    assign    dq               = dq_reg;                        // DQ buffer
207 
 
208 
    // Commands Operation
209 
    `define   ACT       0
210 
    `define   NOP       1
211 
    `define   READ      2
212 
    `define   WRITE     3
213 
    `define   PRECH     4
214 
    `define   A_REF     5
215 
    `define   BST       6
216 
    `define   LMR       7
217 
 
218 
    // Timing Check variable
219 
    real  MRD_chk;
220 
    real  WR_chkm0, WR_chkm1, WR_chkm2, WR_chkm3;
221 
    real  RFC_chk, RRD_chk;
222 
    real  RC_chk0, RC_chk1, RC_chk2, RC_chk3 ;
223 
    real  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 ;
224 
    real  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 ;
225 
    real  RP_chk0, RP_chk1, RP_chk2, RP_chk3 ;
226 
    real  SELF_chk, DPDN_chk ;
227 
 
228 
    initial begin
229 
        mem_init;
230 
        dq_reg = {no_of_data{1'bz}};
231 
        Data_in_enable = 0; Data_out_enable = 0;
232 
        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
233 
        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
234 
        WR_chkm0 = 0; WR_chkm1 = 0; WR_chkm2 = 0; WR_chkm3 = 0;
235 
        RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
236 
        RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
237 
        MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
238 
        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
239 
        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
240 
        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
241 
        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
242 
        SELF_chk = 0; DPDN_chk = 0;
243 
        Read_cmd_received=0;
244 
        Read_cmd_count=0;
245 
        Read_cmd_received_cke=0;
246 
        Read_cmd_count_cke=0;
247 
        Write_cmd_received_cke=0;
248 
        Write_cmd_count_cke=0;
249 
        state_act_pwrdn=0;
250 
        state_pre_pwrdn=0;
251 
        state_dpdn=0;
252 
        state_self=0;
253 
        dpdn_check_start=0;
254 
        EMode_reg=0;
255 
        Mode_reg=0;
256 
        Count_at_Read=0;
257 
 
258 
        $timeformat (-9, 2, " ns", 12);
259 
    end
260 
 
261 
    // System clock generator
262 
    always begin
263 
        @ (posedge clk) begin
264 
            Sys_clk = ckeZ;
265 
            ckeZ = cke;
266 
        end
267 
        @ (negedge clk) begin
268 
            Sys_clk = 1'b0;
269 
        end
270 
    end
271 
 
272 
    always @ (posedge clk) begin
273 
        // CKE Exit
274 
        if (cke === 1'b1) begin
275 
          if (state_self === 1'b1) begin
276 
            state_self = 1'b0;
277 
            SELF_chk=$realtime;
278 
            if (Debug) $display ("Time = %t : OPERATION = SREFX : Self Refresh exit", $realtime);
279 
          end else if (state_dpdn == 1'b1) begin
280 
            state_dpdn = 1'b0;
281 
            DPDN_chk=$realtime;
282 
            if (Debug) $display ("Time = %t : OPERATION = DPDNX : Deep Powerdown exit", $realtime);
283 
          end else if (state_act_pwrdn == 1'b1) begin
284 
            state_act_pwrdn = 1'b0;
285 
            if (Debug) $display ("Time = %t : OPERATION = APDNX : Active Power down exit", $realtime);
286 
          end else if (state_pre_pwrdn == 1'b1) begin
287 
            state_pre_pwrdn = 1'b0;
288 
            if (Debug) $display ("Time = %t : OPERATION = PPDNX : Precharge Power down exit", $realtime);
289 
          end
290 
        end
291 
    end
292 
 
293 
 
294 
    always @ (Dout_Drive_Flag) begin
295 
 
296 
        if(Cas_latency_2 ==1) begin
297 
 
298 
        Pre_Dout_Drive_Flag <= #tHZ2 Dout_Drive_Flag;
299 
 
300 
        end else if(Cas_latency_3 ==1) begin
301 
 
302 
        Pre_Dout_Drive_Flag <= #tHZ3 Dout_Drive_Flag;
303 
 
304 
        end
305 
 
306 
    end
307 
 
308 
 
309 
 
310 
 
311 
    always @ (posedge Sys_clk) begin
312 
        // Internal Commamd Pipelined
313 
        Command[0] = Command[1];
314 
        Command[1] = Command[2];
315 
        Command[2] = Command[3];
316 
        Command[3] = `NOP;
317 
 
318 
        Col_addr[0] = Col_addr[1];
319 
        Col_addr[1] = Col_addr[2];
320 
        Col_addr[2] = Col_addr[3];
321 
        Col_addr[3] = {no_of_col{1'b0}};
322 
 
323 
        bank_addr[0] = bank_addr[1];
324 
        bank_addr[1] = bank_addr[2];
325 
        bank_addr[2] = bank_addr[3];
326 
        bank_addr[3] = 2'b00;
327 
 
328 
        bank_precharge[0] = bank_precharge[1];
329 
        bank_precharge[1] = bank_precharge[2];
330 
        bank_precharge[2] = bank_precharge[3];
331 
        bank_precharge[3] = 2'b00;
332 
 
333 
        A10_precharge[0] = A10_precharge[1];
334 
        A10_precharge[1] = A10_precharge[2];
335 
        A10_precharge[2] = A10_precharge[3];
336 
        A10_precharge[3] = 1'b0;
337 
 
338 
        // dqm pipeline for Read
339 
        dqm_reg0 = dqm_reg1;
340 
        dqm_reg1 = dqm;
341 
 
342 
        dqm_save[3]=dqm_save[2];
343 
        dqm_save[2]=dqm_save[1];
344 
        dqm_save[1]=dqm_save[0];
345 
        dqm_save[0]=dqm;
346 
 
347 
 
348 
        if (Read_cmd_received == 1'b1) begin
349 
           Read_cmd_count = Read_cmd_count + 1;
350 
        end
351 
        else begin
352 
           Read_cmd_count = 4'b0;
353 
        end
354 
        //if (Read_cmd_count == (BL+CL+1)) begin
355 
        if (Read_cmd_count == Count_at_Read+(BL+CL+1)) begin
356 
           Read_cmd_received = 1'b0;
357 
        end
358 
 
359 
        // Count for CKE
360 
        if (Read_cmd_received_cke == 1'b1) begin
361 
           Read_cmd_count_cke = Read_cmd_count_cke + 1;
362 
        end
363 
        else begin
364 
           Read_cmd_count_cke = 4'b0;
365 
        end
366 
        if (Read_cmd_count_cke == (BL+CL-1)) begin
367 
           Read_cmd_received_cke = 1'b0;
368 
        end
369 
 
370 
        // Count for CKE
371 
        if (Write_cmd_received_cke == 1'b1) begin
372 
           Write_cmd_count_cke = Write_cmd_count_cke + 1;
373 
        end
374 
        else begin
375 
           Write_cmd_count_cke = 4'b0;
376 
        end
377 
        if (Write_cmd_count_cke == BL) begin
378 
           Write_cmd_received_cke = 1'b0;
379 
        end
380 
 
381 
 
382 
 
383 
        // Read or Write with Auto Precharge Counter
384 
        if (Auto_precharge[0] === 1'b1) begin
385 
            Count_precharge[0] = Count_precharge[0] + 1;
386 
        end
387 
        if (Auto_precharge[1] === 1'b1) begin
388 
            Count_precharge[1] = Count_precharge[1] + 1;
389 
        end
390 
        if (Auto_precharge[2] === 1'b1) begin
391 
            Count_precharge[2] = Count_precharge[2] + 1;
392 
        end
393 
        if (Auto_precharge[3] === 1'b1) begin
394 
            Count_precharge[3] = Count_precharge[3] + 1;
395 
        end
396 
 
397 
        // Read or Write Interrupt Counter
398 
        if (RW_interrupt_write[0] === 1'b1) begin
399 
            RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
400 
        end
401 
        if (RW_interrupt_write[1] === 1'b1) begin
402 
            RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
403 
        end
404 
        if (RW_interrupt_write[2] === 1'b1) begin
405 
            RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
406 
        end
407 
        if (RW_interrupt_write[3] === 1'b1) begin
408 
            RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
409 
        end
410 
 
411 
        // tMRD Counter
412 
        MRD_chk = MRD_chk + 1;
413 
 
414 
        // Auto Refresh
415 
        if (Aref_enable === 1'b1) begin
416 
            if (Debug) begin
417 
                //$display ("%m : at time %t AREF : Auto Refresh", $realtime);
418 
                $display ("Time = %t : OPERATION = AREF  : Auto Refresh", $realtime);
419 
            end
420 
 
421 
            // DPDXN to Auto Refresh
422 
            if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
423 
                $display ("Time = %t : ERROR : Pwrup violation(DPDX to AREF)", $realtime);
424 
            end
425 
 
426 
            // Self exit to Auto Refresh
427 
            if ($realtime - SELF_chk < tXSR) begin
428 
                $display ("Time = %t : ERROR : tXSR violation(SREFX to AREF)", $realtime);
429 
            end
430 
 
431 
            // Auto Refresh to Auto Refresh
432 
            if ($realtime - RFC_chk < tRFC) begin
433 
                //$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $realtime);
434 
                $display ("Time = %t : ERROR : tRFC violation(AREF to AREF)", $realtime);
435 
            end
436 
 
437 
            // Precharge to Auto Refresh
438 
            if (($realtime - RP_chk0 < tRP)) begin
439 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
440 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE0 to AREF)", $realtime);
441 
            end
442 
            if (($realtime - RP_chk1 < tRP)) begin
443 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
444 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE1 to AREF)", $realtime);
445 
            end
446 
            if (($realtime - RP_chk2 < tRP)) begin
447 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
448 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE2 to AREF)", $realtime);
449 
            end
450 
            if (($realtime - RP_chk3 < tRP)) begin
451 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
452 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE3 to AREF)", $realtime);
453 
            end
454 
 
455 
 
456 
            // Precharge to Refresh
457 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
458 
                //$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $realtime);
459 
                $display ("Time = %t : ERROR : All banks must be Precharged before AREF", $realtime);
460 
            end
461 
 
462 
            // Load Mode Register to Auto Refresh
463 
            if (MRD_chk < tMRD) begin
464 
                //$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $realtime);
465 
                $display ("Time = %t : ERROR : tMRD violation(MRS to AREF)", $realtime);
466 
            end
467 
 
468 
            // Record Current tRFC time
469 
            RFC_chk = $realtime;
470 
        end
471 
 
472 
        // Load Mode Register
473 
        if (Mode_reg_enable === 1'b1) begin
474 
            // Register Mode
475 
            Mode_reg = addr;
476 
 
477 
            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
478 
            if (Debug) begin
479 
                //$display ("%m : at time %t LMR  : Load Mode Register", $realtime);
480 
                $display ("Time = %t : OPERATION = MRS   : Load Mode Register", $realtime);
481 
                // CAS Latency
482 
                case (addr[6 : 4])
483 
                    3'b010  : $display ("                                 CAS Latency      = 2");
484 
                    3'b011  : $display ("                                 CAS Latency      = 3");
485 
                    default : $display ("                                 CAS Latency      = Reserved");
486 
                endcase
487 
                case (addr[6 : 4])
488 
                    3'b010  : CL=2;
489 
                    3'b011  : CL=3;
490 
                    default : CL=3;
491 
                endcase
492 
 
493 
                // Burst Length
494 
                case (addr[2 : 0])
495 
                    3'b000  : $display ("                                 Burst Length     = 1");
496 
                    3'b001  : $display ("                                 Burst Length     = 2");
497 
                    3'b010  : $display ("                                 Burst Length     = 4");
498 
                    3'b011  : $display ("                                 Burst Length     = 8");
499 
                    3'b111  : $display ("                                 Burst Length     = Full");
500 
                    default : $display ("                                 Burst Length     = Reserved");
501 
                endcase
502 
 
503 
                case (addr[2 : 0])
504 
                    3'b000  : BL=1;
505 
                    3'b001  : BL=2;
506 
                    3'b010  : BL=4;
507 
                    3'b011  : BL=8;
508 
                    3'b111  : BL=512;
509 
                    default : BL=4;
510 
                endcase
511 
 
512 
 
513 
                // Burst Type
514 
                if (addr[3] === 1'b0) begin
515 
                    $display ("                                 Burst Type       = Sequential");
516 
                end else if (addr[3] === 1'b1) begin
517 
                    $display ("                                 Burst Type       = Interleaved");
518 
                end else begin
519 
                    $display ("                                 Burst Type       = Reserved");
520 
                end
521 
 
522 
                // Write Burst Mode
523 
                if (addr[9] === 1'b0) begin
524 
                    $display ("                                 Write Burst Mode = Programmed Burst Length");
525 
                end else if (addr[9] === 1'b1) begin
526 
                    $display ("                                 Write Burst Mode = Single Location Access");
527 
                end else begin
528 
                    $display ("                                 Write Burst Mode = Reserved");
529 
                end
530 
            end
531 
 
532 
            // Precharge to Load Mode Register
533 
            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0 ) begin
534 
                //$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
535 
                $display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
536 
            end
537 
 
538 
            // Precharge to Load Mode Register
539 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
540 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
541 
                //$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
542 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to MRS)", $realtime);
543 
            end
544 
 
545 
            // Auto Refresh to Load Mode Register
546 
            if ($realtime - RFC_chk < tRFC) begin
547 
                //$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
548 
                $display ("Time = %t : ERROR : tRFC violation(AREF to MRS)", $realtime);
549 
            end
550 
 
551 
            // Load Mode Register to Load Mode Register
552 
            if (MRD_chk < tMRD) begin
553 
                //$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
554 
                $display ("Time = %t : ERROR : tMRD violation(MRS to MRS)", $realtime);
555 
            end
556 
 
557 
            // Reset MRD Counter
558 
            MRD_chk = 0;
559 
        end
560 
 
561 
        // Load Extended Mode Register
562 
        if (EMode_reg_enable === 1'b1) begin
563 
            // Register Mode
564 
            EMode_reg = addr;
565 
 
566 
            // Decode Driver Strength, Maximum Case Temp, Self Refresh Coverage
567 
            if (Debug) begin
568 
                //$display ("%m : at time %t LMR  : Load Mode Register", $realtime);
569 
                $display ("Time = %t : OPERATION = EMRS  : Load Extended Mode Register", $realtime);
570 
                // Driver Strength
571 
                case (addr[6 : 5])
572 
                    2'b00   : $display ("                                 Driver Strength        = Full");
573 
                    2'b01   : $display ("                                 Driver Strength        = 1/2");
574 
                    2'b10   : $display ("                                 Driver Strength        = 1/4");
575 
                    2'b11   : $display ("                                 Driver Strength        = 1/8");
576 
                    default : $display ("                                 Driver Strength        = Reserved");
577 
                endcase
578 
 
579 
                // Self Refresh Coverage
580 
                case (addr[2 : 0])
581 
                    3'b000   : $display ("                                 Self Refresh Coverage  = All Banks");
582 
                    3'b001   : $display ("                                 Self Refresh Coverage  = TWO Bank");
583 
                    3'b010   : $display ("                                 Self Refresh Coverage  = One Bank");
584 
                    3'b101   : $display ("                                 Self Refresh Coverage  = Half of one Banks");
585 
                    3'b110   : $display ("                                 Self Refresh Coverage  = Quater of one Banks");
586 
                    default  : $display ("                                 Self Refresh Coverage  = Reserved");
587 
                endcase
588 
 
589 
            end
590 
 
591 
            // Precharge to Load Mode Register
592 
            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
593 
                //$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
594 
                $display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
595 
            end
596 
 
597 
            // Precharge to Load Mode Register
598 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
599 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
600 
                //$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
601 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to EMRS)", $realtime);
602 
            end
603 
 
604 
            // Auto Refresh to Load Mode Register
605 
            if ($realtime - RFC_chk < tRFC) begin
606 
                //$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
607 
                $display ("Time = %t : ERROR : tRFC violation(AREF to EMRS)", $realtime);
608 
            end
609 
 
610 
            // Load Mode Register to Load Mode Register
611 
            if (MRD_chk < tMRD) begin
612 
                //$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
613 
                $display ("Time = %t : ERROR : tMRD violation(MRS to EMRS)", $realtime);
614 
            end
615 
 
616 
            // Reset MRD Counter
617 
            MRD_chk = 0;
618 
        end
619 
 
620 
        // Active Block (Latch bank address and Row address)
621 
        if (Active_enable === 1'b1) begin
622 
            // Activate an open bank can corrupt data
623 
            if ((ba === 2'b00 && Act_b0 === 1'b1) || (ba === 2'b01 && Act_b1 === 1'b1) ||
624 
                (ba === 2'b10 && Act_b2 === 1'b1) || (ba === 2'b11 && Act_b3 === 1'b1)) begin
625 
                //$display ("%m : at time %t ERROR: bank already activated -- data can be corrupted", $realtime);
626 
                $display ("Time = %t : ERROR : bank already activated -- data could be corrupted", $realtime);
627 
               // $display ("Time = %t : Bank = %d, Act_b0 = %d, Act_b2 = %d", $realtime, ba, Act_b0, Act_b2);
628 
            end
629 
 
630 
            // Activate bank 0
631 
            if (ba === 2'b00 && Pc_b0 === 1'b1) begin
632 
                // Debug Message
633 
                if (Debug) begin
634 
                    //$display ("%m : at time %t ACT  : bank = 0 Row = %d", $realtime, addr);
635 
                    $display ("Time = %t : OPERATION = ACT   : bank = 0 Row = 'h%h", $realtime, addr);
636 
                end
637 
 
638 
                // Self exit to ACTIVE
639 
                if ($realtime - SELF_chk < tXSR) begin
640 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT0)", $realtime);
641 
                end
642 
 
643 
                // DPDXN to Precharge
644 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
645 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT0)", $realtime);
646 
                end
647 
 
648 
                // ACTIVE to ACTIVE command period
649 
                if ($realtime - RC_chk0 < tRC) begin
650 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $realtime);
651 
                    $display ("Time = %t : ERROR : tRC violation (ACT0 to ACT0) ", $realtime);
652 
                end
653 
 
654 
                // Precharge to Activate bank 0
655 
                if ($realtime - RP_chk0 < tRP) begin
656 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $realtime);
657 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE0 to PRECHARGE0) ", $realtime);
658 
                end
659 
 
660 
                // Record variables
661 
                Act_b0 = 1'b1;
662 
                Pc_b0 = 1'b0;
663 
                B0_row_addr = addr [no_of_addr - 1 : 0];
664 
                RAS_chk0 = $realtime;
665 
                RC_chk0 = $realtime;
666 
                RCD_chk0 = $realtime;
667 
            end
668 
 
669 
            // Activate bank 1
670 
            if (ba === 2'b01 && Pc_b1 === 1'b1) begin
671 
                // Debug Message
672 
                if (Debug) begin
673 
                    //$display ("%m : at time %t ACT  : bank = 1 Row = %d", $realtime, addr);
674 
                    $display ("Time = %t : OPERATION = ACT   : bank = 1 Row = 'h%h", $realtime, addr);
675 
                end
676 
 
677 
                // DPDXN to Precharge
678 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
679 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT1)", $realtime);
680 
                end
681 
 
682 
                // Self exit to ACTIVE
683 
                if ($realtime - SELF_chk < tXSR) begin
684 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT1)", $realtime);
685 
                end
686 
 
687 
                // ACTIVE to ACTIVE command period
688 
                if ($realtime - RC_chk1 < tRC) begin
689 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $realtime);
690 
                    $display ("Time = %t : ERROR : tRC violation (ACT1 to ACT1) ", $realtime);
691 
                end
692 
 
693 
                // Precharge to Activate bank 1
694 
                if ($realtime - RP_chk1 < tRP) begin
695 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $realtime);
696 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE1 to PRECHARGE1) ", $realtime);
697 
                end
698 
 
699 
                // Record variables
700 
                Act_b1 = 1'b1;
701 
                Pc_b1 = 1'b0;
702 
                B1_row_addr = addr [no_of_addr - 1 : 0];
703 
                RAS_chk1 = $realtime;
704 
                RC_chk1 = $realtime;
705 
                RCD_chk1 = $realtime;
706 
            end
707 
 
708 
            // Activate bank 2
709 
            if (ba === 2'b10 && Pc_b2 === 1'b1) begin
710 
                // Debug Message
711 
                if (Debug) begin
712 
                    //$display ("%m : at time %t ACT  : bank = 2 Row = %d", $realtime, addr);
713 
                    $display ("Time = %t : OPERATION = ACT   : bank = 2 Row = 'h%h", $realtime, addr);
714 
                end
715 
 
716 
                // DPDXN to Precharge
717 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
718 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT2)", $realtime);
719 
                end
720 
 
721 
                // Self exit to ACTIVE
722 
                if ($realtime - SELF_chk < tXSR) begin
723 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT2)", $realtime);
724 
                end
725 
 
726 
                // ACTIVE to ACTIVE command period
727 
                if ($realtime - RC_chk2 < tRC) begin
728 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $realtime);
729 
                    $display ("Time = %t : ERROR : tRC violation (ACT2 to ACT2) ", $realtime);
730 
                end
731 
 
732 
                // Precharge to Activate bank 2
733 
                if ($realtime - RP_chk2 < tRP) begin
734 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $realtime);
735 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE2 to PRECHARGE2) ", $realtime);
736 
                end
737 
 
738 
                // Record variables
739 
                Act_b2 = 1'b1;
740 
                Pc_b2 = 1'b0;
741 
                B2_row_addr = addr [no_of_addr - 1 : 0];
742 
                RAS_chk2 = $realtime;
743 
                RC_chk2 = $realtime;
744 
                RCD_chk2 = $realtime;
745 
            end
746 
 
747 
            // Activate bank 3
748 
            if (ba === 2'b11 && Pc_b3 === 1'b1) begin
749 
                // Debug Message
750 
                if (Debug) begin
751 
                    //$display ("%m : at time %t ACT  : bank = 3 Row = %d", $realtime, addr);
752 
                    $display ("Time = %t : OPERATION = ACT   : bank = 3 Row = 'h%h", $realtime, addr);
753 
                end
754 
 
755 
                // DPDXN to Precharge
756 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
757 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT3)", $realtime);
758 
                end
759 
 
760 
                // Self exit to ACTIVE
761 
                if ($realtime - SELF_chk < tXSR) begin
762 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT3)", $realtime);
763 
                end
764 
 
765 
                // ACTIVE to ACTIVE command period
766 
                if ($realtime - RC_chk3 < tRC) begin
767 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $realtime);
768 
                    $display ("Time = %t : ERROR : tRC violation (ACT1 to ACT3) ", $realtime);
769 
                end
770 
 
771 
                // Precharge to Activate bank 3
772 
                if ($realtime - RP_chk3 < tRP) begin
773 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $realtime);
774 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE3 to PRECHARGE3) ", $realtime);
775 
                end
776 
 
777 
                // Record variables
778 
                Act_b3 = 1'b1;
779 
                Pc_b3 = 1'b0;
780 
                B3_row_addr = addr [no_of_addr - 1 : 0];
781 
                RAS_chk3 = $realtime;
782 
                RC_chk3 = $realtime;
783 
                RCD_chk3 = $realtime;
784 
            end
785 
 
786 
            // Active other bank to Active bank A
787 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b00)) begin
788 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
789 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT0) ", $realtime);
790 
            end
791 
 
792 
            // Active other bank to Active bank B
793 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b01)) begin
794 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
795 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT1) ", $realtime);
796 
            end
797 
 
798 
            // Active other bank to Active bank C
799 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b10)) begin
800 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
801 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT2) ", $realtime);
802 
            end
803 
 
804 
            // Active other bank to Active bank D
805 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b11)) begin
806 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
807 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT3) ", $realtime);
808 
            end
809 
 
810 
            // Auto Refresh to Activate
811 
            if ($realtime - RFC_chk < tRFC) begin
812 
                //$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $realtime, ba);
813 
                $display ("Time = %t : ERROR : tRFC violation(AREF to ACT)", $realtime);
814 
            end
815 
 
816 
            // Load Mode Register to Active
817 
            if (MRD_chk < tMRD ) begin
818 
                //$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $realtime, ba);
819 
                $display ("Time = %t : ERROR : tMRD violation(MRS to ACT)", $realtime);
820 
            end
821 
 
822 
            // Record variables for checking violation
823 
            RRD_chk = $realtime;
824 
            Prev_bank = ba;
825 
        end
826 
 
827 
        // Precharge Block
828 
        if (Prech_enable == 1'b1) begin
829 
            // Load Mode Register to Precharge
830 
            if ($realtime - MRD_chk < tMRD) begin
831 
                //$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $realtime);
832 
                $display ("Time = %t : ERROR : tMRD violation(MRS to PRECHARGE)", $realtime);
833 
            end
834 
 
835 
            //Precharge bank 0
836 
 
837 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b00)) && Act_b0 === 1'b1) begin
838 
                Act_b0 = 1'b0;
839 
                Pc_b0 = 1'b1;
840 
                RP_chk0 = $realtime;
841 
 
842 
                if (Debug) begin
843 
                    //$display ("%m : at time %t ACT  : bank = 0 Row = %d", $realtime, addr);
844 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 0 ", $realtime);
845 
                end
846 
 
847 
                // DPDXN to Precharge
848 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
849 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE0)", $realtime);
850 
                end
851 
 
852 
                // Activate to Precharge
853 
                if ($realtime - RAS_chk0 < tRAS) begin
854 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
855 
                    $display ("Time = %t : ERROR : tRAS violation(ACT0 to PRECHARGE0)", $realtime);
856 
                end
857 
 
858 
                // tWR violation check for write
859 
                if ($realtime - WR_chkm0 < tDPLm) begin
860 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
861 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE0)", $realtime);
862 
                end
863 
            end
864 
 
865 
            // Precharge bank 1
866 
 
867 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b01)) && Act_b1 === 1'b1) begin
868 
                Act_b1 = 1'b0;
869 
                Pc_b1 = 1'b1;
870 
                RP_chk1 = $realtime;
871 
 
872 
                if (Debug) begin
873 
                    //$display ("%m : at time %t ACT  : bank = 1 Row = %d", $realtime, addr);
874 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 1 ", $realtime);
875 
                end
876 
 
877 
                // DPDXN to Precharge
878 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
879 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE1)", $realtime);
880 
                end
881 
 
882 
                // Activate to Precharge
883 
                if ($realtime - RAS_chk1 < tRAS) begin
884 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
885 
                    $display ("Time = %t : ERROR : tRAS violation(ACT1 to PRECHARGE1)", $realtime);
886 
                end
887 
 
888 
                // tWR violation check for write
889 
                if ($realtime - WR_chkm1 < tDPLm) begin
890 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
891 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE1)", $realtime);
892 
                end
893 
            end
894 
 
895 
            // Precharge bank 2
896 
 
897 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b10)) && Act_b2 === 1'b1) begin
898 
                Act_b2 = 1'b0;
899 
                Pc_b2 = 1'b1;
900 
                RP_chk2 = $realtime;
901 
 
902 
                if (Debug) begin
903 
                    //$display ("%m : at time %t ACT  : bank = 2 Row = %d", $realtime, addr);
904 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 2 ", $realtime);
905 
                end
906 
 
907 
                // DPDXN to Precharge
908 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
909 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE2)", $realtime);
910 
                end
911 
 
912 
                // Activate to Precharge
913 
                if ($realtime - RAS_chk2 < tRAS) begin
914 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
915 
                    $display ("Time = %t : ERROR : tRAS violation(ACT2 to PRECHARGE2)", $realtime);
916 
                end
917 
 
918 
                // tWR violation check for write
919 
                if ($realtime - WR_chkm2 < tDPLm) begin
920 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
921 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE2)", $realtime);
922 
                end
923 
            end
924 
 
925 
            // Precharge bank 3
926 
 
927 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b11)) && Act_b3 === 1'b1) begin
928 
                Act_b3 = 1'b0;
929 
                Pc_b3 = 1'b1;
930 
                RP_chk3 = $realtime;
931 
 
932 
                if (Debug) begin
933 
                    //$display ("%m : at time %t ACT  : bank = 3 Row = %d", $realtime, addr);
934 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 3 ", $realtime);
935 
                end
936 
 
937 
                // DPDXN to Precharge
938 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
939 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE3)", $realtime);
940 
                end
941 
 
942 
                // Activate to Precharge
943 
                if ($realtime - RAS_chk3 < tRAS) begin
944 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
945 
                    $display ("Time = %t : ERROR : tRAS violation(ACT3 to PRECHARGE3)", $realtime);
946 
                end
947 
 
948 
                // tWR violation check for write
949 
                if ($realtime - WR_chkm3 < tDPLm) begin
950 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
951 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE3)", $realtime);
952 
                end
953 
            end
954 
 
955 
 
956 
            // Terminate a Write Immediately (if same bank or all banks)
957 
            if (Data_in_enable === 1'b1 && (bank === ba || addr[10] === 1'b1)) begin
958 
                Data_in_enable = 1'b0;
959 
            end
960 
 
961 
            // Precharge Command Pipeline for Read
962 
            if (Cas_latency_3 === 1'b1) begin
963 
                Command[2] = `PRECH;
964 
                bank_precharge[2] = ba;
965 
                A10_precharge[2] = addr[10];
966 
            end else if (Cas_latency_2 === 1'b1) begin
967 
                Command[1] = `PRECH;
968 
                bank_precharge[1] = ba;
969 
                A10_precharge[1] = addr[10];
970 
            end
971 
        end
972 
 
973 
        // Burst terminate
974 
        if (Burst_term === 1'b1) begin
975 
            // Terminate a Write Immediately
976 
            if (Data_in_enable == 1'b1) begin
977 
                Data_in_enable = 1'b0;
978 
            end
979 
 
980 
            // Terminate a Read Depend on CAS Latency
981 
            if (Cas_latency_3 === 1'b1) begin
982 
                Command[2] = `BST;
983 
            end else if (Cas_latency_2 == 1'b1) begin
984 
                Command[1] = `BST;
985 
            end
986 
 
987 
            // Display debug message
988 
            if (Debug) begin
989 
                //$display ("%m : at time %t BST  : Burst Terminate",$realtime);
990 
                  $display ("Time = %t : OPERATION = BST   : Burst Stop", $realtime);
991 
            end
992 
        end
993 
 
994 
        // Read, Write, Column Latch
995 
        if (Read_enable === 1'b1) begin
996 
 
997 
            Read_cmd_received = 1'b1;
998 
            Read_cmd_received_cke = 1'b1;
999 
            //Read_cmd_count = 0;
1000 
            Count_at_Read = Read_cmd_count;
1001 
            Read_cmd_count_cke = 0;
1002 
            Write_cmd_received_cke = 1'b0;
1003 
 
1004 
            // Check to see if bank is open (ACT)
1005 
            if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
1006 
                (ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
1007 
                //$display("%m : at time %t ERROR: bank is not Activated for Read", $realtime);
1008 
                  $display ("Time = %t : ERROR : bank is not Activated for Read", $realtime);
1009 
            end
1010 
 
1011 
            // Activate to Read or Write
1012 
            if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD) ||
1013 
                (ba == 2'b01) && ($realtime - RCD_chk1 < tRCD) ||
1014 
                (ba == 2'b10) && ($realtime - RCD_chk2 < tRCD) ||
1015 
                (ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
1016 
                //$display("%m : at time %t ERROR: tRCD violation during Read", $realtime);
1017 
                  $display ("Time = %t : ERROR : tRCD violation(ACT to READ)", $realtime);
1018 
            end
1019 
 
1020 
            // CAS Latency pipeline
1021 
            if (Cas_latency_3 == 1'b1) begin
1022 
                Command[2] = `READ;
1023 
                Col_addr[2] = addr;
1024 
                bank_addr[2] = ba;
1025 
            end else if (Cas_latency_2 == 1'b1) begin
1026 
                Command[1] = `READ;
1027 
                Col_addr[1] = addr;
1028 
                bank_addr[1] = ba;
1029 
            end
1030 
 
1031 
            // Read interrupt Write (terminate Write immediately)
1032 
            if (Data_in_enable == 1'b1) begin
1033 
                Data_in_enable = 1'b0;
1034 
 
1035 
                // Interrupting a Write with Autoprecharge
1036 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
1037 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
1038 
                    RW_interrupt_counter[RW_interrupt_bank] = 0;
1039 
 
1040 
                    // Display debug message
1041 
                    if (Debug) begin
1042 
                        //$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $realtime);
1043 
                        $display ("Time = %t : OPERATION = Read interrupt Write with Autoprecharge", $realtime);
1044 
                    end
1045 
                end
1046 
            end
1047 
 
1048 
            // Read with Auto Precharge
1049 
            if (addr[10] == 1'b1) begin
1050 
                Auto_precharge[ba] = 1'b1;
1051 
                Count_precharge[ba] = 0;
1052 
                RW_interrupt_bank = ba;
1053 
                Read_precharge[ba] = 1'b1;
1054 
            end
1055 
        end
1056 
 
1057 
        // Write Command
1058 
        if (Write_enable == 1'b1) begin
1059 
 
1060 
            RIW_violate=1'b0;
1061 
            if ((Pre_Dout_Drive_Flag == 1'b1) || (Dout_Drive_Flag == 1'b1)) begin
1062 
                  $display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
1063 
            end
1064 
            else if ((Data_out_enable == 1'b1) && (&(dqm_save[1]) != 1'b1)) begin
1065 
                  $display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
1066 
            end
1067 
 
1068 
 
1069 
            Write_cmd_received_cke=1'b1;
1070 
            Read_cmd_received=1'b0;
1071 
            Read_cmd_received_cke=1'b0;
1072 
            Write_cmd_count_cke=1'b0;
1073 
 
1074 
            // Activate to Write
1075 
            if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
1076 
                (ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
1077 
                //$display("%m : at time %t ERROR: bank is not Activated for Write", $realtime);
1078 
                  $display ("Time = %t : ERROR : bank is not Activated for Write", $realtime);
1079 
            end
1080 
 
1081 
            if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD)) begin
1082 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT0 to WRITE)", $realtime, RCD_chk0,$realtime-RCD_chk0);
1083 
            end
1084 
            if ((ba == 2'b01) && ($realtime - RCD_chk1 < tRCD)) begin
1085 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT1 to WRITE)", $realtime, RCD_chk1,$realtime-RCD_chk1);
1086 
            end
1087 
            if ((ba == 2'b10) && ($realtime - RCD_chk2 < tRCD)) begin
1088 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT2 to WRITE)", $realtime, RCD_chk2,$realtime-RCD_chk2);
1089 
            end
1090 
            if ((ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
1091 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT3 to WRITE)", $realtime, RCD_chk3,$realtime-RCD_chk3);
1092 
            end
1093 
 
1094 
 
1095 
            // Latch Write command, bank, and Column
1096 
            Command[0] = `WRITE;
1097 
            Command[1] = `NOP;
1098 
            Col_addr[0] = addr;
1099 
            bank_addr[0] = ba;
1100 
 
1101 
            // Write interrupt Write (terminate Write immediately)
1102 
            if (Data_in_enable == 1'b1) begin
1103 
                Data_in_enable = 1'b0;
1104 
 
1105 
                // Interrupting a Write with Autoprecharge
1106 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
1107 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
1108 
 
1109 
                    // Display debug message
1110 
                    if (Debug) begin
1111 
                        //$display ("%m : at time %t NOTE : Read bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1112 
                        $display ("Time = %t : OPERATION = Write bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1113 
 
1114 
                    end
1115 
                end
1116 
            end
1117 
 
1118 
            // Write interrupt Read (terminate Read immediately)
1119 
            if (Data_out_enable == 1'b1) begin
1120 
                Data_out_enable = 1'b0;
1121 
 
1122 
                // Interrupting a Read with Autoprecharge
1123 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
1124 
                    RW_interrupt_read[RW_interrupt_bank] = 1'b1;
1125 
 
1126 
                    // Display debug message
1127 
                    if (Debug) begin
1128 
                        //$display ("%m : at time %t NOTE : Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1129 
                        $display ("Time = %t : OPERATION = Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1130 
                    end
1131 
                end
1132 
            end
1133 
 
1134 
            // Write with Auto Precharge
1135 
            if (addr[10] == 1'b1) begin
1136 
                Auto_precharge[ba] = 1'b1;
1137 
                Count_precharge[ba] = 0;
1138 
                RW_interrupt_bank = ba;
1139 
                Write_precharge[ba] = 1'b1;
1140 
            end
1141 
        end
1142 
 
1143 
        /*
1144 
            Write with Auto Precharge Calculation
1145 
                The device start internal precharge when:
1146 
                    1.  Meet minimum tRAS requirement
1147 
                and 2.  tWR cycle(s) after last valid data
1148 
                 or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
1149 
 
1150 
            Note: Model is starting the internal precharge 1 cycle after they meet all the
1151 
                  requirement but tRP will be compensate for the time after the 1 cycle.
1152 
        */
1153 
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
1154 
            if ((($realtime - RAS_chk0 >= tRAS) &&                                                          // Case 1
1155 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||   // Case 2
1156 
                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
1157 
                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
1158 
                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
1159 
                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin                 // Case 3
1160 
                    Auto_precharge[0] = 1'b0;
1161 
                    Write_precharge[0] = 1'b0;
1162 
                    RW_interrupt_write[0] = 1'b0;
1163 
                    Pc_b0 = 1'b1;
1164 
                    Act_b0 = 1'b0;
1165 
                    RP_chk0 = $realtime + tDPLa;
1166 
                    if (Debug) begin
1167 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
1168 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime+tDPLa);
1169 
                    end
1170 
            end
1171 
        end
1172 
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
1173 
            if ((($realtime - RAS_chk1 >= tRAS) &&                                                          // Case 1
1174 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||   // Case 2
1175 
                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
1176 
                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
1177 
                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
1178 
                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin                 // Case 3
1179 
                    Auto_precharge[1] = 1'b0;
1180 
                    Write_precharge[1] = 1'b0;
1181 
                    RW_interrupt_write[1] = 1'b0;
1182 
                    Pc_b1 = 1'b1;
1183 
                    Act_b1 = 1'b0;
1184 
                    RP_chk1 = $realtime + tDPLa;
1185 
                    if (Debug) begin
1186 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
1187 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime+tDPLa);
1188 
                    end
1189 
            end
1190 
        end
1191 
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
1192 
            if ((($realtime - RAS_chk2 >= tRAS) &&                                                          // Case 1
1193 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||   // Case 2
1194 
                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
1195 
                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
1196 
                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
1197 
                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin                 // Case 3
1198 
                    Auto_precharge[2] = 1'b0;
1199 
                    Write_precharge[2] = 1'b0;
1200 
                    RW_interrupt_write[2] = 1'b0;
1201 
                    Pc_b2 = 1'b1;
1202 
                    Act_b2 = 1'b0;
1203 
                    RP_chk2 = $realtime + tDPLa;
1204 
                    if (Debug) begin
1205 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
1206 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime+tDPLa);
1207 
                    end
1208 
            end
1209 
        end
1210 
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
1211 
            if ((($realtime - RAS_chk3 >= tRAS) &&                                                          // Case 1
1212 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||   // Case 2
1213 
                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
1214 
                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
1215 
                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
1216 
                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin                 // Case 3
1217 
                    Auto_precharge[3] = 1'b0;
1218 
                    Write_precharge[3] = 1'b0;
1219 
                    RW_interrupt_write[3] = 1'b0;
1220 
                    Pc_b3 = 1'b1;
1221 
                    Act_b3 = 1'b0;
1222 
                    RP_chk3 = $realtime + tDPLa;
1223 
                    if (Debug) begin
1224 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
1225 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime+tDPLa);
1226 
                    end
1227 
            end
1228 
        end
1229 
 
1230 
        //  Read with Auto Precharge Calculation
1231 
        //      The device start internal precharge:
1232 
        //          1.  Meet minimum tRAS requirement
1233 
        //      and 2.  CAS Latency - 1 cycles before last burst
1234 
        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
1235 
        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
1236 
            if ((($realtime - RAS_chk0 >= tRAS) &&                                                      // Case 1
1237 
                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 2
1238 
                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
1239 
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
1240 
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
1241 
                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
1242 
                    Pc_b0 = 1'b1;
1243 
                    Act_b0 = 1'b0;
1244 
                    RP_chk0 = $realtime;
1245 
                    Auto_precharge[0] = 1'b0;
1246 
                    Read_precharge[0] = 1'b0;
1247 
                    RW_interrupt_read[0] = 1'b0;
1248 
                    if (Debug) begin
1249 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
1250 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime);
1251 
                    end
1252 
            end
1253 
        end
1254 
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
1255 
            if ((($realtime - RAS_chk1 >= tRAS) &&
1256 
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
1257 
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
1258 
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
1259 
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
1260 
                 (RW_interrupt_read[1] == 1'b1)) begin
1261 
                    Pc_b1 = 1'b1;
1262 
                    Act_b1 = 1'b0;
1263 
                    RP_chk1 = $realtime;
1264 
                    Auto_precharge[1] = 1'b0;
1265 
                    Read_precharge[1] = 1'b0;
1266 
                    RW_interrupt_read[1] = 1'b0;
1267 
                    if (Debug) begin
1268 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
1269 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime);
1270 
                    end
1271 
            end
1272 
        end
1273 
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
1274 
            if ((($realtime - RAS_chk2 >= tRAS) &&
1275 
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
1276 
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
1277 
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
1278 
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
1279 
                 (RW_interrupt_read[2] == 1'b1)) begin
1280 
                    Pc_b2 = 1'b1;
1281 
                    Act_b2 = 1'b0;
1282 
                    RP_chk2 = $realtime;
1283 
                    Auto_precharge[2] = 1'b0;
1284 
                    Read_precharge[2] = 1'b0;
1285 
                    RW_interrupt_read[2] = 1'b0;
1286 
                    if (Debug) begin
1287 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
1288 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime);
1289 
                    end
1290 
            end
1291 
        end
1292 
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
1293 
            if ((($realtime - RAS_chk3 >= tRAS) &&
1294 
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
1295 
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
1296 
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
1297 
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
1298 
                 (RW_interrupt_read[3] == 1'b1)) begin
1299 
                    Pc_b3 = 1'b1;
1300 
                    Act_b3 = 1'b0;
1301 
                    RP_chk3 = $realtime;
1302 
                    Auto_precharge[3] = 1'b0;
1303 
                    Read_precharge[3] = 1'b0;
1304 
                    RW_interrupt_read[3] = 1'b0;
1305 
                    if (Debug) begin
1306 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
1307 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime);
1308 
                    end
1309 
            end
1310 
        end
1311 
 
1312 
        // CKE Function
1313 
        if (cke === 1'b0) begin
1314 
          if (Sref_enable === 1'b1) begin
1315 
            state_self = 1'b1;
1316 
            if (Debug) begin
1317 
                $display ("Time = %t : OPERATION = SREF  : Self Refresh", $realtime);
1318 
                if (EMode_reg[2:0]==3'b000) $display ("         Refresh Full Bank");
1319 
 
1320 
                if (EMode_reg[2:0]==3'b001) begin
1321 
                     $display ("                Refresh Only TWO Bank");
1322 
                     abbank_init;
1323 
                end
1324 
 
1325 
                if (EMode_reg[2:0]==3'b010) begin
1326 
                     $display ("                Refresh Only One Bank(BANK A)");
1327 
                     bbank_init;
1328 
                end
1329 
                if (EMode_reg[2:0]==3'b101) begin
1330 
                     $display ("                Refresh Only half of one Bank(BANK A, A10=0)");
1331 
                     half_init;
1332 
                end
1333 
                if (EMode_reg[2:0]==3'b110) begin
1334 
                     $display ("                Refresh Only Quarter of one Bank(BANK A, A10=0)");
1335 
                     quat_init;
1336 
                end
1337 
            end
1338 
 
1339 
            // Precharge to Auto Refresh
1340 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
1341 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
1342 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to SREF)", $realtime);
1343 
 
1344 
            // Precharge to Refresh
1345 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
1346 
                $display ("Time = %t : ERROR : All banks must be Precharged before SREF", $realtime);
1347 
 
1348 
            // Load Mode Register to Self Refresh
1349 
            if (MRD_chk < tMRD)
1350 
                $display ("Time = %t : ERROR : tMRD violation(MRS to SREF)", $realtime);
1351 
 
1352 
          end else if (Deep_pwrdn == 1'b1) begin
1353 
            state_dpdn = 1'b1;
1354 
            dpdn_check_start = 1'b1;
1355 
            Act_b0 = 0; Act_b1 = 0; Act_b2 = 0; Act_b3 = 0;
1356 
            Pc_b0 = 1; Pc_b1 = 1; Pc_b2 = 1; Pc_b3 = 1;
1357 
            mem_init;
1358 
            if (Debug) $display ("Time = %t : OPERATION = DPDN  : Deep Powerdown", $realtime);
1359 
 
1360 
            // Precharge to Auto Refresh
1361 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
1362 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
1363 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to DPDN)", $realtime);
1364 
 
1365 
            // Precharge to Refresh
1366 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
1367 
                $display ("Time = %t : ERROR : All banks must be Precharged before DPDN", $realtime);
1368 
 
1369 
          end else if (act_pwrdn == 1'b1) begin
1370 
            state_act_pwrdn = 1'b1;
1371 
            if (Debug) $display ("Time = %t : OPERATION = APDN  : Active Power down", $realtime);
1372 
          end else if (pch_pwrdn == 1'b1) begin
1373 
            state_pre_pwrdn = 1'b1;
1374 
            if (Debug) $display ("Time = %t : OPERATION = PPDN  : Precharge Power down", $realtime);
1375 
          end else if (clk_suspend_write == 1'b1) begin
1376 
            if (Debug) $display ("Time = %t : OPERATION = CKSW   : Clock Suspend during Write", $realtime);
1377 
          end else if (clk_suspend_read == 1'b1) begin
1378 
            if (Debug) $display ("Time = %t : OPERATION = CKSR   : Clock Suspend during Read", $realtime);
1379 
          end
1380 
        end
1381 
 
1382 
        // Internal Precharge or Bst
1383 
        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
1384 
            if (bank_precharge[0] == bank || A10_precharge[0] == 1'b1) begin
1385 
                if (Data_out_enable == 1'b1) begin
1386 
                    Data_out_enable = 1'b0;
1387 
                end
1388 
            end
1389 
        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
1390 
            if (Data_out_enable == 1'b1) begin
1391 
                Data_out_enable = 1'b0;
1392 
            end
1393 
        end
1394 
 
1395 
        if (Data_out_enable == 1'b0) begin
1396 
            dq_reg <= #tOH {no_of_data{1'bz}};
1397 
            Dout_Drive_Flag <= #tOH 1'b0;
1398 
        end
1399 
 
1400 
        // Detect Read or Write command
1401 
        if (Command[0] == `READ) begin
1402 
            bank = bank_addr[0];
1403 
            Col = Col_addr[0];
1404 
            Col_brst = Col_addr[0];
1405 
            case (bank_addr[0])
1406 
                2'b00 : Row = B0_row_addr;
1407 
                2'b01 : Row = B1_row_addr;
1408 
                2'b10 : Row = B2_row_addr;
1409 
                2'b11 : Row = B3_row_addr;
1410 
 
1411 
            endcase
1412 
            Burst_counter = 0;
1413 
            Data_in_enable = 1'b0;
1414 
            Data_out_enable = 1'b1;
1415 
        end else if (Command[0] == `WRITE) begin
1416 
            bank = bank_addr[0];
1417 
            Col = Col_addr[0];
1418 
            Col_brst = Col_addr[0];
1419 
            case (bank_addr[0])
1420 
                2'b00 : Row = B0_row_addr;
1421 
                2'b01 : Row = B1_row_addr;
1422 
                2'b10 : Row = B2_row_addr;
1423 
                2'b11 : Row = B3_row_addr;
1424 
            endcase
1425 
            Burst_counter = 0;
1426 
            Data_in_enable = 1'b1;
1427 
            Data_out_enable = 1'b0;
1428 
        end
1429 
 
1430 
        // DQ buffer (Driver/Receiver)
1431 
        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
1432 
            // Array buffer
1433 
            case (bank)
1434 
                2'b00 : dq_dqm = bank0 [{Row, Col}];
1435 
                2'b01 : dq_dqm = bank1 [{Row, Col}];
1436 
                2'b10 : dq_dqm = bank2 [{Row, Col}];
1437 
                2'b11 : dq_dqm = bank3 [{Row, Col}];
1438 
            endcase
1439 
 
1440 
            // dqm operation
1441 
            if (dqm[0] == 1'b0) begin
1442 
                dq_dqm [ 7 : 0] = dq [ 7 : 0 ] & dq [ 7 : 0 ];
1443 
            end
1444 
            if (dqm[1] == 1'b0) begin
1445 
                dq_dqm [15 : 8] = dq [15 : 8] & dq [15 : 8];
1446 
            end
1447 
 
1448 
 
1449 
 
1450 
            // Write to memory
1451 
            case (bank)
1452 
                2'b00 : bank0 [{Row, Col}] = dq_dqm;
1453 
                2'b01 : bank1 [{Row, Col}] = dq_dqm;
1454 
                2'b10 : bank2 [{Row, Col}] = dq_dqm;
1455 
                2'b11 : bank3 [{Row, Col}] = dq_dqm;
1456 
            endcase
1457 
 
1458 
            // Display debug message
1459 
            if (dqm !== 2'b11) begin
1460 
                // Record tWR for manual precharge
1461 
                if (bank == 2'b00) WR_chkm0 = $realtime;
1462 
                if (bank == 2'b01) WR_chkm1 = $realtime;
1463 
                if (bank == 2'b10) WR_chkm2 = $realtime;
1464 
                if (bank == 2'b11) WR_chkm3 = $realtime;
1465 
 
1466 
                if (Debug) begin
1467 
                    //$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_dqm);
1468 
                    $display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_dqm);
1469 
                end
1470 
            end else begin
1471 
                if (Debug) begin
1472 
                    //$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1473 
                    $display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1474 
                end
1475 
            end
1476 
 
1477 
            // Advance burst counter subroutine
1478 
 
1479 
                if(Cas_latency_2 == 1) begin
1480 
 
1481 
                         #tHZ2 Burst_decode;
1482 
 
1483 
                end else if(Cas_latency_3 == 1) begin
1484 
 
1485 
                         #tHZ3 Burst_decode;
1486 
 
1487 
                end
1488 
 
1489 
 
1490 
        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
1491 
            // Array buffer
1492 
            case (bank)
1493 
                2'b00 : dq_dqm = bank0[{Row, Col}];
1494 
                2'b01 : dq_dqm = bank1[{Row, Col}];
1495 
                2'b10 : dq_dqm = bank2[{Row, Col}];
1496 
                2'b11 : dq_dqm = bank3[{Row, Col}];
1497 
            endcase
1498 
 
1499 
 
1500 
            // dqm operation
1501 
            if (dqm_reg0 [0] == 1'b1) begin
1502 
                dq_dqm [ 7 : 0] = 8'bz;
1503 
            end
1504 
            if (dqm_reg0 [1] == 1'b1) begin
1505 
                dq_dqm [15 : 8] = 8'bz;
1506 
            end
1507 
 
1508 
            if(Cas_latency_2 ==1) begin
1509 
 
1510 
            // Display debug message
1511 
            if ( &(dqm_reg0) != 1'b1) begin
1512 
                dq_reg = #tAC2 dq_dqm;
1513 
                Dout_Drive_Flag = 1'b1;
1514 
                if (Debug) begin
1515 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
1516 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
1517 
                end
1518 
            end else begin
1519 
                dq_reg = #tHZ2 {no_of_data{1'bz}};
1520 
                Dout_Drive_Flag = 1'b0;
1521 
                if (Debug) begin
1522 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1523 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1524 
 
1525 
                end
1526 
            end
1527 
 
1528 
            end else if(Cas_latency_3 ==1) begin
1529 
 
1530 
            // Display debug message
1531 
            if ( &(dqm_reg0) != 1'b1) begin
1532 
                dq_reg = #tAC3 dq_dqm;
1533 
                Dout_Drive_Flag = 1'b1;
1534 
                if (Debug) begin
1535 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
1536 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
1537 
                end
1538 
            end else begin
1539 
                dq_reg = #tHZ3 {no_of_data{1'bz}};
1540 
                Dout_Drive_Flag = 1'b0;
1541 
                if (Debug) begin
1542 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1543 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1544 
 
1545 
                end
1546 
            end
1547 
 
1548 
           end
1549 
 
1550 
            // Advance burst counter subroutine
1551 
            Burst_decode;
1552 
        end
1553 
    end
1554 
 
1555 
    // Burst counter decode
1556 
    task Burst_decode;
1557 
        begin
1558 
            // Advance Burst Counter
1559 
            Burst_counter = Burst_counter + 1;
1560 
 
1561 
            // Burst Type
1562 
            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
1563 
                Col_temp = Col + 1;
1564 
            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
1565 
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
1566 
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
1567 
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
1568 
            end
1569 
 
1570 
            // Burst Length
1571 
            if (Burst_length_2) begin                                       // Burst Length = 2
1572 
                Col [0] = Col_temp [0];
1573 
            end else if (Burst_length_4) begin                              // Burst Length = 4
1574 
                Col [1 : 0] = Col_temp [1 : 0];
1575 
            end else if (Burst_length_8) begin                              // Burst Length = 8
1576 
                Col [2 : 0] = Col_temp [2 : 0];
1577 
            end else begin                                                  // Burst Length = FULL
1578 
                Col = Col_temp;
1579 
            end
1580 
 
1581 
            // Burst Read Single Write
1582 
            if (Write_burst_mode == 1'b1) begin
1583 
                Data_in_enable = 1'b0;
1584 
            end
1585 
 
1586 
            // Data Counter
1587 
            if (Burst_length_1 == 1'b1) begin
1588 
                if (Burst_counter >= 1) begin
1589 
                    Data_in_enable = 1'b0;
1590 
                    Data_out_enable = 1'b0;
1591 
                end
1592 
            end else if (Burst_length_2 == 1'b1) begin
1593 
                if (Burst_counter >= 2) begin
1594 
                    Data_in_enable = 1'b0;
1595 
                    Data_out_enable = 1'b0;
1596 
                end
1597 
            end else if (Burst_length_4 == 1'b1) begin
1598 
                if (Burst_counter >= 4) begin
1599 
                    Data_in_enable = 1'b0;
1600 
                    Data_out_enable = 1'b0;
1601 
                end
1602 
            end else if (Burst_length_8 == 1'b1) begin
1603 
                if (Burst_counter >= 8) begin
1604 
                    Data_in_enable = 1'b0;
1605 
                    Data_out_enable = 1'b0;
1606 
                end
1607 
            end
1608 
        end
1609 
    endtask
1610 
 
1611 
    task mem_init;
1612 
        begin
1613 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1614 
          begin
1615 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1616 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1617 
              bank2[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1618 
              bank3[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1619 
              //bank0[ccc]=16'b1111_1111_1111_1111;
1620 
              //bank1[ccc]=16'b1111_1111_1111_1111;
1621 
          end
1622 
        end
1623 
    endtask
1624 
 
1625 
    task abbank_init;
1626 
        begin
1627 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1628 
          begin
1629 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1630 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1631 
          end
1632 
        end
1633 
    endtask
1634 
 
1635 
 
1636 
    task bbank_init;
1637 
        begin
1638 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1639 
          begin
1640 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1641 
          end
1642 
        end
1643 
    endtask
1644 
 
1645 
    task half_init;
1646 
        begin
1647 
          bbank_init;
1648 
          for (ccc='b0100_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1649 
          begin
1650 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1651 
          end
1652 
        end
1653 
    endtask
1654 
 
1655 
    task quat_init;
1656 
        begin
1657 
          bbank_init;
1658 
          for (ccc='b0010_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1659 
          begin
1660 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1661 
          end
1662 
        end
1663 
    endtask
1664 
`endprotect
1665 
 
1666 
    // Timing Parameters
1667 
    specify
1668 
        specparam
1669 
          `ifdef S50
1670 
            tAH  =  1.0,                                        // addr, ba Hold Time
1671 
            tAS  =  1.5,                                        // addr, ba Setup Time
1672 
            tCH  =  2.5,                                        // Clock High-Level Width
1673 
            tCL  =  2.5,                                        // Clock Low-Level Width
1674 
            tCK  =  5.0,                                        // Clock Cycle Time
1675 
            tDH  =  1.0,                                        // Data-in Hold Time
1676 
            tDS  =  1.5,                                        // Data-in Setup Time
1677 
            tCKH =  1.0,                                        // CKE Hold  Time
1678 
            tCKS =  1.5,                                        // CKE Setup Time
1679 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1680 
            tCMS =  1.5;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1681 
          `endif
1682 
 
1683 
          `ifdef S60
1684 
            tAH  =  1.0,                                        // addr, ba Hold Time
1685 
            tAS  =  1.5,                                        // addr, ba Setup Time
1686 
            tCH  =  2.5,                                        // Clock High-Level Width
1687 
            tCL  =  2.5,                                        // Clock Low-Level Width
1688 
            tCK  =  6.0,                                        // Clock Cycle Time
1689 
            tDH  =  1.0,                                        // Data-in Hold Time
1690 
            tDS  =  1.5,                                        // Data-in Setup Time
1691 
            tCKH =  1.0,                                        // CKE Hold  Time
1692 
            tCKS =  1.5,                                        // CKE Setup Time
1693 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1694 
            tCMS =  1.5;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1695 
          `endif
1696 
 
1697 
          `ifdef S75
1698 
            tAH  =  1.0,                                        // addr, ba Hold Time
1699 
            tAS  =  2.0,                                        // addr, ba Setup Time
1700 
            tCH  =  2.5,                                        // Clock High-Level Width
1701 
            tCL  =  2.5,                                        // Clock Low-Level Width
1702 
            tCK  =  7.5,                                        // Clock Cycle Time
1703 
            tDH  =  1.0,                                        // Data-in Hold Time
1704 
            tDS  =  2.0,                                        // Data-in Setup Time
1705 
            tCKH =  1.0,                                        // CKE Hold  Time
1706 
            tCKS =  2.0,                                        // CKE Setup Time
1707 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1708 
            tCMS =  2.0;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1709 
          `endif
1710 
 
1711 
 
1712 
        $width    (posedge clk,           tCH);
1713 
        $width    (negedge clk,           tCL);
1714 
        $period   (negedge clk,           tCK);
1715 
        $period   (posedge clk,           tCK);
1716 
        $setuphold(posedge clk,    cke,   tCKS, tCKH);
1717 
        $setuphold(posedge clk,    csb,  tCMS, tCMH);
1718 
        $setuphold(posedge clk,    casb, tCMS, tCMH);
1719 
        $setuphold(posedge clk,    rasb, tCMS, tCMH);
1720 
        $setuphold(posedge clk,    web,  tCMS, tCMH);
1721 
        $setuphold(posedge clk,    addr,  tAS,  tAH);
1722 
        $setuphold(posedge clk,    ba,    tAS,  tAH);
1723 
        $setuphold(posedge clk,    dqm,   tCMS, tCMH);
1724 
        $setuphold(posedge dq_chk, dq,    tDS,  tDH);
1725 
    endspecify
1726 
 
1727 
 
1728 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.