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dinesha |
//////////////////////////////////////////////////////////////////////////////
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// File name : mt48lc4m32b2.v
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//////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2006 Free Model Foundry; http://www.freemodelfoundry.com
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License version 2 as
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// published by the Free Software Foundation.
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//
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// MODIFICATION HISTORY:
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//
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// version: | author: | mod date: | changes made:
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// V1.0 I.Milutinovic 06 Apr 18 Initial release
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//
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//////////////////////////////////////////////////////////////////////////////
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// PART DESCRIPTION:
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//
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// Library: RAM
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// Technology: LVTTL
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// Part: MT48LC4M32B2
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//
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// Description: 1M x 32 x 4Banks SDRAM
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//
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//////////////////////////////////////////////////////////////////////////////
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// Known Bugs:
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//
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// MODULE DECLARATION //
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1 ns/100 ps
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module mt48lc4m32b2
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(
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A11 ,
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A10 ,
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A9 ,
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A8 ,
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A7 ,
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A6 ,
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A5 ,
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A4 ,
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A3 ,
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A2 ,
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A1 ,
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A0 ,
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DQ31 ,
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DQ30 ,
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DQ29 ,
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DQ28 ,
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DQ27 ,
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DQ26 ,
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DQ25 ,
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DQ24 ,
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DQ23 ,
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DQ22 ,
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DQ21 ,
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DQ20 ,
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DQ19 ,
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DQ18 ,
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DQ17 ,
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DQ16 ,
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DQ15 ,
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DQ14 ,
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DQ13 ,
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DQ12 ,
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DQ11 ,
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DQ10 ,
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DQ9 ,
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DQ8 ,
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DQ7 ,
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DQ6 ,
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DQ5 ,
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DQ4 ,
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DQ3 ,
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DQ2 ,
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DQ1 ,
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DQ0 ,
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BA0 ,
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BA1 ,
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DQM3 ,
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DQM2 ,
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DQM1 ,
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DQM0 ,
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CLK ,
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CKE ,
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WENeg ,
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RASNeg ,
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CSNeg ,
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CASNeg );
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////////////////////////////////////////////////////////////////////////
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// Port / Part Pin Declarations
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////////////////////////////////////////////////////////////////////////
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input A11 ;
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input A10 ;
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input A9 ;
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input A8 ;
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input A7 ;
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input A6 ;
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input A5 ;
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input A4 ;
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input A3 ;
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input A2 ;
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input A1 ;
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input A0 ;
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inout DQ31 ;
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inout DQ30 ;
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inout DQ29 ;
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inout DQ28 ;
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inout DQ27 ;
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inout DQ26 ;
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inout DQ25 ;
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| 118 |
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inout DQ24 ;
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| 119 |
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inout DQ23 ;
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| 120 |
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inout DQ22 ;
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inout DQ21 ;
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inout DQ20 ;
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inout DQ19 ;
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inout DQ18 ;
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inout DQ17 ;
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inout DQ16 ;
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inout DQ15 ;
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inout DQ14 ;
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inout DQ13 ;
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inout DQ12 ;
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inout DQ11 ;
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inout DQ10 ;
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inout DQ9 ;
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inout DQ8 ;
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inout DQ7 ;
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inout DQ6 ;
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inout DQ5 ;
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inout DQ4 ;
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inout DQ3 ;
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inout DQ2 ;
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inout DQ1 ;
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inout DQ0 ;
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input BA0 ;
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input BA1 ;
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input DQM3 ;
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input DQM2 ;
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input DQM1 ;
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input DQM0 ;
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input CLK ;
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input CKE ;
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input WENeg ;
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input RASNeg ;
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input CSNeg ;
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input CASNeg ;
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// interconnect path delay signals
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wire A11_ipd ;
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wire A10_ipd ;
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wire A9_ipd ;
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wire A8_ipd ;
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wire A7_ipd ;
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wire A6_ipd ;
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wire A5_ipd ;
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wire A4_ipd ;
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wire A3_ipd ;
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wire A2_ipd ;
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wire A1_ipd ;
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wire A0_ipd ;
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wire [11 : 0] A;
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assign A = {A11_ipd,
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A10_ipd,
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A9_ipd,
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A8_ipd,
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A7_ipd,
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A6_ipd,
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A5_ipd,
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A4_ipd,
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A3_ipd,
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A2_ipd,
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A1_ipd,
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A0_ipd };
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wire DQ31_ipd ;
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wire DQ30_ipd ;
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wire DQ29_ipd ;
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wire DQ28_ipd ;
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wire DQ27_ipd ;
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wire DQ26_ipd ;
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wire DQ25_ipd ;
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wire DQ24_ipd ;
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wire DQ23_ipd ;
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wire DQ22_ipd ;
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wire DQ21_ipd ;
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wire DQ20_ipd ;
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wire DQ19_ipd ;
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wire DQ18_ipd ;
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wire DQ17_ipd ;
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wire DQ16_ipd ;
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wire DQ15_ipd ;
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wire DQ14_ipd ;
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wire DQ13_ipd ;
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wire DQ12_ipd ;
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wire DQ11_ipd ;
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wire DQ10_ipd ;
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wire DQ9_ipd ;
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wire DQ8_ipd ;
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wire DQ7_ipd ;
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wire DQ6_ipd ;
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wire DQ5_ipd ;
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wire DQ4_ipd ;
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wire DQ3_ipd ;
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wire DQ2_ipd ;
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wire DQ1_ipd ;
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wire DQ0_ipd ;
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wire [31 : 0 ] DQIn;
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assign DQIn = { DQ31_ipd,
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DQ30_ipd,
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DQ29_ipd,
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DQ28_ipd,
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DQ27_ipd,
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DQ26_ipd,
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DQ25_ipd,
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DQ24_ipd,
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DQ23_ipd,
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DQ22_ipd,
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DQ21_ipd,
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DQ20_ipd,
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DQ19_ipd,
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DQ18_ipd,
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DQ17_ipd,
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DQ16_ipd,
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DQ15_ipd,
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DQ14_ipd,
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DQ13_ipd,
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DQ12_ipd,
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DQ11_ipd,
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DQ10_ipd,
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DQ9_ipd,
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DQ8_ipd,
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DQ7_ipd,
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DQ6_ipd,
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DQ5_ipd,
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DQ4_ipd,
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DQ3_ipd,
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DQ2_ipd,
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DQ1_ipd,
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DQ0_ipd };
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wire [31 : 0] DQOut;
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assign DQOut = { DQ31,
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DQ30,
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DQ29,
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DQ28,
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DQ27,
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DQ26,
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DQ25,
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DQ24,
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DQ23,
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DQ22,
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DQ21,
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DQ20,
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DQ19,
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DQ18,
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DQ17,
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DQ16,
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DQ15,
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DQ14,
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DQ13,
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DQ12,
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DQ11,
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DQ10,
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DQ9,
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DQ8,
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DQ7,
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DQ6,
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DQ5,
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DQ4,
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DQ3,
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DQ2,
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DQ1,
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DQ0 };
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wire BA0_ipd ;
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wire BA1_ipd ;
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wire DQM3_ipd ;
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wire DQM2_ipd ;
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wire DQM1_ipd ;
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wire DQM0_ipd ;
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wire CLK_ipd ;
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wire CKE_ipd ;
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wire WENeg_ipd ;
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wire RASNeg_ipd ;
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wire CSNeg_ipd ;
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wire CASNeg_ipd ;
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integer bank;
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integer bank_tmp;
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// internal delays
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reg rct_in ;
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reg rct_out;
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reg [3:0] rcdt_in ;
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reg [3:0] rcdt_out;
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reg pre_in ;
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reg pre_out ;
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reg refreshed_in ;
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reg refreshed_out ;
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reg rcar_out ;
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reg rcar_in ;
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reg wrt_in ;
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reg wrt_out ;
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reg [3:0] ras_in = 1'b0;
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reg [3:0] ras_out = 1'b0;
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reg [31 : 0] DQ_zd = 32'bz;
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assign {DQ31_zd,
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DQ30_zd,
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DQ29_zd,
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DQ28_zd,
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DQ27_zd,
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| 324 |
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DQ26_zd,
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| 325 |
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DQ25_zd,
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| 326 |
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DQ24_zd,
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| 327 |
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DQ23_zd,
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| 328 |
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DQ22_zd,
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| 329 |
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DQ21_zd,
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| 330 |
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DQ20_zd,
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| 331 |
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DQ19_zd,
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| 332 |
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DQ18_zd,
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| 333 |
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DQ17_zd,
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| 334 |
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DQ16_zd,
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| 335 |
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DQ15_zd,
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| 336 |
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DQ14_zd,
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| 337 |
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DQ13_zd,
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| 338 |
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DQ12_zd,
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| 339 |
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DQ11_zd,
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| 340 |
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DQ10_zd,
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| 341 |
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DQ9_zd,
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| 342 |
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DQ8_zd,
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| 343 |
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DQ7_zd,
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| 344 |
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DQ6_zd,
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| 345 |
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DQ5_zd,
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| 346 |
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DQ4_zd,
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| 347 |
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DQ3_zd,
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| 348 |
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DQ2_zd,
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| 349 |
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DQ1_zd,
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| 350 |
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DQ0_zd } = DQ_zd;
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| 351 |
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| 352 |
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parameter UserPreload = 1'b1;
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| 353 |
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parameter mem_file_name = "none"; //"mt48lc4m32b2.mem";
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| 354 |
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parameter TimingModel = "DefaultTimingModel";
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| 355 |
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parameter PartID = "mt48lc4m32b2";
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| 356 |
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parameter hi_bank = 3;
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| 357 |
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parameter depth = 25'h100000;
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| 358 |
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| 359 |
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reg PoweredUp = 1'b0;
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| 360 |
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reg CKEreg = 1'b0;
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| 361 |
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reg CAS_Lat ;
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| 362 |
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reg CAS_Lat2;
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| 363 |
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reg [31:0] DataDrive = 32'bz ;
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| 364 |
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| 365 |
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// Memory array declaration
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| 366 |
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integer Mem [0:(hi_bank+1)*depth*4-1];
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| 367 |
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| 368 |
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// Type definition for state machine
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| 369 |
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parameter pwron = 5'd0;
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| 370 |
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parameter precharge = 5'd1;
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| 371 |
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parameter idle = 5'd2;
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| 372 |
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parameter mode_set = 5'd3;
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| 373 |
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parameter self_refresh = 5'd4;
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| 374 |
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parameter auto_refresh = 5'd5;
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| 375 |
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parameter pwrdwn = 5'd6;
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| 376 |
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parameter bank_act = 5'd7;
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| 377 |
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parameter bank_act_pwrdwn = 5'd8;
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| 378 |
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parameter write = 5'd9;
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| 379 |
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parameter write_suspend = 5'd10;
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| 380 |
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parameter read = 5'd11;
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| 381 |
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parameter read_suspend = 5'd12;
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| 382 |
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parameter write_auto_pre = 5'd13;
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| 383 |
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parameter read_auto_pre = 5'd14;
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| 384 |
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|
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| 385 |
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reg [4:0] statebank [hi_bank:0];
|
| 386 |
|
|
|
| 387 |
|
|
// Type definition for commands
|
| 388 |
|
|
parameter desl = 4'd0;
|
| 389 |
|
|
parameter nop = 4'd1;
|
| 390 |
|
|
parameter bst = 4'd2;
|
| 391 |
|
|
parameter rd = 4'd3;
|
| 392 |
|
|
parameter writ = 4'd4;
|
| 393 |
|
|
parameter act = 4'd5;
|
| 394 |
|
|
parameter pre = 4'd6;
|
| 395 |
|
|
parameter mrs = 4'd7;
|
| 396 |
|
|
parameter ref = 4'd8;
|
| 397 |
|
|
|
| 398 |
|
|
reg [3:0] command = desl;
|
| 399 |
|
|
|
| 400 |
|
|
// burst type
|
| 401 |
|
|
parameter sequential = 1'b0;
|
| 402 |
|
|
parameter interleave = 1'b1;
|
| 403 |
|
|
reg Burst ;
|
| 404 |
|
|
|
| 405 |
|
|
// write burst mode
|
| 406 |
|
|
parameter programmed = 1'b0;
|
| 407 |
|
|
parameter single = 1'b1;
|
| 408 |
|
|
reg WB ;
|
| 409 |
|
|
|
| 410 |
|
|
//burst sequences
|
| 411 |
|
|
integer intab [0:63];
|
| 412 |
|
|
|
| 413 |
|
|
reg [19:0] MemAddr [hi_bank:0];
|
| 414 |
|
|
integer BurstCnt [hi_bank:0];
|
| 415 |
|
|
integer StartAddr [hi_bank:0];
|
| 416 |
|
|
integer BurstInc [hi_bank:0];
|
| 417 |
|
|
integer BaseLoc [hi_bank:0];
|
| 418 |
|
|
|
| 419 |
|
|
integer Loc;
|
| 420 |
|
|
integer BurstLen;
|
| 421 |
|
|
integer Burst_Bits;
|
| 422 |
|
|
|
| 423 |
|
|
reg written = 1'b0;
|
| 424 |
|
|
reg chip_en = 1'b0;
|
| 425 |
|
|
|
| 426 |
|
|
integer cur_bank;
|
| 427 |
|
|
reg [11:0] ModeReg ;
|
| 428 |
|
|
integer Ref_Cnt = 0;
|
| 429 |
|
|
|
| 430 |
|
|
time Next_Ref = 0;
|
| 431 |
|
|
reg [8*8:1] BankString ;
|
| 432 |
|
|
|
| 433 |
|
|
reg Viol = 1'b0;
|
| 434 |
|
|
reg [31:0] DataDriveOut = 32'bz;
|
| 435 |
|
|
reg [31:0] DataDrive1 = 32'bz;
|
| 436 |
|
|
reg [31:0] DataDrive2 = 32'bz;
|
| 437 |
|
|
reg [31:0] DataDrive3 = 32'bz;
|
| 438 |
|
|
|
| 439 |
|
|
reg DQM0_reg0 ;
|
| 440 |
|
|
reg DQM0_reg1 ;
|
| 441 |
|
|
reg DQM0_reg2 ;
|
| 442 |
|
|
reg DQM1_reg0 ;
|
| 443 |
|
|
reg DQM1_reg1 ;
|
| 444 |
|
|
reg DQM1_reg2 ;
|
| 445 |
|
|
reg DQM2_reg0 ;
|
| 446 |
|
|
reg DQM2_reg1 ;
|
| 447 |
|
|
reg DQM2_reg2 ;
|
| 448 |
|
|
reg DQM3_reg0 ;
|
| 449 |
|
|
reg DQM3_reg1 ;
|
| 450 |
|
|
reg DQM3_reg2 ;
|
| 451 |
|
|
|
| 452 |
|
|
// tdevice values: values for internal delays
|
| 453 |
|
|
time tdevice_TRC = 0;
|
| 454 |
|
|
time tdevice_TRCAR = 0;
|
| 455 |
|
|
time tdevice_TRCD = 0;
|
| 456 |
|
|
time tdevice_TRP = 0;
|
| 457 |
|
|
time tdevice_TWR = 0;
|
| 458 |
|
|
|
| 459 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 460 |
|
|
//Interconnect Path Delay Section
|
| 461 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 462 |
|
|
buf (A11_ipd, A11);
|
| 463 |
|
|
buf (A10_ipd, A10);
|
| 464 |
|
|
buf (A9_ipd , A9 );
|
| 465 |
|
|
buf (A8_ipd , A8 );
|
| 466 |
|
|
buf (A7_ipd , A7 );
|
| 467 |
|
|
buf (A6_ipd , A6 );
|
| 468 |
|
|
buf (A5_ipd , A5 );
|
| 469 |
|
|
buf (A4_ipd , A4 );
|
| 470 |
|
|
buf (A3_ipd , A3 );
|
| 471 |
|
|
buf (A2_ipd , A2 );
|
| 472 |
|
|
buf (A1_ipd , A1 );
|
| 473 |
|
|
buf (A0_ipd , A0 );
|
| 474 |
|
|
|
| 475 |
|
|
buf (DQ31_ipd , DQ31 );
|
| 476 |
|
|
buf (DQ30_ipd , DQ30 );
|
| 477 |
|
|
buf (DQ29_ipd , DQ29 );
|
| 478 |
|
|
buf (DQ28_ipd , DQ28 );
|
| 479 |
|
|
buf (DQ27_ipd , DQ27 );
|
| 480 |
|
|
buf (DQ26_ipd , DQ26 );
|
| 481 |
|
|
buf (DQ25_ipd , DQ25 );
|
| 482 |
|
|
buf (DQ24_ipd , DQ24 );
|
| 483 |
|
|
buf (DQ23_ipd , DQ23 );
|
| 484 |
|
|
buf (DQ22_ipd , DQ22 );
|
| 485 |
|
|
buf (DQ21_ipd , DQ21 );
|
| 486 |
|
|
buf (DQ20_ipd , DQ20 );
|
| 487 |
|
|
buf (DQ19_ipd , DQ19 );
|
| 488 |
|
|
buf (DQ18_ipd , DQ18 );
|
| 489 |
|
|
buf (DQ17_ipd , DQ17 );
|
| 490 |
|
|
buf (DQ16_ipd , DQ16 );
|
| 491 |
|
|
buf (DQ15_ipd , DQ15 );
|
| 492 |
|
|
buf (DQ14_ipd , DQ14 );
|
| 493 |
|
|
buf (DQ13_ipd , DQ13 );
|
| 494 |
|
|
buf (DQ12_ipd , DQ12 );
|
| 495 |
|
|
buf (DQ11_ipd , DQ11 );
|
| 496 |
|
|
buf (DQ10_ipd , DQ10 );
|
| 497 |
|
|
buf (DQ9_ipd , DQ9 );
|
| 498 |
|
|
buf (DQ8_ipd , DQ8 );
|
| 499 |
|
|
buf (DQ7_ipd , DQ7 );
|
| 500 |
|
|
buf (DQ6_ipd , DQ6 );
|
| 501 |
|
|
buf (DQ5_ipd , DQ5 );
|
| 502 |
|
|
buf (DQ4_ipd , DQ4 );
|
| 503 |
|
|
buf (DQ3_ipd , DQ3 );
|
| 504 |
|
|
buf (DQ2_ipd , DQ2 );
|
| 505 |
|
|
buf (DQ1_ipd , DQ1 );
|
| 506 |
|
|
buf (DQ0_ipd , DQ0 );
|
| 507 |
|
|
|
| 508 |
|
|
buf (CASNeg_ipd, CASNeg);
|
| 509 |
|
|
buf (RASNeg_ipd, RASNeg);
|
| 510 |
|
|
buf (BA0_ipd , BA0 );
|
| 511 |
|
|
buf (BA1_ipd , BA1 );
|
| 512 |
|
|
buf (DQM0_ipd , DQM0 );
|
| 513 |
|
|
buf (DQM1_ipd , DQM1 );
|
| 514 |
|
|
buf (DQM2_ipd , DQM2 );
|
| 515 |
|
|
buf (DQM3_ipd , DQM3 );
|
| 516 |
|
|
buf (CLK_ipd , CLK );
|
| 517 |
|
|
buf (CKE_ipd , CKE );
|
| 518 |
|
|
buf (WENeg_ipd , WENeg );
|
| 519 |
|
|
buf (CSNeg_ipd , CSNeg );
|
| 520 |
|
|
|
| 521 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 522 |
|
|
// Propagation delay Section
|
| 523 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 524 |
|
|
nmos (DQ31 , DQ31_zd , 1);
|
| 525 |
|
|
nmos (DQ30 , DQ30_zd , 1);
|
| 526 |
|
|
nmos (DQ29 , DQ29_zd , 1);
|
| 527 |
|
|
nmos (DQ28 , DQ28_zd , 1);
|
| 528 |
|
|
nmos (DQ27 , DQ27_zd , 1);
|
| 529 |
|
|
nmos (DQ26 , DQ26_zd , 1);
|
| 530 |
|
|
nmos (DQ25 , DQ25_zd , 1);
|
| 531 |
|
|
nmos (DQ24 , DQ24_zd , 1);
|
| 532 |
|
|
nmos (DQ23 , DQ23_zd , 1);
|
| 533 |
|
|
nmos (DQ22 , DQ22_zd , 1);
|
| 534 |
|
|
nmos (DQ21 , DQ21_zd , 1);
|
| 535 |
|
|
nmos (DQ20 , DQ20_zd , 1);
|
| 536 |
|
|
nmos (DQ19 , DQ19_zd , 1);
|
| 537 |
|
|
nmos (DQ18 , DQ18_zd , 1);
|
| 538 |
|
|
nmos (DQ17 , DQ17_zd , 1);
|
| 539 |
|
|
nmos (DQ16 , DQ16_zd , 1);
|
| 540 |
|
|
nmos (DQ15 , DQ15_zd , 1);
|
| 541 |
|
|
nmos (DQ14 , DQ14_zd , 1);
|
| 542 |
|
|
nmos (DQ13 , DQ13_zd , 1);
|
| 543 |
|
|
nmos (DQ12 , DQ12_zd , 1);
|
| 544 |
|
|
nmos (DQ11 , DQ11_zd , 1);
|
| 545 |
|
|
nmos (DQ10 , DQ10_zd , 1);
|
| 546 |
|
|
nmos (DQ9 , DQ9_zd , 1);
|
| 547 |
|
|
nmos (DQ8 , DQ8_zd , 1);
|
| 548 |
|
|
nmos (DQ7 , DQ7_zd , 1);
|
| 549 |
|
|
nmos (DQ6 , DQ6_zd , 1);
|
| 550 |
|
|
nmos (DQ5 , DQ5_zd , 1);
|
| 551 |
|
|
nmos (DQ4 , DQ4_zd , 1);
|
| 552 |
|
|
nmos (DQ3 , DQ3_zd , 1);
|
| 553 |
|
|
nmos (DQ2 , DQ2_zd , 1);
|
| 554 |
|
|
nmos (DQ1 , DQ1_zd , 1);
|
| 555 |
|
|
nmos (DQ0 , DQ0_zd , 1);
|
| 556 |
|
|
|
| 557 |
|
|
wire deg;
|
| 558 |
|
|
wire chip_act;
|
| 559 |
|
|
assign chip_act = chip_en;
|
| 560 |
|
|
|
| 561 |
|
|
wire chip_act_deg;
|
| 562 |
|
|
assign chip_act_deg = chip_act && deg;
|
| 563 |
|
|
|
| 564 |
|
|
wire cas_latency1;
|
| 565 |
|
|
wire cas_latency2;
|
| 566 |
|
|
wire cas_latency3;
|
| 567 |
|
|
|
| 568 |
|
|
assign cas_latency1 = CAS_Lat && ~CAS_Lat2;
|
| 569 |
|
|
assign cas_latency2 = ~CAS_Lat && CAS_Lat2;
|
| 570 |
|
|
assign cas_latency3 = CAS_Lat && CAS_Lat2;
|
| 571 |
|
|
|
| 572 |
|
|
specify
|
| 573 |
|
|
// tipd delays: interconnect path delays, mapped to input port delays.
|
| 574 |
|
|
// In Verilog it is not necessary to declare any tipd delay variables,
|
| 575 |
|
|
// they can be taken from SDF file
|
| 576 |
|
|
// With all the other delays real delays would be taken from SDF file
|
| 577 |
|
|
|
| 578 |
|
|
// tpd delays
|
| 579 |
|
|
specparam tpd_CLK_DQ1 = 1;
|
| 580 |
|
|
specparam tpd_CLK_DQ2 = 1;
|
| 581 |
|
|
specparam tpd_CLK_DQ3 = 1;
|
| 582 |
|
|
|
| 583 |
|
|
// tpw values: pulse widths
|
| 584 |
|
|
specparam tpw_CLK_posedge = 1;
|
| 585 |
|
|
specparam tpw_CLK_negedge = 1;
|
| 586 |
|
|
|
| 587 |
|
|
// tsetup values: setup times
|
| 588 |
|
|
specparam tsetup_DQ0_CLK = 1; // tDS
|
| 589 |
|
|
|
| 590 |
|
|
// thold values: hold times
|
| 591 |
|
|
specparam thold_DQ0_CLK = 1; // tDH
|
| 592 |
|
|
|
| 593 |
|
|
// tperiod_min: minimum clock period = 1/max freq
|
| 594 |
|
|
specparam tperiod_CLK_cl0_eq_1_posedge = 1; //tCK
|
| 595 |
|
|
specparam tperiod_CLK_cl1_eq_1_posedge = 1;
|
| 596 |
|
|
specparam tperiod_CLK_cl2_eq_1_posedge = 1;
|
| 597 |
|
|
|
| 598 |
|
|
// tdevice values: values for internal delays
|
| 599 |
|
|
specparam tdevice_REF = 15625 ;
|
| 600 |
|
|
specparam tdevice_TRASmin = 42;
|
| 601 |
|
|
specparam tdevice_TRASmax = 120000;
|
| 602 |
|
|
|
| 603 |
|
|
///////////////////////////////////////////////////////////////////////
|
| 604 |
|
|
// Input Port Delays don't require Verilog description
|
| 605 |
|
|
///////////////////////////////////////////////////////////////////////
|
| 606 |
|
|
// Path delays //
|
| 607 |
|
|
///////////////////////////////////////////////////////////////////////
|
| 608 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ0) = tpd_CLK_DQ1;
|
| 609 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ1) = tpd_CLK_DQ1;
|
| 610 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ2) = tpd_CLK_DQ1;
|
| 611 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ3) = tpd_CLK_DQ1;
|
| 612 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ4) = tpd_CLK_DQ1;
|
| 613 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ5) = tpd_CLK_DQ1;
|
| 614 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ6) = tpd_CLK_DQ1;
|
| 615 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ7) = tpd_CLK_DQ1;
|
| 616 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ8) = tpd_CLK_DQ1;
|
| 617 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ9) = tpd_CLK_DQ1;
|
| 618 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ10) = tpd_CLK_DQ1;
|
| 619 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ11) = tpd_CLK_DQ1;
|
| 620 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ12) = tpd_CLK_DQ1;
|
| 621 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ13) = tpd_CLK_DQ1;
|
| 622 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ14) = tpd_CLK_DQ1;
|
| 623 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ15) = tpd_CLK_DQ1;
|
| 624 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ16) = tpd_CLK_DQ1;
|
| 625 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ17) = tpd_CLK_DQ1;
|
| 626 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ18) = tpd_CLK_DQ1;
|
| 627 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ19) = tpd_CLK_DQ1;
|
| 628 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ20) = tpd_CLK_DQ1;
|
| 629 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ21) = tpd_CLK_DQ1;
|
| 630 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ22) = tpd_CLK_DQ1;
|
| 631 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ23) = tpd_CLK_DQ1;
|
| 632 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ24) = tpd_CLK_DQ1;
|
| 633 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ25) = tpd_CLK_DQ1;
|
| 634 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ26) = tpd_CLK_DQ1;
|
| 635 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ27) = tpd_CLK_DQ1;
|
| 636 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ28) = tpd_CLK_DQ1;
|
| 637 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ29) = tpd_CLK_DQ1;
|
| 638 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ30) = tpd_CLK_DQ1;
|
| 639 |
|
|
if (CAS_Lat && ~CAS_Lat2) (CLK *> DQ31) = tpd_CLK_DQ1;
|
| 640 |
|
|
|
| 641 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ0) = tpd_CLK_DQ2;
|
| 642 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ1) = tpd_CLK_DQ2;
|
| 643 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ2) = tpd_CLK_DQ2;
|
| 644 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ3) = tpd_CLK_DQ2;
|
| 645 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ4) = tpd_CLK_DQ2;
|
| 646 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ5) = tpd_CLK_DQ2;
|
| 647 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ6) = tpd_CLK_DQ2;
|
| 648 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ7) = tpd_CLK_DQ2;
|
| 649 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ8) = tpd_CLK_DQ2;
|
| 650 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ9) = tpd_CLK_DQ2;
|
| 651 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ10) = tpd_CLK_DQ2;
|
| 652 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ11) = tpd_CLK_DQ2;
|
| 653 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ12) = tpd_CLK_DQ2;
|
| 654 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ13) = tpd_CLK_DQ2;
|
| 655 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ14) = tpd_CLK_DQ2;
|
| 656 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ15) = tpd_CLK_DQ2;
|
| 657 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ16) = tpd_CLK_DQ2;
|
| 658 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ17) = tpd_CLK_DQ2;
|
| 659 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ18) = tpd_CLK_DQ2;
|
| 660 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ19) = tpd_CLK_DQ2;
|
| 661 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ20) = tpd_CLK_DQ2;
|
| 662 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ21) = tpd_CLK_DQ2;
|
| 663 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ22) = tpd_CLK_DQ2;
|
| 664 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ23) = tpd_CLK_DQ2;
|
| 665 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ24) = tpd_CLK_DQ2;
|
| 666 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ25) = tpd_CLK_DQ2;
|
| 667 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ26) = tpd_CLK_DQ2;
|
| 668 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ27) = tpd_CLK_DQ2;
|
| 669 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ28) = tpd_CLK_DQ2;
|
| 670 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ29) = tpd_CLK_DQ2;
|
| 671 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ30) = tpd_CLK_DQ2;
|
| 672 |
|
|
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ31) = tpd_CLK_DQ2;
|
| 673 |
|
|
|
| 674 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ0) = tpd_CLK_DQ3;
|
| 675 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ1) = tpd_CLK_DQ3;
|
| 676 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ2) = tpd_CLK_DQ3;
|
| 677 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ3) = tpd_CLK_DQ3;
|
| 678 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ4) = tpd_CLK_DQ3;
|
| 679 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ5) = tpd_CLK_DQ3;
|
| 680 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ6) = tpd_CLK_DQ3;
|
| 681 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ7) = tpd_CLK_DQ3;
|
| 682 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ8) = tpd_CLK_DQ3;
|
| 683 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ9) = tpd_CLK_DQ3;
|
| 684 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ10) = tpd_CLK_DQ3;
|
| 685 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ11) = tpd_CLK_DQ3;
|
| 686 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ12) = tpd_CLK_DQ3;
|
| 687 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ13) = tpd_CLK_DQ3;
|
| 688 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ14) = tpd_CLK_DQ3;
|
| 689 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ15) = tpd_CLK_DQ3;
|
| 690 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ16) = tpd_CLK_DQ3;
|
| 691 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ17) = tpd_CLK_DQ3;
|
| 692 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ18) = tpd_CLK_DQ3;
|
| 693 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ19) = tpd_CLK_DQ3;
|
| 694 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ20) = tpd_CLK_DQ3;
|
| 695 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ21) = tpd_CLK_DQ3;
|
| 696 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ22) = tpd_CLK_DQ3;
|
| 697 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ23) = tpd_CLK_DQ3;
|
| 698 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ24) = tpd_CLK_DQ3;
|
| 699 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ25) = tpd_CLK_DQ3;
|
| 700 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ26) = tpd_CLK_DQ3;
|
| 701 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ27) = tpd_CLK_DQ3;
|
| 702 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ28) = tpd_CLK_DQ3;
|
| 703 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ29) = tpd_CLK_DQ3;
|
| 704 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ30) = tpd_CLK_DQ3;
|
| 705 |
|
|
if (CAS_Lat && CAS_Lat2) (CLK *> DQ31) = tpd_CLK_DQ3;
|
| 706 |
|
|
|
| 707 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 708 |
|
|
// Timing Check Section
|
| 709 |
|
|
////////////////////////////////////////////////////////////////////////
|
| 710 |
|
|
$setup (BA0 , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 711 |
|
|
$setup (BA1 , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 712 |
|
|
$setup (DQM0, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 713 |
|
|
$setup (DQM1, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 714 |
|
|
$setup (DQM2, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 715 |
|
|
$setup (DQM3, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 716 |
|
|
$setup (CKE , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 717 |
|
|
$setup (WENeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 718 |
|
|
$setup (CSNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 719 |
|
|
$setup (CASNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 720 |
|
|
$setup (RASNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 721 |
|
|
|
| 722 |
|
|
$setup (DQ0 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 723 |
|
|
$setup (DQ1 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 724 |
|
|
$setup (DQ2 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 725 |
|
|
$setup (DQ3 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 726 |
|
|
$setup (DQ4 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 727 |
|
|
$setup (DQ5 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 728 |
|
|
$setup (DQ6 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 729 |
|
|
$setup (DQ7 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 730 |
|
|
$setup (DQ8 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 731 |
|
|
$setup (DQ9 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 732 |
|
|
$setup (DQ10 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 733 |
|
|
$setup (DQ11 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 734 |
|
|
$setup (DQ12 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 735 |
|
|
$setup (DQ13 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 736 |
|
|
$setup (DQ14 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 737 |
|
|
$setup (DQ15 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 738 |
|
|
$setup (DQ16 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 739 |
|
|
$setup (DQ17 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 740 |
|
|
$setup (DQ18 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 741 |
|
|
$setup (DQ19 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 742 |
|
|
$setup (DQ20 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 743 |
|
|
$setup (DQ21 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 744 |
|
|
$setup (DQ22 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 745 |
|
|
$setup (DQ23 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 746 |
|
|
$setup (DQ24 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 747 |
|
|
$setup (DQ25 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 748 |
|
|
$setup (DQ26 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 749 |
|
|
$setup (DQ27 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 750 |
|
|
$setup (DQ28 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 751 |
|
|
$setup (DQ29 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 752 |
|
|
$setup (DQ30 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 753 |
|
|
$setup (DQ31 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
|
| 754 |
|
|
|
| 755 |
|
|
$setup (A0, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 756 |
|
|
$setup (A1, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 757 |
|
|
$setup (A2, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 758 |
|
|
$setup (A3, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 759 |
|
|
$setup (A4, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 760 |
|
|
$setup (A5, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 761 |
|
|
$setup (A6, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 762 |
|
|
$setup (A7, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 763 |
|
|
$setup (A8, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 764 |
|
|
$setup (A9, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 765 |
|
|
$setup (A10, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 766 |
|
|
$setup (A11, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
|
| 767 |
|
|
|
| 768 |
|
|
$hold (posedge CLK &&& chip_act, BA0, thold_DQ0_CLK, Viol);
|
| 769 |
|
|
$hold (posedge CLK &&& chip_act, BA1, thold_DQ0_CLK, Viol);
|
| 770 |
|
|
$hold (posedge CLK &&& chip_act, DQM0, thold_DQ0_CLK, Viol);
|
| 771 |
|
|
$hold (posedge CLK &&& chip_act, DQM1, thold_DQ0_CLK, Viol);
|
| 772 |
|
|
$hold (posedge CLK &&& chip_act, DQM2, thold_DQ0_CLK, Viol);
|
| 773 |
|
|
$hold (posedge CLK &&& chip_act, DQM3, thold_DQ0_CLK, Viol);
|
| 774 |
|
|
$hold (posedge CLK &&& chip_act, CKE , thold_DQ0_CLK, Viol);
|
| 775 |
|
|
$hold (posedge CLK &&& chip_act, CASNeg, thold_DQ0_CLK, Viol);
|
| 776 |
|
|
$hold (posedge CLK &&& chip_act, RASNeg, thold_DQ0_CLK, Viol);
|
| 777 |
|
|
$hold (posedge CLK &&& chip_act, WENeg, thold_DQ0_CLK, Viol);
|
| 778 |
|
|
$hold (posedge CLK &&& chip_act, CSNeg, thold_DQ0_CLK, Viol);
|
| 779 |
|
|
|
| 780 |
|
|
$hold (posedge CLK &&& chip_act, A0, thold_DQ0_CLK, Viol);
|
| 781 |
|
|
$hold (posedge CLK &&& chip_act, A1, thold_DQ0_CLK, Viol);
|
| 782 |
|
|
$hold (posedge CLK &&& chip_act, A2, thold_DQ0_CLK, Viol);
|
| 783 |
|
|
$hold (posedge CLK &&& chip_act, A3, thold_DQ0_CLK, Viol);
|
| 784 |
|
|
$hold (posedge CLK &&& chip_act, A4, thold_DQ0_CLK, Viol);
|
| 785 |
|
|
$hold (posedge CLK &&& chip_act, A5, thold_DQ0_CLK, Viol);
|
| 786 |
|
|
$hold (posedge CLK &&& chip_act, A6, thold_DQ0_CLK, Viol);
|
| 787 |
|
|
$hold (posedge CLK &&& chip_act, A7, thold_DQ0_CLK, Viol);
|
| 788 |
|
|
$hold (posedge CLK &&& chip_act, A8, thold_DQ0_CLK, Viol);
|
| 789 |
|
|
$hold (posedge CLK &&& chip_act, A9, thold_DQ0_CLK, Viol);
|
| 790 |
|
|
$hold (posedge CLK &&& chip_act, A10, thold_DQ0_CLK, Viol);
|
| 791 |
|
|
$hold (posedge CLK &&& chip_act, A11, thold_DQ0_CLK, Viol);
|
| 792 |
|
|
|
| 793 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ0, thold_DQ0_CLK, Viol);
|
| 794 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ1, thold_DQ0_CLK, Viol);
|
| 795 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ2, thold_DQ0_CLK, Viol);
|
| 796 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ3, thold_DQ0_CLK, Viol);
|
| 797 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ4, thold_DQ0_CLK, Viol);
|
| 798 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ5, thold_DQ0_CLK, Viol);
|
| 799 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ6, thold_DQ0_CLK, Viol);
|
| 800 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ7, thold_DQ0_CLK, Viol);
|
| 801 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ8, thold_DQ0_CLK, Viol);
|
| 802 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ9, thold_DQ0_CLK, Viol);
|
| 803 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ10, thold_DQ0_CLK, Viol);
|
| 804 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ11, thold_DQ0_CLK, Viol);
|
| 805 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ12, thold_DQ0_CLK, Viol);
|
| 806 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ13, thold_DQ0_CLK, Viol);
|
| 807 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ14, thold_DQ0_CLK, Viol);
|
| 808 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ15, thold_DQ0_CLK, Viol);
|
| 809 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ16, thold_DQ0_CLK, Viol);
|
| 810 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ17, thold_DQ0_CLK, Viol);
|
| 811 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ18, thold_DQ0_CLK, Viol);
|
| 812 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ19, thold_DQ0_CLK, Viol);
|
| 813 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ20, thold_DQ0_CLK, Viol);
|
| 814 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ21, thold_DQ0_CLK, Viol);
|
| 815 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ22, thold_DQ0_CLK, Viol);
|
| 816 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ23, thold_DQ0_CLK, Viol);
|
| 817 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ24, thold_DQ0_CLK, Viol);
|
| 818 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ25, thold_DQ0_CLK, Viol);
|
| 819 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ26, thold_DQ0_CLK, Viol);
|
| 820 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ27, thold_DQ0_CLK, Viol);
|
| 821 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ28, thold_DQ0_CLK, Viol);
|
| 822 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ29, thold_DQ0_CLK, Viol);
|
| 823 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ30, thold_DQ0_CLK, Viol);
|
| 824 |
|
|
$hold (posedge CLK &&& chip_act_deg, DQ31, thold_DQ0_CLK, Viol);
|
| 825 |
|
|
|
| 826 |
|
|
$width (posedge CLK &&& chip_act, tpw_CLK_posedge);
|
| 827 |
|
|
$width (negedge CLK &&& chip_act, tpw_CLK_negedge);
|
| 828 |
|
|
|
| 829 |
|
|
$period (posedge CLK &&& cas_latency1, tperiod_CLK_cl0_eq_1_posedge);
|
| 830 |
|
|
$period (posedge CLK &&& cas_latency2, tperiod_CLK_cl1_eq_1_posedge);
|
| 831 |
|
|
$period (posedge CLK &&& cas_latency3, tperiod_CLK_cl2_eq_1_posedge);
|
| 832 |
|
|
|
| 833 |
|
|
endspecify
|
| 834 |
|
|
|
| 835 |
|
|
task generate_out ;
|
| 836 |
|
|
output [31:0] DataDrive;
|
| 837 |
|
|
input Bank;
|
| 838 |
|
|
integer Bank;
|
| 839 |
|
|
integer location;
|
| 840 |
|
|
begin
|
| 841 |
|
|
location = Bank * depth * 4 + Loc;
|
| 842 |
|
|
|
| 843 |
|
|
DataDrive[7:0] = 8'bx;
|
| 844 |
|
|
if (Mem[location] > -1)
|
| 845 |
|
|
DataDrive[7:0] = Mem[location];
|
| 846 |
|
|
|
| 847 |
|
|
DataDrive[15:8] = 8'bx;
|
| 848 |
|
|
if (Mem[location+1] > -1)
|
| 849 |
|
|
DataDrive[15:8] = Mem[location+1];
|
| 850 |
|
|
|
| 851 |
|
|
DataDrive[23:16] = 8'bx;
|
| 852 |
|
|
if (Mem[location+2] > -1)
|
| 853 |
|
|
DataDrive[23:16] = Mem[location+2];
|
| 854 |
|
|
|
| 855 |
|
|
DataDrive[31:24] = 8'bx;
|
| 856 |
|
|
if (Mem[location+3] > -1)
|
| 857 |
|
|
DataDrive[31:24] = Mem[location+3];
|
| 858 |
|
|
end
|
| 859 |
|
|
endtask
|
| 860 |
|
|
|
| 861 |
|
|
task MemWrite;
|
| 862 |
|
|
input Bank;
|
| 863 |
|
|
integer Bank;
|
| 864 |
|
|
integer location;
|
| 865 |
|
|
begin
|
| 866 |
|
|
location = Bank * depth * 4 + Loc;
|
| 867 |
|
|
|
| 868 |
|
|
if (~DQM0_ipd)
|
| 869 |
|
|
begin
|
| 870 |
|
|
Mem[location] = -1;
|
| 871 |
|
|
if (~Viol)
|
| 872 |
|
|
Mem[location] = DQIn[7:0];
|
| 873 |
|
|
end
|
| 874 |
|
|
|
| 875 |
|
|
if (~DQM1_ipd)
|
| 876 |
|
|
begin
|
| 877 |
|
|
Mem[location+1] = -1;
|
| 878 |
|
|
if (~Viol)
|
| 879 |
|
|
Mem[location+1] = DQIn[15:8];
|
| 880 |
|
|
end
|
| 881 |
|
|
|
| 882 |
|
|
if (~DQM2_ipd)
|
| 883 |
|
|
begin
|
| 884 |
|
|
Mem[location+2] = -1;
|
| 885 |
|
|
if (~Viol)
|
| 886 |
|
|
Mem[location+2] = DQIn[23:16];
|
| 887 |
|
|
end
|
| 888 |
|
|
|
| 889 |
|
|
if (~DQM3_ipd)
|
| 890 |
|
|
begin
|
| 891 |
|
|
Mem[location+3] = -1;
|
| 892 |
|
|
if (~Viol)
|
| 893 |
|
|
Mem[location+3] = DQIn[31:24];
|
| 894 |
|
|
end
|
| 895 |
|
|
end
|
| 896 |
|
|
endtask
|
| 897 |
|
|
|
| 898 |
|
|
task BurstIncProc;
|
| 899 |
|
|
input Bank;
|
| 900 |
|
|
integer Bank;
|
| 901 |
|
|
begin
|
| 902 |
|
|
BurstInc[Bank] = 0;
|
| 903 |
|
|
if (Burst_Bits == 1)
|
| 904 |
|
|
BurstInc[Bank] = A[0:0];
|
| 905 |
|
|
if (Burst_Bits == 2)
|
| 906 |
|
|
BurstInc[Bank] = A[1:0];
|
| 907 |
|
|
if (Burst_Bits == 3)
|
| 908 |
|
|
BurstInc[Bank] = A[2:0];
|
| 909 |
|
|
if (Burst_Bits == 7)
|
| 910 |
|
|
BurstInc[Bank] = A[6:0];
|
| 911 |
|
|
end
|
| 912 |
|
|
endtask
|
| 913 |
|
|
|
| 914 |
|
|
task NextStateAuto;
|
| 915 |
|
|
input Bank;
|
| 916 |
|
|
input state;
|
| 917 |
|
|
integer Bank;
|
| 918 |
|
|
reg [4:0] state;
|
| 919 |
|
|
begin
|
| 920 |
|
|
if (~A[10])
|
| 921 |
|
|
statebank[Bank] = state;
|
| 922 |
|
|
else if (A[10])
|
| 923 |
|
|
if (state == write)
|
| 924 |
|
|
statebank[Bank] = write_auto_pre;
|
| 925 |
|
|
else
|
| 926 |
|
|
statebank[Bank] = read_auto_pre;
|
| 927 |
|
|
end
|
| 928 |
|
|
endtask
|
| 929 |
|
|
|
| 930 |
|
|
//////////////////////////////////////////////////////////////////////////
|
| 931 |
|
|
// Main Behavior Block //
|
| 932 |
|
|
//////////////////////////////////////////////////////////////////////////
|
| 933 |
|
|
|
| 934 |
|
|
// chech when data is generated from model to avoid setup/hold check in
|
| 935 |
|
|
// those occasion
|
| 936 |
|
|
reg deq;
|
| 937 |
|
|
always @(DQIn, DQOut)
|
| 938 |
|
|
begin
|
| 939 |
|
|
if (DQIn==DQOut)
|
| 940 |
|
|
deq=1'b1;
|
| 941 |
|
|
else
|
| 942 |
|
|
deq=1'b0;
|
| 943 |
|
|
end
|
| 944 |
|
|
assign deg=deq;
|
| 945 |
|
|
|
| 946 |
|
|
// initialize burst sequences
|
| 947 |
|
|
initial
|
| 948 |
|
|
begin
|
| 949 |
|
|
intab[0] = 0;
|
| 950 |
|
|
intab[1] = 1;
|
| 951 |
|
|
intab[2] = 2;
|
| 952 |
|
|
intab[3] = 3;
|
| 953 |
|
|
intab[4] = 4;
|
| 954 |
|
|
intab[5] = 5;
|
| 955 |
|
|
intab[6] = 6;
|
| 956 |
|
|
intab[7] = 7;
|
| 957 |
|
|
intab[8] = 1;
|
| 958 |
|
|
intab[9] = 0;
|
| 959 |
|
|
intab[10] = 3;
|
| 960 |
|
|
intab[11] = 2;
|
| 961 |
|
|
intab[12] = 5;
|
| 962 |
|
|
intab[13] = 4;
|
| 963 |
|
|
intab[14] = 7;
|
| 964 |
|
|
intab[15] = 6;
|
| 965 |
|
|
intab[16] = 2;
|
| 966 |
|
|
intab[17] = 3;
|
| 967 |
|
|
intab[18] = 0;
|
| 968 |
|
|
intab[19] = 1;
|
| 969 |
|
|
intab[20] = 6;
|
| 970 |
|
|
intab[21] = 7;
|
| 971 |
|
|
intab[22] = 4;
|
| 972 |
|
|
intab[23] = 5;
|
| 973 |
|
|
intab[24] = 3;
|
| 974 |
|
|
intab[25] = 2;
|
| 975 |
|
|
intab[26] = 1;
|
| 976 |
|
|
intab[27] = 0;
|
| 977 |
|
|
intab[28] = 7;
|
| 978 |
|
|
intab[29] = 6;
|
| 979 |
|
|
intab[30] = 5;
|
| 980 |
|
|
intab[31] = 4;
|
| 981 |
|
|
intab[32] = 4;
|
| 982 |
|
|
intab[33] = 5;
|
| 983 |
|
|
intab[34] = 6;
|
| 984 |
|
|
intab[35] = 7;
|
| 985 |
|
|
intab[36] = 0;
|
| 986 |
|
|
intab[37] = 1;
|
| 987 |
|
|
intab[38] = 2;
|
| 988 |
|
|
intab[39] = 3;
|
| 989 |
|
|
intab[40] = 5;
|
| 990 |
|
|
intab[41] = 4;
|
| 991 |
|
|
intab[42] = 7;
|
| 992 |
|
|
intab[43] = 6;
|
| 993 |
|
|
intab[44] = 1;
|
| 994 |
|
|
intab[45] = 0;
|
| 995 |
|
|
intab[46] = 3;
|
| 996 |
|
|
intab[47] = 2;
|
| 997 |
|
|
intab[48] = 6;
|
| 998 |
|
|
intab[49] = 7;
|
| 999 |
|
|
intab[50] = 4;
|
| 1000 |
|
|
intab[51] = 5;
|
| 1001 |
|
|
intab[52] = 2;
|
| 1002 |
|
|
intab[53] = 3;
|
| 1003 |
|
|
intab[54] = 0;
|
| 1004 |
|
|
intab[55] = 1;
|
| 1005 |
|
|
intab[56] = 7;
|
| 1006 |
|
|
intab[57] = 6;
|
| 1007 |
|
|
intab[58] = 5;
|
| 1008 |
|
|
intab[59] = 4;
|
| 1009 |
|
|
intab[60] = 3;
|
| 1010 |
|
|
intab[61] = 2;
|
| 1011 |
|
|
intab[62] = 1;
|
| 1012 |
|
|
intab[63] = 0;
|
| 1013 |
|
|
end
|
| 1014 |
|
|
|
| 1015 |
|
|
// initialize memory and load preload files if any
|
| 1016 |
|
|
initial
|
| 1017 |
|
|
begin: InitMemory
|
| 1018 |
|
|
integer i;
|
| 1019 |
|
|
for (i=0; i<=((hi_bank+1)*depth*4 - 1); i=i+1)
|
| 1020 |
|
|
begin
|
| 1021 |
|
|
Mem[i] = -1;
|
| 1022 |
|
|
end
|
| 1023 |
|
|
// Memory preload file
|
| 1024 |
|
|
// mt48lc4m32b2.mem file
|
| 1025 |
|
|
// @bbbbbb - <bbbbbb> stands for address within memory,
|
| 1026 |
|
|
// dd - <dd> is word to be written at Mem(bbbbbb++)
|
| 1027 |
|
|
// (bbbbbb is incremented at every load)
|
| 1028 |
|
|
if (UserPreload && !(mem_file_name == "none"))
|
| 1029 |
|
|
$readmemh(mem_file_name,Mem);
|
| 1030 |
|
|
end
|
| 1031 |
|
|
|
| 1032 |
|
|
//Power Up time 100 us;
|
| 1033 |
|
|
initial
|
| 1034 |
|
|
begin
|
| 1035 |
|
|
PoweredUp = 1'b0;
|
| 1036 |
|
|
statebank[0] = pwron;
|
| 1037 |
|
|
statebank[1] = pwron;
|
| 1038 |
|
|
statebank[2] = pwron;
|
| 1039 |
|
|
statebank[3] = pwron;
|
| 1040 |
|
|
#100000 PoweredUp = 1'b1;
|
| 1041 |
|
|
end
|
| 1042 |
|
|
|
| 1043 |
|
|
always @(posedge wrt_in)
|
| 1044 |
|
|
begin:TWRrise
|
| 1045 |
|
|
#tdevice_TWR wrt_out = wrt_in;
|
| 1046 |
|
|
end
|
| 1047 |
|
|
|
| 1048 |
|
|
always @(negedge wrt_in)
|
| 1049 |
|
|
begin:TWRfall
|
| 1050 |
|
|
#1 wrt_out = wrt_in;
|
| 1051 |
|
|
end
|
| 1052 |
|
|
|
| 1053 |
|
|
always @(posedge ras_in[0])
|
| 1054 |
|
|
begin:TRASrise0
|
| 1055 |
|
|
ras_out[0] <= #tdevice_TRASmin ras_in[0];
|
| 1056 |
|
|
end
|
| 1057 |
|
|
|
| 1058 |
|
|
always @(negedge ras_in[0])
|
| 1059 |
|
|
begin:TRASfall0
|
| 1060 |
|
|
ras_out[0] <= #tdevice_TRASmax ras_in[0];
|
| 1061 |
|
|
end
|
| 1062 |
|
|
|
| 1063 |
|
|
always @(posedge ras_in[1])
|
| 1064 |
|
|
begin:TRASrise1
|
| 1065 |
|
|
ras_out[1] <= #tdevice_TRASmin ras_in[1];
|
| 1066 |
|
|
end
|
| 1067 |
|
|
|
| 1068 |
|
|
always @(negedge ras_in[1])
|
| 1069 |
|
|
begin:TRASfall1
|
| 1070 |
|
|
ras_out[1] <= #tdevice_TRASmax ras_in[1];
|
| 1071 |
|
|
end
|
| 1072 |
|
|
|
| 1073 |
|
|
always @(posedge ras_in[2])
|
| 1074 |
|
|
begin:TRASrise2
|
| 1075 |
|
|
ras_out[2] <= #tdevice_TRASmin ras_in[2];
|
| 1076 |
|
|
end
|
| 1077 |
|
|
always @(negedge ras_in[2])
|
| 1078 |
|
|
begin:TRASfall2
|
| 1079 |
|
|
ras_out[2] <= #tdevice_TRASmax ras_in[2];
|
| 1080 |
|
|
end
|
| 1081 |
|
|
|
| 1082 |
|
|
always @(posedge ras_in[3])
|
| 1083 |
|
|
begin:TRASrise3
|
| 1084 |
|
|
ras_out[3] <= #tdevice_TRASmin ras_in[3];
|
| 1085 |
|
|
end
|
| 1086 |
|
|
|
| 1087 |
|
|
always @(negedge ras_in[3])
|
| 1088 |
|
|
begin:TRASfall3
|
| 1089 |
|
|
ras_out[3] <= #tdevice_TRASmax ras_in[3];
|
| 1090 |
|
|
end
|
| 1091 |
|
|
|
| 1092 |
|
|
always @(posedge rcdt_in[0])
|
| 1093 |
|
|
begin:TRCDrise0
|
| 1094 |
|
|
rcdt_out[0] <= #5 1'b1;
|
| 1095 |
|
|
end
|
| 1096 |
|
|
always @(negedge rcdt_in[0])
|
| 1097 |
|
|
begin:TRCDfall0
|
| 1098 |
|
|
rcdt_out[0] <= #tdevice_TRCD 1'b0;
|
| 1099 |
|
|
end
|
| 1100 |
|
|
|
| 1101 |
|
|
always @(posedge rcdt_in[1])
|
| 1102 |
|
|
begin:TRCDrise1
|
| 1103 |
|
|
rcdt_out[1] <= #5 1'b1;
|
| 1104 |
|
|
end
|
| 1105 |
|
|
always @(negedge rcdt_in[1])
|
| 1106 |
|
|
begin:TRCDfall1
|
| 1107 |
|
|
rcdt_out[1] <= #tdevice_TRCD 1'b0;
|
| 1108 |
|
|
end
|
| 1109 |
|
|
|
| 1110 |
|
|
always @(posedge rcdt_in[2])
|
| 1111 |
|
|
begin:TRCDrise2
|
| 1112 |
|
|
rcdt_out[2] <= #5 1'b1;
|
| 1113 |
|
|
end
|
| 1114 |
|
|
always @(negedge rcdt_in[2])
|
| 1115 |
|
|
begin:TRCDfall2
|
| 1116 |
|
|
rcdt_out[2] <= #tdevice_TRCD 1'b0;
|
| 1117 |
|
|
end
|
| 1118 |
|
|
|
| 1119 |
|
|
always @(posedge rcdt_in[3])
|
| 1120 |
|
|
begin:TRCDrise3
|
| 1121 |
|
|
rcdt_out[3] <= #5 1'b1;
|
| 1122 |
|
|
end
|
| 1123 |
|
|
always @(negedge rcdt_in[3])
|
| 1124 |
|
|
begin:TRCDfall3
|
| 1125 |
|
|
rcdt_out[3] <= #tdevice_TRCD 1'b0;
|
| 1126 |
|
|
end
|
| 1127 |
|
|
|
| 1128 |
|
|
/////////////////////////////////////////////////////////////////////////
|
| 1129 |
|
|
// Functional Section
|
| 1130 |
|
|
/////////////////////////////////////////////////////////////////////////
|
| 1131 |
|
|
always @(posedge CLK)
|
| 1132 |
|
|
begin
|
| 1133 |
|
|
if ($time > Next_Ref && PoweredUp && Ref_Cnt > 0)
|
| 1134 |
|
|
begin
|
| 1135 |
|
|
Ref_Cnt = Ref_Cnt - 1;
|
| 1136 |
|
|
Next_Ref = $time + tdevice_REF;
|
| 1137 |
|
|
end
|
| 1138 |
|
|
if (CKEreg)
|
| 1139 |
|
|
begin
|
| 1140 |
|
|
if (~CSNeg_ipd)
|
| 1141 |
|
|
chip_en = 1;
|
| 1142 |
|
|
else
|
| 1143 |
|
|
chip_en = 0;
|
| 1144 |
|
|
end
|
| 1145 |
|
|
|
| 1146 |
|
|
if (CKEreg && ~CSNeg_ipd)
|
| 1147 |
|
|
begin
|
| 1148 |
|
|
if (DQM0_ipd == 1'bx)
|
| 1149 |
|
|
$display(" Unusable value for DQM0 ");
|
| 1150 |
|
|
if (DQM1_ipd == 1'bx)
|
| 1151 |
|
|
$display(" Unusable value for DQM1 ");
|
| 1152 |
|
|
if (DQM2_ipd == 1'bx)
|
| 1153 |
|
|
$display(" Unusable value for DQM2 ");
|
| 1154 |
|
|
if (DQM3_ipd == 1'bx)
|
| 1155 |
|
|
$display(" Unusable value for DQM3 ");
|
| 1156 |
|
|
if (WENeg_ipd == 1'bx)
|
| 1157 |
|
|
$display(" Unusable value for WENeg ");
|
| 1158 |
|
|
if (RASNeg_ipd == 1'bx)
|
| 1159 |
|
|
$display(" Unusable value for RASNeg ");
|
| 1160 |
|
|
if (CASNeg_ipd == 1'bx)
|
| 1161 |
|
|
$display(" Unusable value for CASNeg ");
|
| 1162 |
|
|
|
| 1163 |
|
|
// Command Decode
|
| 1164 |
|
|
if (RASNeg_ipd && CASNeg_ipd && WENeg_ipd)
|
| 1165 |
|
|
command = nop;
|
| 1166 |
|
|
else if (~RASNeg_ipd && CASNeg_ipd && WENeg_ipd)
|
| 1167 |
|
|
command = act;
|
| 1168 |
|
|
else if (RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd)
|
| 1169 |
|
|
command = rd;
|
| 1170 |
|
|
else if (RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd)
|
| 1171 |
|
|
command = writ;
|
| 1172 |
|
|
else if (RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd)
|
| 1173 |
|
|
command = bst;
|
| 1174 |
|
|
else if (~RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd)
|
| 1175 |
|
|
command = pre;
|
| 1176 |
|
|
else if (~RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd)
|
| 1177 |
|
|
command = ref;
|
| 1178 |
|
|
else if (~RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd)
|
| 1179 |
|
|
command = mrs;
|
| 1180 |
|
|
|
| 1181 |
|
|
// PowerUp Check
|
| 1182 |
|
|
if (~(PoweredUp) && command != nop)
|
| 1183 |
|
|
begin
|
| 1184 |
|
|
$display (" Incorrect power up. Command issued before ");
|
| 1185 |
|
|
$display (" power up complete. ");
|
| 1186 |
|
|
end
|
| 1187 |
|
|
|
| 1188 |
|
|
// Bank Decode
|
| 1189 |
|
|
if (~BA0_ipd && ~BA1_ipd)
|
| 1190 |
|
|
cur_bank = 0;
|
| 1191 |
|
|
else if (BA0_ipd && ~BA1_ipd)
|
| 1192 |
|
|
cur_bank = 1;
|
| 1193 |
|
|
else if (~BA0_ipd && BA1_ipd)
|
| 1194 |
|
|
cur_bank = 2;
|
| 1195 |
|
|
else if (BA0_ipd && BA1_ipd)
|
| 1196 |
|
|
cur_bank = 3;
|
| 1197 |
|
|
else
|
| 1198 |
|
|
begin
|
| 1199 |
|
|
$display ("Could not decode bank selection - results");
|
| 1200 |
|
|
$display ("may be incorrect.");
|
| 1201 |
|
|
end
|
| 1202 |
|
|
end
|
| 1203 |
|
|
|
| 1204 |
|
|
// The Big State Machine
|
| 1205 |
|
|
if (CKEreg)
|
| 1206 |
|
|
begin
|
| 1207 |
|
|
if (CSNeg_ipd == 1'bx)
|
| 1208 |
|
|
$display ("Unusable value for CSNeg");
|
| 1209 |
|
|
|
| 1210 |
|
|
if (CSNeg_ipd)
|
| 1211 |
|
|
command = nop;
|
| 1212 |
|
|
|
| 1213 |
|
|
// DQM pipeline
|
| 1214 |
|
|
DQM0_reg2 = DQM0_reg1;
|
| 1215 |
|
|
DQM0_reg1 = DQM0_reg0;
|
| 1216 |
|
|
DQM0_reg0 = DQM0_ipd;
|
| 1217 |
|
|
DQM1_reg2 = DQM1_reg1;
|
| 1218 |
|
|
DQM1_reg1 = DQM1_reg0;
|
| 1219 |
|
|
DQM1_reg0 = DQM1_ipd;
|
| 1220 |
|
|
DQM2_reg2 = DQM2_reg1;
|
| 1221 |
|
|
DQM2_reg1 = DQM2_reg0;
|
| 1222 |
|
|
DQM2_reg0 = DQM2_ipd;
|
| 1223 |
|
|
DQM3_reg2 = DQM3_reg1;
|
| 1224 |
|
|
DQM3_reg1 = DQM3_reg0;
|
| 1225 |
|
|
DQM3_reg0 = DQM3_ipd;
|
| 1226 |
|
|
|
| 1227 |
|
|
// by default data drive is Z, might get over written in one
|
| 1228 |
|
|
// of the passes below
|
| 1229 |
|
|
DataDrive = 32'bz;
|
| 1230 |
|
|
|
| 1231 |
|
|
for (bank = 0; bank <= hi_bank; bank = bank + 1)
|
| 1232 |
|
|
begin
|
| 1233 |
|
|
case (statebank[bank])
|
| 1234 |
|
|
pwron :
|
| 1235 |
|
|
begin
|
| 1236 |
|
|
if (~DQM0_ipd)
|
| 1237 |
|
|
begin
|
| 1238 |
|
|
$display ("DQM0 must be held high during");
|
| 1239 |
|
|
$display ("initialization.");
|
| 1240 |
|
|
end
|
| 1241 |
|
|
if (~DQM1_ipd)
|
| 1242 |
|
|
begin
|
| 1243 |
|
|
$display ("DQM1 must be held high during");
|
| 1244 |
|
|
$display ("initialization.");
|
| 1245 |
|
|
end
|
| 1246 |
|
|
if (~DQM2_ipd)
|
| 1247 |
|
|
begin
|
| 1248 |
|
|
$display ("DQM2 must be held high during");
|
| 1249 |
|
|
$display ("initialization.");
|
| 1250 |
|
|
end
|
| 1251 |
|
|
if (~DQM3_ipd)
|
| 1252 |
|
|
begin
|
| 1253 |
|
|
$display ("DQM3 must be held high during");
|
| 1254 |
|
|
$display ("initialization.");
|
| 1255 |
|
|
end
|
| 1256 |
|
|
|
| 1257 |
|
|
if (~PoweredUp)
|
| 1258 |
|
|
begin
|
| 1259 |
|
|
if (command != nop)
|
| 1260 |
|
|
$display ("Only NOPs allowed during power up.");
|
| 1261 |
|
|
DataDrive = 32'bz;
|
| 1262 |
|
|
end
|
| 1263 |
|
|
else if (command == pre && (cur_bank == bank || A[10]))
|
| 1264 |
|
|
begin
|
| 1265 |
|
|
statebank[bank] = precharge;
|
| 1266 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1267 |
|
|
end
|
| 1268 |
|
|
end
|
| 1269 |
|
|
|
| 1270 |
|
|
precharge :
|
| 1271 |
|
|
begin
|
| 1272 |
|
|
if (cur_bank == bank)
|
| 1273 |
|
|
// It is only an error if this bank is selected
|
| 1274 |
|
|
if (command != nop && command != pre)
|
| 1275 |
|
|
begin
|
| 1276 |
|
|
$display ("Illegal command received ");
|
| 1277 |
|
|
$display ("during precharge.",$time);
|
| 1278 |
|
|
end
|
| 1279 |
|
|
end
|
| 1280 |
|
|
|
| 1281 |
|
|
idle :
|
| 1282 |
|
|
begin
|
| 1283 |
|
|
if (command == nop || command == bst || command == pre
|
| 1284 |
|
|
|| cur_bank != bank)
|
| 1285 |
|
|
begin
|
| 1286 |
|
|
end
|
| 1287 |
|
|
else if (command == mrs)
|
| 1288 |
|
|
begin
|
| 1289 |
|
|
if (statebank[0] == idle && statebank[1] == idle &&
|
| 1290 |
|
|
statebank[2] == idle && statebank[3] == idle)
|
| 1291 |
|
|
begin
|
| 1292 |
|
|
ModeReg = A;
|
| 1293 |
|
|
statebank[bank] = mode_set;
|
| 1294 |
|
|
end
|
| 1295 |
|
|
end
|
| 1296 |
|
|
else if (command == ref)
|
| 1297 |
|
|
begin
|
| 1298 |
|
|
if (statebank[0] == idle && statebank[1] == idle &&
|
| 1299 |
|
|
statebank[2] == idle && statebank[3] == idle)
|
| 1300 |
|
|
if (CKE)
|
| 1301 |
|
|
begin
|
| 1302 |
|
|
statebank[bank] = auto_refresh;
|
| 1303 |
|
|
statebank[bank] <= #tdevice_TRCAR idle;
|
| 1304 |
|
|
end
|
| 1305 |
|
|
else
|
| 1306 |
|
|
begin
|
| 1307 |
|
|
statebank[0] = self_refresh;
|
| 1308 |
|
|
statebank[1] = self_refresh;
|
| 1309 |
|
|
statebank[2] = self_refresh;
|
| 1310 |
|
|
statebank[3] = self_refresh;
|
| 1311 |
|
|
end
|
| 1312 |
|
|
end
|
| 1313 |
|
|
else if (command == act)
|
| 1314 |
|
|
begin
|
| 1315 |
|
|
statebank[bank] = bank_act;
|
| 1316 |
|
|
ras_in[bank] = 1'b1;
|
| 1317 |
|
|
ras_in [bank] <= #70 1'b0;
|
| 1318 |
|
|
rct_in = 1'b1;
|
| 1319 |
|
|
rct_in <= #1 1'b0;
|
| 1320 |
|
|
rcdt_in[bank] = 1'b1;
|
| 1321 |
|
|
rcdt_in[bank] <= #1 1'b0;
|
| 1322 |
|
|
MemAddr[bank][19:8] = A; // latch row addr
|
| 1323 |
|
|
end
|
| 1324 |
|
|
else
|
| 1325 |
|
|
$display ("Illegal command received in idle state.",$time);
|
| 1326 |
|
|
end
|
| 1327 |
|
|
|
| 1328 |
|
|
mode_set :
|
| 1329 |
|
|
begin
|
| 1330 |
|
|
if (ModeReg[7] != 0 || ModeReg[8] != 0)
|
| 1331 |
|
|
$display ("Illegal operating mode set.");
|
| 1332 |
|
|
if (command != nop)
|
| 1333 |
|
|
begin
|
| 1334 |
|
|
$display ("Illegal command received during mode");
|
| 1335 |
|
|
$display ("set.",$time);
|
| 1336 |
|
|
end
|
| 1337 |
|
|
|
| 1338 |
|
|
// read burst length
|
| 1339 |
|
|
if (ModeReg[2:0] == 3'b000)
|
| 1340 |
|
|
begin
|
| 1341 |
|
|
BurstLen = 1;
|
| 1342 |
|
|
Burst_Bits = 0;
|
| 1343 |
|
|
end
|
| 1344 |
|
|
else if (ModeReg[2:0] == 3'b001)
|
| 1345 |
|
|
begin
|
| 1346 |
|
|
BurstLen = 2;
|
| 1347 |
|
|
Burst_Bits = 1;
|
| 1348 |
|
|
end
|
| 1349 |
|
|
else if (ModeReg[2:0] == 3'b010)
|
| 1350 |
|
|
begin
|
| 1351 |
|
|
BurstLen = 4;
|
| 1352 |
|
|
Burst_Bits = 2;
|
| 1353 |
|
|
end
|
| 1354 |
|
|
else if (ModeReg[2:0] == 3'b011)
|
| 1355 |
|
|
begin
|
| 1356 |
|
|
BurstLen = 8;
|
| 1357 |
|
|
Burst_Bits = 3;
|
| 1358 |
|
|
end
|
| 1359 |
|
|
else if (ModeReg[2:0] == 3'b111)
|
| 1360 |
|
|
begin
|
| 1361 |
|
|
BurstLen = 256;
|
| 1362 |
|
|
Burst_Bits = 7;
|
| 1363 |
|
|
end
|
| 1364 |
|
|
else
|
| 1365 |
|
|
$display ("Invalid burst length specified.");
|
| 1366 |
|
|
|
| 1367 |
|
|
// read burst type
|
| 1368 |
|
|
if (~ModeReg[3])
|
| 1369 |
|
|
Burst = sequential;
|
| 1370 |
|
|
else if (ModeReg[3])
|
| 1371 |
|
|
Burst = interleave;
|
| 1372 |
|
|
else
|
| 1373 |
|
|
$display ("Invalid burst type specified.");
|
| 1374 |
|
|
|
| 1375 |
|
|
// read CAS latency
|
| 1376 |
|
|
if (ModeReg[6:4] == 3'b001)
|
| 1377 |
|
|
begin
|
| 1378 |
|
|
CAS_Lat = 1'b1;
|
| 1379 |
|
|
CAS_Lat2 = 1'b0;
|
| 1380 |
|
|
end
|
| 1381 |
|
|
else if (ModeReg[6:4] == 3'b010)
|
| 1382 |
|
|
begin
|
| 1383 |
|
|
CAS_Lat = 1'b0;
|
| 1384 |
|
|
CAS_Lat2 = 1'b1;
|
| 1385 |
|
|
end
|
| 1386 |
|
|
else if (ModeReg[6:4] == 3'b011)
|
| 1387 |
|
|
begin
|
| 1388 |
|
|
CAS_Lat = 1'b1;
|
| 1389 |
|
|
CAS_Lat2 = 1'b1;
|
| 1390 |
|
|
end
|
| 1391 |
|
|
else
|
| 1392 |
|
|
$display ("CAS Latency set incorrecty");
|
| 1393 |
|
|
|
| 1394 |
|
|
// write burst mode
|
| 1395 |
|
|
if (~ModeReg[9])
|
| 1396 |
|
|
WB = programmed;
|
| 1397 |
|
|
else if (ModeReg[9])
|
| 1398 |
|
|
WB = single;
|
| 1399 |
|
|
else
|
| 1400 |
|
|
$display ("Invalid burst type specified.");
|
| 1401 |
|
|
|
| 1402 |
|
|
statebank[bank] = idle;
|
| 1403 |
|
|
end
|
| 1404 |
|
|
|
| 1405 |
|
|
auto_refresh :
|
| 1406 |
|
|
begin
|
| 1407 |
|
|
if (Ref_Cnt < 4096)
|
| 1408 |
|
|
Ref_Cnt = Ref_Cnt + 1;
|
| 1409 |
|
|
if (command != nop)
|
| 1410 |
|
|
begin
|
| 1411 |
|
|
$display ("Illegal command received during");
|
| 1412 |
|
|
$display ("auto_refresh.",$time);
|
| 1413 |
|
|
end
|
| 1414 |
|
|
end
|
| 1415 |
|
|
|
| 1416 |
|
|
bank_act :
|
| 1417 |
|
|
begin
|
| 1418 |
|
|
if (command == pre && (cur_bank == bank || A[10]))
|
| 1419 |
|
|
begin
|
| 1420 |
|
|
if (~ras_out[bank])
|
| 1421 |
|
|
begin
|
| 1422 |
|
|
$display ("precharge command does not meet tRAS");
|
| 1423 |
|
|
$display ("time", $time);
|
| 1424 |
|
|
end
|
| 1425 |
|
|
statebank[bank] = precharge;
|
| 1426 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1427 |
|
|
end
|
| 1428 |
|
|
else if (command == nop || command == bst
|
| 1429 |
|
|
|| cur_bank != bank)
|
| 1430 |
|
|
begin
|
| 1431 |
|
|
end
|
| 1432 |
|
|
else if (command == rd)
|
| 1433 |
|
|
begin
|
| 1434 |
|
|
if (rcdt_out[bank])
|
| 1435 |
|
|
begin
|
| 1436 |
|
|
$display ("read command received too soon");
|
| 1437 |
|
|
$display ("after active",$time);
|
| 1438 |
|
|
end
|
| 1439 |
|
|
if (A[10] == 1'bx)
|
| 1440 |
|
|
begin
|
| 1441 |
|
|
$display ("A(10) = X during read command.");
|
| 1442 |
|
|
$display ("Next state unknown.");
|
| 1443 |
|
|
end
|
| 1444 |
|
|
MemAddr[bank][7:0] = 8'b0;// clr old addr
|
| 1445 |
|
|
// latch col addr
|
| 1446 |
|
|
if (Burst_Bits == 0)
|
| 1447 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1448 |
|
|
if (Burst_Bits == 1)
|
| 1449 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1450 |
|
|
if (Burst_Bits == 2)
|
| 1451 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1452 |
|
|
if (Burst_Bits == 3)
|
| 1453 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1454 |
|
|
if (Burst_Bits == 7)
|
| 1455 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1456 |
|
|
BurstIncProc(bank);
|
| 1457 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1458 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1459 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1460 |
|
|
generate_out(DataDrive,bank);
|
| 1461 |
|
|
BurstCnt[bank] = 1;
|
| 1462 |
|
|
NextStateAuto(bank, read);
|
| 1463 |
|
|
bank_tmp = bank;
|
| 1464 |
|
|
end
|
| 1465 |
|
|
else if (command == writ)
|
| 1466 |
|
|
begin
|
| 1467 |
|
|
if (rcdt_out[bank])
|
| 1468 |
|
|
begin
|
| 1469 |
|
|
$display ("write command received too soon");
|
| 1470 |
|
|
$display ("after active",$time);
|
| 1471 |
|
|
end
|
| 1472 |
|
|
if (A[10] == 1'bx)
|
| 1473 |
|
|
begin
|
| 1474 |
|
|
$display ("A(10) = X during write command.");
|
| 1475 |
|
|
$display ("Next state unknown.");
|
| 1476 |
|
|
end
|
| 1477 |
|
|
MemAddr[bank][7:0] = 8'b0; // clr old addr
|
| 1478 |
|
|
BurstIncProc(bank);
|
| 1479 |
|
|
// latch col addr
|
| 1480 |
|
|
if (Burst_Bits == 0)
|
| 1481 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1482 |
|
|
if (Burst_Bits == 1)
|
| 1483 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1484 |
|
|
if (Burst_Bits == 2)
|
| 1485 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1486 |
|
|
if (Burst_Bits == 3)
|
| 1487 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1488 |
|
|
if (Burst_Bits == 7)
|
| 1489 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1490 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1491 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1492 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1493 |
|
|
MemWrite(bank);
|
| 1494 |
|
|
BurstCnt[bank] = 1'b1;
|
| 1495 |
|
|
wrt_in = 1'b1;
|
| 1496 |
|
|
NextStateAuto(bank, write);
|
| 1497 |
|
|
written = 1'b1;
|
| 1498 |
|
|
end
|
| 1499 |
|
|
else if (cur_bank == bank || command == mrs)
|
| 1500 |
|
|
begin
|
| 1501 |
|
|
$display ("Illegal command received in");
|
| 1502 |
|
|
$display ("active state",$time);
|
| 1503 |
|
|
end
|
| 1504 |
|
|
end
|
| 1505 |
|
|
|
| 1506 |
|
|
write :
|
| 1507 |
|
|
begin
|
| 1508 |
|
|
if (command == bst)
|
| 1509 |
|
|
begin
|
| 1510 |
|
|
statebank[bank] = bank_act;
|
| 1511 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1512 |
|
|
end
|
| 1513 |
|
|
else if (command == rd)
|
| 1514 |
|
|
if (cur_bank == bank)
|
| 1515 |
|
|
begin
|
| 1516 |
|
|
MemAddr[bank][7:0] = 8'b0;// clr old addr
|
| 1517 |
|
|
BurstIncProc(bank);
|
| 1518 |
|
|
// latch col addr
|
| 1519 |
|
|
if (Burst_Bits == 0)
|
| 1520 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1521 |
|
|
if (Burst_Bits == 1)
|
| 1522 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1523 |
|
|
if (Burst_Bits == 2)
|
| 1524 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1525 |
|
|
if (Burst_Bits == 3)
|
| 1526 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1527 |
|
|
if (Burst_Bits == 7)
|
| 1528 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1529 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1530 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1531 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1532 |
|
|
generate_out(DataDrive, bank);
|
| 1533 |
|
|
BurstCnt[bank] = 1'b1;
|
| 1534 |
|
|
NextStateAuto(bank, read);
|
| 1535 |
|
|
end
|
| 1536 |
|
|
else
|
| 1537 |
|
|
statebank[bank] = bank_act;
|
| 1538 |
|
|
else if (command == writ)
|
| 1539 |
|
|
if (cur_bank == bank)
|
| 1540 |
|
|
begin
|
| 1541 |
|
|
MemAddr[bank][7:0] = 8'b0;// clr old addr
|
| 1542 |
|
|
BurstIncProc(bank);
|
| 1543 |
|
|
// latch col addr
|
| 1544 |
|
|
if (Burst_Bits == 0)
|
| 1545 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1546 |
|
|
if (Burst_Bits == 1)
|
| 1547 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1548 |
|
|
if (Burst_Bits == 2)
|
| 1549 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1550 |
|
|
if (Burst_Bits == 3)
|
| 1551 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1552 |
|
|
if (Burst_Bits == 7)
|
| 1553 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1554 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1555 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1556 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1557 |
|
|
MemWrite(bank);
|
| 1558 |
|
|
BurstCnt[bank] = 1'b1;
|
| 1559 |
|
|
wrt_in = 1'b1;
|
| 1560 |
|
|
if (A[10])
|
| 1561 |
|
|
statebank[bank] = write_auto_pre;
|
| 1562 |
|
|
end
|
| 1563 |
|
|
else
|
| 1564 |
|
|
statebank[bank] = bank_act;
|
| 1565 |
|
|
else if (command == pre && (cur_bank == bank || A[10]))
|
| 1566 |
|
|
begin
|
| 1567 |
|
|
if (~ras_out[bank])
|
| 1568 |
|
|
begin
|
| 1569 |
|
|
$display ("precharge command does not meet tRAS time",$time);
|
| 1570 |
|
|
end
|
| 1571 |
|
|
if (~DQM0_ipd)
|
| 1572 |
|
|
begin
|
| 1573 |
|
|
$display ("DQM0 should be held high, data is");
|
| 1574 |
|
|
$display ("lost.",$time);
|
| 1575 |
|
|
end
|
| 1576 |
|
|
if (~DQM1_ipd)
|
| 1577 |
|
|
begin
|
| 1578 |
|
|
$display ("DQM1 should be held high, data is");
|
| 1579 |
|
|
$display ("lost.",$time);
|
| 1580 |
|
|
end
|
| 1581 |
|
|
if (~DQM2_ipd)
|
| 1582 |
|
|
begin
|
| 1583 |
|
|
$display ("DQM2 should be held high, data is");
|
| 1584 |
|
|
$display ("lost.",$time);
|
| 1585 |
|
|
end
|
| 1586 |
|
|
if (~DQM2_ipd)
|
| 1587 |
|
|
begin
|
| 1588 |
|
|
$display ("DQM2 should be held high, data is");
|
| 1589 |
|
|
$display ("lost.",$time);
|
| 1590 |
|
|
end
|
| 1591 |
|
|
wrt_in = 1'b0;
|
| 1592 |
|
|
statebank[bank] = precharge;
|
| 1593 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1594 |
|
|
end
|
| 1595 |
|
|
else if (command == nop || cur_bank != bank)
|
| 1596 |
|
|
if (BurstCnt[bank] == BurstLen || WB == single)
|
| 1597 |
|
|
begin
|
| 1598 |
|
|
statebank[bank] = bank_act;
|
| 1599 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1600 |
|
|
ras_in[bank] = 1'b1;
|
| 1601 |
|
|
end
|
| 1602 |
|
|
else
|
| 1603 |
|
|
begin
|
| 1604 |
|
|
if (Burst == sequential)
|
| 1605 |
|
|
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
|
| 1606 |
|
|
else
|
| 1607 |
|
|
BurstInc[bank] =
|
| 1608 |
|
|
intab[StartAddr[bank]*8 + BurstCnt[bank]];
|
| 1609 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1610 |
|
|
MemWrite(bank);
|
| 1611 |
|
|
BurstCnt[bank] = BurstCnt[bank] + 1;
|
| 1612 |
|
|
wrt_in = 1'b1;
|
| 1613 |
|
|
end
|
| 1614 |
|
|
else if (cur_bank == bank)
|
| 1615 |
|
|
$display ("Illegal command received in write state",$time);
|
| 1616 |
|
|
end
|
| 1617 |
|
|
|
| 1618 |
|
|
read :
|
| 1619 |
|
|
begin
|
| 1620 |
|
|
if (command == bst)
|
| 1621 |
|
|
begin
|
| 1622 |
|
|
statebank[bank] = bank_act;
|
| 1623 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1624 |
|
|
end
|
| 1625 |
|
|
else if (command == rd)
|
| 1626 |
|
|
if (cur_bank == bank)
|
| 1627 |
|
|
begin
|
| 1628 |
|
|
MemAddr[bank][7:0] = 8'b0;// clr old addr
|
| 1629 |
|
|
BurstIncProc(bank);
|
| 1630 |
|
|
// latch col addr
|
| 1631 |
|
|
if (Burst_Bits == 0)
|
| 1632 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1633 |
|
|
if (Burst_Bits == 1)
|
| 1634 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1635 |
|
|
if (Burst_Bits == 2)
|
| 1636 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1637 |
|
|
if (Burst_Bits == 3)
|
| 1638 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1639 |
|
|
if (Burst_Bits == 7)
|
| 1640 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1641 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1642 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1643 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1644 |
|
|
generate_out(DataDrive, bank);
|
| 1645 |
|
|
BurstCnt[bank] = 1'b1;
|
| 1646 |
|
|
NextStateAuto(bank, read);
|
| 1647 |
|
|
end
|
| 1648 |
|
|
else
|
| 1649 |
|
|
statebank[bank] = bank_act;
|
| 1650 |
|
|
else if (command == writ)
|
| 1651 |
|
|
if (cur_bank == bank)
|
| 1652 |
|
|
begin
|
| 1653 |
|
|
if (rcdt_out[bank])
|
| 1654 |
|
|
begin
|
| 1655 |
|
|
$display ("write command received too soon after active",$time);
|
| 1656 |
|
|
end
|
| 1657 |
|
|
if (A[10] == 1'bx)
|
| 1658 |
|
|
begin
|
| 1659 |
|
|
$display ("A(10) = X during write command.");
|
| 1660 |
|
|
$display ("Next state unknown.");
|
| 1661 |
|
|
end
|
| 1662 |
|
|
|
| 1663 |
|
|
MemAddr[bank][7:0] = 8'b0;// clr old addr
|
| 1664 |
|
|
BurstIncProc(bank);
|
| 1665 |
|
|
// latch col addr
|
| 1666 |
|
|
if (Burst_Bits == 0)
|
| 1667 |
|
|
MemAddr[bank][7:0] = A[7:0];
|
| 1668 |
|
|
if (Burst_Bits == 1)
|
| 1669 |
|
|
MemAddr[bank][7:1] = A[7:1];
|
| 1670 |
|
|
if (Burst_Bits == 2)
|
| 1671 |
|
|
MemAddr[bank][7:2] = A[7:2];
|
| 1672 |
|
|
if (Burst_Bits == 3)
|
| 1673 |
|
|
MemAddr[bank][7:3] = A[7:3];
|
| 1674 |
|
|
if (Burst_Bits == 7)
|
| 1675 |
|
|
MemAddr[bank][7:7] = A[7:7];
|
| 1676 |
|
|
StartAddr[bank] = BurstInc[bank] % 8;
|
| 1677 |
|
|
BaseLoc[bank] = MemAddr[bank];
|
| 1678 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1679 |
|
|
MemWrite(bank);
|
| 1680 |
|
|
BurstCnt[bank] = 1'b1;
|
| 1681 |
|
|
wrt_in = 1'b1;
|
| 1682 |
|
|
NextStateAuto(bank,write);
|
| 1683 |
|
|
end
|
| 1684 |
|
|
else
|
| 1685 |
|
|
statebank[bank] = bank_act;
|
| 1686 |
|
|
|
| 1687 |
|
|
else if (command == pre && (cur_bank == bank || A[10]))
|
| 1688 |
|
|
begin
|
| 1689 |
|
|
if (~ras_out[bank])
|
| 1690 |
|
|
begin
|
| 1691 |
|
|
$display ("Precharge command does not meet tRAS time",$time);
|
| 1692 |
|
|
end
|
| 1693 |
|
|
statebank[bank] = precharge;
|
| 1694 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1695 |
|
|
end
|
| 1696 |
|
|
|
| 1697 |
|
|
else if (command == nop || cur_bank != bank)
|
| 1698 |
|
|
begin
|
| 1699 |
|
|
if (BurstCnt[bank] == BurstLen)
|
| 1700 |
|
|
begin
|
| 1701 |
|
|
statebank[bank] = bank_act;
|
| 1702 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1703 |
|
|
ras_in[bank] = 1'b1;
|
| 1704 |
|
|
end
|
| 1705 |
|
|
else
|
| 1706 |
|
|
begin
|
| 1707 |
|
|
if (Burst == sequential)
|
| 1708 |
|
|
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
|
| 1709 |
|
|
else
|
| 1710 |
|
|
BurstInc[bank] =
|
| 1711 |
|
|
intab[StartAddr[bank]*8 + BurstCnt[bank]];
|
| 1712 |
|
|
|
| 1713 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1714 |
|
|
generate_out(DataDrive, bank);
|
| 1715 |
|
|
BurstCnt[bank] = BurstCnt[bank] + 1;
|
| 1716 |
|
|
end
|
| 1717 |
|
|
end
|
| 1718 |
|
|
else if (cur_bank == bank)
|
| 1719 |
|
|
$display ("Illegal command received in read state",$time);
|
| 1720 |
|
|
end
|
| 1721 |
|
|
|
| 1722 |
|
|
write_auto_pre :
|
| 1723 |
|
|
begin
|
| 1724 |
|
|
if (command == nop || cur_bank != bank)
|
| 1725 |
|
|
if (BurstCnt[bank] == BurstLen || WB == single)
|
| 1726 |
|
|
begin
|
| 1727 |
|
|
statebank[bank] = precharge;
|
| 1728 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1729 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1730 |
|
|
ras_in[bank] = 1'b1;
|
| 1731 |
|
|
end
|
| 1732 |
|
|
else
|
| 1733 |
|
|
begin
|
| 1734 |
|
|
if (Burst == sequential)
|
| 1735 |
|
|
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
|
| 1736 |
|
|
else
|
| 1737 |
|
|
BurstInc[bank] =
|
| 1738 |
|
|
intab[StartAddr[bank]*8 + BurstCnt[bank]];
|
| 1739 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1740 |
|
|
MemWrite(bank);
|
| 1741 |
|
|
BurstCnt[bank] = BurstCnt[bank] + 1;
|
| 1742 |
|
|
wrt_in = 1'b1;
|
| 1743 |
|
|
end
|
| 1744 |
|
|
else
|
| 1745 |
|
|
$display ("Illegal command received in write state.",$time);
|
| 1746 |
|
|
end
|
| 1747 |
|
|
|
| 1748 |
|
|
read_auto_pre :
|
| 1749 |
|
|
begin
|
| 1750 |
|
|
if (command == nop || (cur_bank != bank && command != rd
|
| 1751 |
|
|
&& command != writ))
|
| 1752 |
|
|
if (BurstCnt[bank] == BurstLen)
|
| 1753 |
|
|
begin
|
| 1754 |
|
|
statebank[bank] = precharge;
|
| 1755 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1756 |
|
|
BurstCnt[bank] = 1'b0;
|
| 1757 |
|
|
ras_in[bank] = 1'b1;
|
| 1758 |
|
|
end
|
| 1759 |
|
|
else
|
| 1760 |
|
|
begin
|
| 1761 |
|
|
if (Burst == sequential)
|
| 1762 |
|
|
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
|
| 1763 |
|
|
else
|
| 1764 |
|
|
BurstInc[bank] =
|
| 1765 |
|
|
intab[StartAddr[bank]*8 + BurstCnt[bank]];
|
| 1766 |
|
|
Loc = 4*(BaseLoc[bank] + BurstInc[bank]);
|
| 1767 |
|
|
generate_out(DataDrive, bank);
|
| 1768 |
|
|
BurstCnt[bank] = BurstCnt[bank] + 1;
|
| 1769 |
|
|
end
|
| 1770 |
|
|
else if ((command == rd || command == writ) && cur_bank
|
| 1771 |
|
|
!= bank)
|
| 1772 |
|
|
begin
|
| 1773 |
|
|
statebank[bank] = precharge;
|
| 1774 |
|
|
statebank[bank] <= #tdevice_TRP idle;
|
| 1775 |
|
|
end
|
| 1776 |
|
|
else
|
| 1777 |
|
|
$display ("Illegal command received in read state",$time);
|
| 1778 |
|
|
end
|
| 1779 |
|
|
endcase
|
| 1780 |
|
|
end
|
| 1781 |
|
|
|
| 1782 |
|
|
// Check Refresh Status
|
| 1783 |
|
|
if (written && (Ref_Cnt == 0))
|
| 1784 |
|
|
$display ("memory not refreshed (by ref_cnt)", $time);
|
| 1785 |
|
|
|
| 1786 |
|
|
DataDrive3 = DataDrive2;
|
| 1787 |
|
|
DataDrive2 = DataDrive1;
|
| 1788 |
|
|
DataDrive1 = DataDrive;
|
| 1789 |
|
|
|
| 1790 |
|
|
end
|
| 1791 |
|
|
|
| 1792 |
|
|
// Latency adjustments and DQM read masking
|
| 1793 |
|
|
if (~DQM0_reg1)
|
| 1794 |
|
|
if (CAS_Lat && CAS_Lat2)
|
| 1795 |
|
|
DataDriveOut[7:0] = DataDrive3[7:0];
|
| 1796 |
|
|
else if (~CAS_Lat && CAS_Lat2)
|
| 1797 |
|
|
DataDriveOut[7:0] = DataDrive2[7:0];
|
| 1798 |
|
|
else
|
| 1799 |
|
|
DataDriveOut[7:0] = DataDrive1[7:0];
|
| 1800 |
|
|
else
|
| 1801 |
|
|
DataDriveOut[7:0] = 8'bz;
|
| 1802 |
|
|
|
| 1803 |
|
|
if (~DQM1_reg1)
|
| 1804 |
|
|
if (CAS_Lat && CAS_Lat2)
|
| 1805 |
|
|
DataDriveOut[15:8] = DataDrive3[15:8];
|
| 1806 |
|
|
else if (~CAS_Lat && CAS_Lat2)
|
| 1807 |
|
|
DataDriveOut[15:8] = DataDrive2[15:8];
|
| 1808 |
|
|
else
|
| 1809 |
|
|
DataDriveOut[15:8] = DataDrive1[15:8];
|
| 1810 |
|
|
else
|
| 1811 |
|
|
DataDriveOut[15:8] = 8'bz;
|
| 1812 |
|
|
|
| 1813 |
|
|
if (~DQM2_reg1)
|
| 1814 |
|
|
if (CAS_Lat && CAS_Lat2)
|
| 1815 |
|
|
DataDriveOut[23:16] = DataDrive3[23:16];
|
| 1816 |
|
|
else if (~CAS_Lat && CAS_Lat2)
|
| 1817 |
|
|
DataDriveOut[23:16] = DataDrive2[23:16];
|
| 1818 |
|
|
else
|
| 1819 |
|
|
DataDriveOut[23:16] = DataDrive1[23:16];
|
| 1820 |
|
|
else
|
| 1821 |
|
|
DataDriveOut[23:16] = 8'bz;
|
| 1822 |
|
|
|
| 1823 |
|
|
if (~DQM3_reg1)
|
| 1824 |
|
|
if (CAS_Lat && CAS_Lat2)
|
| 1825 |
|
|
DataDriveOut[31:24] = DataDrive3[31:24];
|
| 1826 |
|
|
else if (~CAS_Lat && CAS_Lat2)
|
| 1827 |
|
|
DataDriveOut[31:24] = DataDrive2[31:24];
|
| 1828 |
|
|
else
|
| 1829 |
|
|
DataDriveOut[31:24] = DataDrive1[31:24];
|
| 1830 |
|
|
else
|
| 1831 |
|
|
DataDriveOut[31:24] = 8'bz;
|
| 1832 |
|
|
|
| 1833 |
|
|
// The Powering-up State Machine
|
| 1834 |
|
|
if (~CKEreg && CKE_ipd)
|
| 1835 |
|
|
begin
|
| 1836 |
|
|
if (CSNeg_ipd == 1'bx)
|
| 1837 |
|
|
$display ("Unusable value for CSNeg");
|
| 1838 |
|
|
if (CSNeg_ipd)
|
| 1839 |
|
|
command = nop;
|
| 1840 |
|
|
|
| 1841 |
|
|
case (statebank[cur_bank])
|
| 1842 |
|
|
write_suspend :
|
| 1843 |
|
|
begin
|
| 1844 |
|
|
statebank[cur_bank] = write;
|
| 1845 |
|
|
end
|
| 1846 |
|
|
|
| 1847 |
|
|
read_suspend :
|
| 1848 |
|
|
begin
|
| 1849 |
|
|
statebank[cur_bank] = read;
|
| 1850 |
|
|
end
|
| 1851 |
|
|
|
| 1852 |
|
|
self_refresh :
|
| 1853 |
|
|
begin
|
| 1854 |
|
|
statebank[0] <= #tdevice_TRP idle;
|
| 1855 |
|
|
statebank[1] <= #tdevice_TRP idle;
|
| 1856 |
|
|
statebank[2] <= #tdevice_TRP idle;
|
| 1857 |
|
|
statebank[3] <= #tdevice_TRP idle;
|
| 1858 |
|
|
Ref_Cnt = 4096;
|
| 1859 |
|
|
if (command != nop)
|
| 1860 |
|
|
begin
|
| 1861 |
|
|
$display ("Illegal command received during self");
|
| 1862 |
|
|
$display ("refresh",$time);
|
| 1863 |
|
|
end
|
| 1864 |
|
|
end
|
| 1865 |
|
|
|
| 1866 |
|
|
pwrdwn :
|
| 1867 |
|
|
begin
|
| 1868 |
|
|
statebank[0] = idle;
|
| 1869 |
|
|
statebank[1] = idle;
|
| 1870 |
|
|
statebank[2] = idle;
|
| 1871 |
|
|
statebank[3] = idle;
|
| 1872 |
|
|
end
|
| 1873 |
|
|
|
| 1874 |
|
|
bank_act_pwrdwn :
|
| 1875 |
|
|
begin
|
| 1876 |
|
|
statebank[cur_bank] = bank_act;
|
| 1877 |
|
|
end
|
| 1878 |
|
|
endcase
|
| 1879 |
|
|
end
|
| 1880 |
|
|
|
| 1881 |
|
|
// The Powering-down State Machine
|
| 1882 |
|
|
if (CKEreg && ~CKE_ipd)
|
| 1883 |
|
|
begin
|
| 1884 |
|
|
if (CSNeg_ipd == 1'bx)
|
| 1885 |
|
|
$display ("Unusable value for CSNeg");
|
| 1886 |
|
|
if (CSNeg_ipd)
|
| 1887 |
|
|
command = nop;
|
| 1888 |
|
|
|
| 1889 |
|
|
case (statebank[cur_bank])
|
| 1890 |
|
|
idle :
|
| 1891 |
|
|
begin
|
| 1892 |
|
|
if (command == nop)
|
| 1893 |
|
|
begin
|
| 1894 |
|
|
statebank[0] = pwrdwn;
|
| 1895 |
|
|
statebank[1] = pwrdwn;
|
| 1896 |
|
|
statebank[2] = pwrdwn;
|
| 1897 |
|
|
statebank[3] = pwrdwn;
|
| 1898 |
|
|
end
|
| 1899 |
|
|
end
|
| 1900 |
|
|
|
| 1901 |
|
|
write :
|
| 1902 |
|
|
begin
|
| 1903 |
|
|
statebank[cur_bank] = write_suspend;
|
| 1904 |
|
|
end
|
| 1905 |
|
|
|
| 1906 |
|
|
read :
|
| 1907 |
|
|
begin
|
| 1908 |
|
|
statebank[cur_bank] = read_suspend;
|
| 1909 |
|
|
end
|
| 1910 |
|
|
|
| 1911 |
|
|
bank_act :
|
| 1912 |
|
|
begin
|
| 1913 |
|
|
statebank[cur_bank] = bank_act_pwrdwn;
|
| 1914 |
|
|
end
|
| 1915 |
|
|
endcase
|
| 1916 |
|
|
end
|
| 1917 |
|
|
|
| 1918 |
|
|
CKEreg = CKE_ipd;
|
| 1919 |
|
|
end
|
| 1920 |
|
|
|
| 1921 |
|
|
always @(DataDriveOut)
|
| 1922 |
|
|
begin
|
| 1923 |
|
|
DQ_zd = DataDriveOut;
|
| 1924 |
|
|
end
|
| 1925 |
|
|
|
| 1926 |
|
|
reg TRC_In , TRCAR_In;
|
| 1927 |
|
|
reg TRCD_In , TRP_In , TWR_In;
|
| 1928 |
|
|
wire TRC_Out, TRCAR_Out, TRCD_Out, TRP_Out, TWR_Out;
|
| 1929 |
|
|
|
| 1930 |
|
|
BUFFER BUF_TRC (TRC_Out , TRC_In);
|
| 1931 |
|
|
BUFFER BUF_TRCAR (TRCAR_Out, TRCAR_In);
|
| 1932 |
|
|
BUFFER BUF_TRCD (TRCD_Out , TRCD_In);
|
| 1933 |
|
|
BUFFER BUF_TRP (TRP_Out , TRP_In);
|
| 1934 |
|
|
BUFFER BUF_TWR (TWR_Out , TWR_In);
|
| 1935 |
|
|
|
| 1936 |
|
|
initial
|
| 1937 |
|
|
begin
|
| 1938 |
|
|
TRC_In = 1;
|
| 1939 |
|
|
TRCAR_In = 1;
|
| 1940 |
|
|
TRCD_In = 1'b1;
|
| 1941 |
|
|
TRP_In = 1;
|
| 1942 |
|
|
TWR_In = 1;
|
| 1943 |
|
|
end
|
| 1944 |
|
|
|
| 1945 |
|
|
always @(posedge TRC_Out)
|
| 1946 |
|
|
begin
|
| 1947 |
|
|
tdevice_TRC = $time;
|
| 1948 |
|
|
end
|
| 1949 |
|
|
|
| 1950 |
|
|
always @(posedge TRCAR_Out)
|
| 1951 |
|
|
begin
|
| 1952 |
|
|
tdevice_TRCAR = $time;
|
| 1953 |
|
|
end
|
| 1954 |
|
|
|
| 1955 |
|
|
always @(posedge TRCD_Out)
|
| 1956 |
|
|
begin
|
| 1957 |
|
|
tdevice_TRCD = $time;
|
| 1958 |
|
|
end
|
| 1959 |
|
|
|
| 1960 |
|
|
always @(posedge TRP_Out)
|
| 1961 |
|
|
begin
|
| 1962 |
|
|
tdevice_TRP = $time;
|
| 1963 |
|
|
end
|
| 1964 |
|
|
|
| 1965 |
|
|
always @(posedge TWR_Out)
|
| 1966 |
|
|
begin
|
| 1967 |
|
|
tdevice_TWR = $time;
|
| 1968 |
|
|
end
|
| 1969 |
|
|
|
| 1970 |
|
|
endmodule
|
| 1971 |
|
|
|
| 1972 |
|
|
module BUFFER (OUT,IN);
|
| 1973 |
|
|
input IN;
|
| 1974 |
|
|
output OUT;
|
| 1975 |
|
|
buf (OUT, IN);
|
| 1976 |
|
|
endmodule
|
