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dinesha |
/****************************************************************************************
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*
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* File Name: MT48LC8M8A2.V
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* Version: 0.0f
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* Date: July 8th, 1999
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* Model: BUS Functional
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* Simulator: Model Technology (PC version 5.2e PE)
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*
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* Dependencies: None
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*
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* Author: Son P. Huynh
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* Email: sphuynh@micron.com
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* Phone: (208) 368-3825
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* Company: Micron Technology, Inc.
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* Model: MT48LC8M16A2 (2Meg x 8 x 4 Banks)
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*
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* Description: Micron 128Mb SDRAM Verilog model
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*
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* Limitation: - Doesn't check for 4096 cycle refresh
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*
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* Note: - Set simulator resolution to "ps" accuracy
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* - Set Debug = 0 to disable $display messages
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*
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* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
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* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
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* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
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*
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* Copyright © 1998 Micron Semiconductor Products, Inc.
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* All rights researved
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*
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* Rev Author Phone Date Changes
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* ---- ---------------------------- ---------- ---------------------------------------
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* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto)
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* Micron Technology Inc. - Fix tWR = 15 ns (Manual)
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* - Fix tRP (Autoprecharge to AutoRefresh)
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*
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* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e)
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* Micron Technology Inc.
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****************************************************************************************/
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`timescale 1ns / 100ps
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module mt48lc8m8a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
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parameter addr_bits = 12;
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parameter data_bits = 8;
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parameter col_bits = 9;
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parameter mem_sizes = 2097151; // 2 Meg
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inout [data_bits - 1 : 0] Dq;
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input [addr_bits - 1 : 0] Addr;
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input [1 : 0] Ba;
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input Clk;
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input Cke;
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input Cs_n;
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input Ras_n;
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input Cas_n;
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input We_n;
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input [0 : 0] Dqm;
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reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
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reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
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reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
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reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
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reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
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reg [0 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
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reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
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reg [addr_bits - 1 : 0] Mode_reg;
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reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
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reg [col_bits - 1 : 0] Col_temp, Burst_counter;
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reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
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reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
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reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
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reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
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reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank)
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reg Read_precharge [0 : 3]; // R AutoPrecharge
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reg Write_precharge [0 : 3]; // W AutoPrecharge
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integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter)
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reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
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reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
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reg Data_in_enable;
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reg Data_out_enable;
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reg [1 : 0] Bank, Previous_bank;
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reg [addr_bits - 1 : 0] Row;
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reg [col_bits - 1 : 0] Col, Col_brst;
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// Internal system clock
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reg CkeZ, Sys_clk;
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// Commands Decode
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wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
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wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
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wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
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wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
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wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
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wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
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wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
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// Burst Length Decode
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wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
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wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
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wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
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wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
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// CAS Latency Decode
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wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
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wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
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32 |
dinesha |
`ifdef VERBOSE
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wire Debug = 1'b1; // Debug messages : 1 = On
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`else
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wire Debug = 1'b0; // Debug messages : 1 = On
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`endif
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17 |
dinesha |
// Write Burst Mode
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wire Write_burst_mode = Mode_reg[9];
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wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
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assign Dq = Dq_reg; // DQ buffer
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// Commands Operation
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`define ACT 0
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`define NOP 1
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`define READ 2
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`define READ_A 3
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`define SDRAM_WRITE 4
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`define WRITE_A 5
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`define SDRAM_PRECH 6
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`define SDRAM_A_REF 7
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`define SDRAM_BST 8
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`define SDRAM_LMR 9
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// Timing Parameters for -75 (PC133) and CAS Latency = 2
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parameter tAC = 6.0;
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parameter tHZ = 7.0;
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parameter tOH = 2.7;
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parameter tMRD = 2.0; // 2 Clk Cycles
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parameter tRAS = 44.0;
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parameter tRC = 66.0;
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parameter tRCD = 20.0;
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parameter tRP = 20.0;
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parameter tRRD = 15.0;
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parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
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parameter tWRp = 15.0; // A2 Version - Precharge mode only (15 ns)
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// Timing Check variable
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integer MRD_chk;
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integer WR_counter [0 : 3];
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time WR_chk [0 : 3];
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time RC_chk, RRD_chk;
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time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
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time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
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time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
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initial begin
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Dq_reg = {data_bits{1'bz}};
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{Data_in_enable, Data_out_enable} = 0;
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{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
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{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
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{WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0;
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{WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0;
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{RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0;
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{RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0;
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{MRD_chk, RC_chk, RRD_chk} = 0;
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{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
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{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
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{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
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$timeformat (-9, 0, " ns", 12);
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//$readmemh("bank0.txt", Bank0);
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//$readmemh("bank1.txt", Bank1);
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//$readmemh("bank2.txt", Bank2);
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//$readmemh("bank3.txt", Bank3);
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end
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// System clock generator
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always begin
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@ (posedge Clk) begin
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Sys_clk = CkeZ;
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CkeZ = Cke;
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end
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@ (negedge Clk) begin
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Sys_clk = 1'b0;
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end
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end
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always @ (posedge Sys_clk) begin
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// Internal Commamd Pipelined
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Command[0] = Command[1];
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Command[1] = Command[2];
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Command[2] = Command[3];
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Command[3] = `NOP;
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Col_addr[0] = Col_addr[1];
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Col_addr[1] = Col_addr[2];
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Col_addr[2] = Col_addr[3];
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Col_addr[3] = {col_bits{1'b0}};
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Bank_addr[0] = Bank_addr[1];
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Bank_addr[1] = Bank_addr[2];
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Bank_addr[2] = Bank_addr[3];
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Bank_addr[3] = 2'b0;
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Bank_precharge[0] = Bank_precharge[1];
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Bank_precharge[1] = Bank_precharge[2];
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Bank_precharge[2] = Bank_precharge[3];
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Bank_precharge[3] = 2'b0;
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A10_precharge[0] = A10_precharge[1];
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A10_precharge[1] = A10_precharge[2];
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A10_precharge[2] = A10_precharge[3];
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A10_precharge[3] = 1'b0;
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// Dqm pipeline for Read
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Dqm_reg0 = Dqm_reg1;
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Dqm_reg1 = Dqm;
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// Read or Write with Auto Precharge Counter
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if (Auto_precharge[0] == 1'b1) begin
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Count_precharge[0] = Count_precharge[0] + 1;
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end
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if (Auto_precharge[1] == 1'b1) begin
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Count_precharge[1] = Count_precharge[1] + 1;
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end
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if (Auto_precharge[2] == 1'b1) begin
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Count_precharge[2] = Count_precharge[2] + 1;
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end
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if (Auto_precharge[3] == 1'b1) begin
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Count_precharge[3] = Count_precharge[3] + 1;
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end
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// tMRD Counter
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MRD_chk = MRD_chk + 1;
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// tWR Counter for Write
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WR_counter[0] = WR_counter[0] + 1;
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WR_counter[1] = WR_counter[1] + 1;
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WR_counter[2] = WR_counter[2] + 1;
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WR_counter[3] = WR_counter[3] + 1;
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// Auto Refresh
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if (Aref_enable == 1'b1) begin
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if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
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// Auto Refresh to Auto Refresh
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if ($time - RC_chk < tRC) begin
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//->tb.test_control.error_detected;
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$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
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end
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// Precharge to Auto Refresh
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if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
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//->tb.test_control.error_detected;
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$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
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end
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// Precharge to Refresh
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if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
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//->tb.test_control.error_detected;
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$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
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end
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// Record Current tRC time
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RC_chk = $time;
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end
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// Load Mode Register
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if (Mode_reg_enable == 1'b1) begin
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// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
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if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin
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Mode_reg = Addr;
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if (Debug) begin
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$display ("at time %t LMR : Load Mode Register", $time);
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// CAS Latency
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if (Addr[6 : 4] == 3'b010)
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$display (" CAS Latency = 2");
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else if (Addr[6 : 4] == 3'b011)
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$display (" CAS Latency = 3");
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else
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$display (" CAS Latency = Reserved");
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// Burst Length
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if (Addr[2 : 0] == 3'b000)
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$display (" Burst Length = 1");
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else if (Addr[2 : 0] == 3'b001)
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$display (" Burst Length = 2");
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else if (Addr[2 : 0] == 3'b010)
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$display (" Burst Length = 4");
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else if (Addr[2 : 0] == 3'b011)
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$display (" Burst Length = 8");
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else if (Addr[3 : 0] == 4'b0111)
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$display (" Burst Length = Full");
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else
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|
|
$display (" Burst Length = Reserved");
|
| 299 |
|
|
// Burst Type
|
| 300 |
|
|
if (Addr[3] == 1'b0)
|
| 301 |
|
|
$display (" Burst Type = Sequential");
|
| 302 |
|
|
else if (Addr[3] == 1'b1)
|
| 303 |
|
|
$display (" Burst Type = Interleaved");
|
| 304 |
|
|
else
|
| 305 |
|
|
$display (" Burst Type = Reserved");
|
| 306 |
|
|
// Write Burst Mode
|
| 307 |
|
|
if (Addr[9] == 1'b0)
|
| 308 |
|
|
$display (" Write Burst Mode = Programmed Burst Length");
|
| 309 |
|
|
else if (Addr[9] == 1'b1)
|
| 310 |
|
|
$display (" Write Burst Mode = Single Location Access");
|
| 311 |
|
|
else
|
| 312 |
|
|
$display (" Write Burst Mode = Reserved");
|
| 313 |
|
|
end
|
| 314 |
|
|
end else begin
|
| 315 |
|
|
|
| 316 |
|
|
//->tb.test_control.error_detected;
|
| 317 |
|
|
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
|
| 318 |
|
|
end
|
| 319 |
|
|
// REF to LMR
|
| 320 |
|
|
if ($time - RC_chk < tRC) begin
|
| 321 |
|
|
|
| 322 |
|
|
//->tb.test_control.error_detected;
|
| 323 |
|
|
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
|
| 324 |
|
|
end
|
| 325 |
|
|
// LMR to LMR
|
| 326 |
|
|
if (MRD_chk < tMRD) begin
|
| 327 |
|
|
|
| 328 |
|
|
//->tb.test_control.error_detected;
|
| 329 |
|
|
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
|
| 330 |
|
|
end
|
| 331 |
|
|
MRD_chk = 0;
|
| 332 |
|
|
end
|
| 333 |
|
|
|
| 334 |
|
|
// Active Block (Latch Bank Address and Row Address)
|
| 335 |
|
|
if (Active_enable == 1'b1) begin
|
| 336 |
|
|
if (Ba == 2'b00 && Pc_b0 == 1'b1) begin
|
| 337 |
|
|
{Act_b0, Pc_b0} = 2'b10;
|
| 338 |
|
|
B0_row_addr = Addr [addr_bits - 1 : 0];
|
| 339 |
|
|
RCD_chk0 = $time;
|
| 340 |
|
|
RAS_chk0 = $time;
|
| 341 |
|
|
if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr);
|
| 342 |
|
|
// Precharge to Activate Bank 0
|
| 343 |
|
|
if ($time - RP_chk0 < tRP) begin
|
| 344 |
|
|
|
| 345 |
|
|
//->tb.test_control.error_detected;
|
| 346 |
|
|
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
|
| 347 |
|
|
end
|
| 348 |
|
|
end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
|
| 349 |
|
|
{Act_b1, Pc_b1} = 2'b10;
|
| 350 |
|
|
B1_row_addr = Addr [addr_bits - 1 : 0];
|
| 351 |
|
|
RCD_chk1 = $time;
|
| 352 |
|
|
RAS_chk1 = $time;
|
| 353 |
|
|
if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr);
|
| 354 |
|
|
// Precharge to Activate Bank 1
|
| 355 |
|
|
if ($time - RP_chk1 < tRP) begin
|
| 356 |
|
|
|
| 357 |
|
|
//->tb.test_control.error_detected;
|
| 358 |
|
|
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
|
| 359 |
|
|
end
|
| 360 |
|
|
end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
|
| 361 |
|
|
{Act_b2, Pc_b2} = 2'b10;
|
| 362 |
|
|
B2_row_addr = Addr [addr_bits - 1 : 0];
|
| 363 |
|
|
RCD_chk2 = $time;
|
| 364 |
|
|
RAS_chk2 = $time;
|
| 365 |
|
|
if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr);
|
| 366 |
|
|
// Precharge to Activate Bank 2
|
| 367 |
|
|
if ($time - RP_chk2 < tRP) begin
|
| 368 |
|
|
|
| 369 |
|
|
//->tb.test_control.error_detected;
|
| 370 |
|
|
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
|
| 371 |
|
|
end
|
| 372 |
|
|
end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
|
| 373 |
|
|
{Act_b3, Pc_b3} = 2'b10;
|
| 374 |
|
|
B3_row_addr = Addr [addr_bits - 1 : 0];
|
| 375 |
|
|
RCD_chk3 = $time;
|
| 376 |
|
|
RAS_chk3 = $time;
|
| 377 |
|
|
if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr);
|
| 378 |
|
|
// Precharge to Activate Bank 3
|
| 379 |
|
|
if ($time - RP_chk3 < tRP) begin
|
| 380 |
|
|
|
| 381 |
|
|
//->tb.test_control.error_detected;
|
| 382 |
|
|
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
|
| 383 |
|
|
end
|
| 384 |
|
|
end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
|
| 385 |
|
|
|
| 386 |
|
|
//->tb.test_control.error_detected;
|
| 387 |
|
|
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
|
| 388 |
|
|
end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
|
| 389 |
|
|
|
| 390 |
|
|
//->tb.test_control.error_detected;
|
| 391 |
|
|
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
|
| 392 |
|
|
end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
|
| 393 |
|
|
|
| 394 |
|
|
//->tb.test_control.error_detected;
|
| 395 |
|
|
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
|
| 396 |
|
|
end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
|
| 397 |
|
|
|
| 398 |
|
|
//->tb.test_control.error_detected;
|
| 399 |
|
|
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
|
| 400 |
|
|
end
|
| 401 |
|
|
// Active Bank A to Active Bank B
|
| 402 |
|
|
if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
|
| 403 |
|
|
|
| 404 |
|
|
//->tb.test_control.error_detected;
|
| 405 |
|
|
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
|
| 406 |
|
|
end
|
| 407 |
|
|
// Load Mode Register to Active
|
| 408 |
|
|
if (MRD_chk < tMRD ) begin
|
| 409 |
|
|
|
| 410 |
|
|
//->tb.test_control.error_detected;
|
| 411 |
|
|
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
|
| 412 |
|
|
end
|
| 413 |
|
|
// Auto Refresh to Activate
|
| 414 |
|
|
if ($time - RC_chk < tRC) begin
|
| 415 |
|
|
|
| 416 |
|
|
//->tb.test_control.error_detected;
|
| 417 |
|
|
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
|
| 418 |
|
|
end
|
| 419 |
|
|
// Record variables for checking violation
|
| 420 |
|
|
RRD_chk = $time;
|
| 421 |
|
|
Previous_bank = Ba;
|
| 422 |
|
|
end
|
| 423 |
|
|
|
| 424 |
|
|
// Precharge Block
|
| 425 |
|
|
if (Prech_enable == 1'b1) begin
|
| 426 |
|
|
if (Addr[10] == 1'b1) begin
|
| 427 |
|
|
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;
|
| 428 |
|
|
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
|
| 429 |
|
|
RP_chk0 = $time;
|
| 430 |
|
|
RP_chk1 = $time;
|
| 431 |
|
|
RP_chk2 = $time;
|
| 432 |
|
|
RP_chk3 = $time;
|
| 433 |
|
|
if (Debug) $display ("at time %t PRE : Bank = ALL",$time);
|
| 434 |
|
|
// Activate to Precharge all banks
|
| 435 |
|
|
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
|
| 436 |
|
|
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
|
| 437 |
|
|
|
| 438 |
|
|
//->tb.test_control.error_detected;
|
| 439 |
|
|
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
|
| 440 |
|
|
end
|
| 441 |
|
|
// tWR violation check for write
|
| 442 |
|
|
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
|
| 443 |
|
|
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
|
| 444 |
|
|
|
| 445 |
|
|
//->tb.test_control.error_detected;
|
| 446 |
|
|
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
|
| 447 |
|
|
end
|
| 448 |
|
|
end else if (Addr[10] == 1'b0) begin
|
| 449 |
|
|
if (Ba == 2'b00) begin
|
| 450 |
|
|
{Pc_b0, Act_b0} = 2'b10;
|
| 451 |
|
|
RP_chk0 = $time;
|
| 452 |
|
|
if (Debug) $display ("at time %t PRE : Bank = 0",$time);
|
| 453 |
|
|
// Activate to Precharge Bank 0
|
| 454 |
|
|
if ($time - RAS_chk0 < tRAS) begin
|
| 455 |
|
|
|
| 456 |
|
|
//->tb.test_control.error_detected;
|
| 457 |
|
|
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
|
| 458 |
|
|
end
|
| 459 |
|
|
end else if (Ba == 2'b01) begin
|
| 460 |
|
|
{Pc_b1, Act_b1} = 2'b10;
|
| 461 |
|
|
RP_chk1 = $time;
|
| 462 |
|
|
if (Debug) $display ("at time %t PRE : Bank = 1",$time);
|
| 463 |
|
|
// Activate to Precharge Bank 1
|
| 464 |
|
|
if ($time - RAS_chk1 < tRAS) begin
|
| 465 |
|
|
|
| 466 |
|
|
//->tb.test_control.error_detected;
|
| 467 |
|
|
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
|
| 468 |
|
|
end
|
| 469 |
|
|
end else if (Ba == 2'b10) begin
|
| 470 |
|
|
{Pc_b2, Act_b2} = 2'b10;
|
| 471 |
|
|
RP_chk2 = $time;
|
| 472 |
|
|
if (Debug) $display ("at time %t PRE : Bank = 2",$time);
|
| 473 |
|
|
// Activate to Precharge Bank 2
|
| 474 |
|
|
if ($time - RAS_chk2 < tRAS) begin
|
| 475 |
|
|
|
| 476 |
|
|
//->tb.test_control.error_detected;
|
| 477 |
|
|
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
|
| 478 |
|
|
end
|
| 479 |
|
|
end else if (Ba == 2'b11) begin
|
| 480 |
|
|
{Pc_b3, Act_b3} = 2'b10;
|
| 481 |
|
|
RP_chk3 = $time;
|
| 482 |
|
|
if (Debug) $display ("at time %t PRE : Bank = 3",$time);
|
| 483 |
|
|
// Activate to Precharge Bank 3
|
| 484 |
|
|
if ($time - RAS_chk3 < tRAS) begin
|
| 485 |
|
|
|
| 486 |
|
|
//->tb.test_control.error_detected;
|
| 487 |
|
|
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
|
| 488 |
|
|
end
|
| 489 |
|
|
end
|
| 490 |
|
|
// tWR violation check for write
|
| 491 |
|
|
if ($time - WR_chk[Ba] < tWRp) begin
|
| 492 |
|
|
|
| 493 |
|
|
//->tb.test_control.error_detected;
|
| 494 |
|
|
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
|
| 495 |
|
|
end
|
| 496 |
|
|
end
|
| 497 |
|
|
// Terminate a Write Immediately (if same bank or all banks)
|
| 498 |
|
|
if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin
|
| 499 |
|
|
Data_in_enable = 1'b0;
|
| 500 |
|
|
end
|
| 501 |
|
|
// Precharge Command Pipeline for Read
|
| 502 |
|
|
if (Cas_latency_3 == 1'b1) begin
|
| 503 |
|
|
Command[2] = `SDRAM_PRECH;
|
| 504 |
|
|
Bank_precharge[2] = Ba;
|
| 505 |
|
|
A10_precharge[2] = Addr[10];
|
| 506 |
|
|
end else if (Cas_latency_2 == 1'b1) begin
|
| 507 |
|
|
Command[1] = `SDRAM_PRECH;
|
| 508 |
|
|
Bank_precharge[1] = Ba;
|
| 509 |
|
|
A10_precharge[1] = Addr[10];
|
| 510 |
|
|
end
|
| 511 |
|
|
end
|
| 512 |
|
|
|
| 513 |
|
|
// Burst terminate
|
| 514 |
|
|
if (Burst_term == 1'b1) begin
|
| 515 |
|
|
// Terminate a Write Immediately
|
| 516 |
|
|
if (Data_in_enable == 1'b1) begin
|
| 517 |
|
|
Data_in_enable = 1'b0;
|
| 518 |
|
|
end
|
| 519 |
|
|
// Terminate a Read Depend on CAS Latency
|
| 520 |
|
|
if (Cas_latency_3 == 1'b1) begin
|
| 521 |
|
|
Command[2] = `SDRAM_BST;
|
| 522 |
|
|
end else if (Cas_latency_2 == 1'b1) begin
|
| 523 |
|
|
Command[1] = `SDRAM_BST;
|
| 524 |
|
|
end
|
| 525 |
|
|
if (Debug) $display ("at time %t BST : Burst Terminate",$time);
|
| 526 |
|
|
end
|
| 527 |
|
|
|
| 528 |
|
|
// Read, Write, Column Latch
|
| 529 |
|
|
if (Read_enable == 1'b1 || Write_enable == 1'b1) begin
|
| 530 |
|
|
// Check to see if bank is open (ACT)
|
| 531 |
|
|
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
|
| 532 |
|
|
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
|
| 533 |
|
|
|
| 534 |
|
|
//->tb.test_control.error_detected;
|
| 535 |
|
|
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
|
| 536 |
|
|
end
|
| 537 |
|
|
// Activate to Read or Write
|
| 538 |
|
|
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
|
| 539 |
|
|
begin
|
| 540 |
|
|
//->tb.test_control.error_detected;
|
| 541 |
|
|
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
|
| 542 |
|
|
end
|
| 543 |
|
|
|
| 544 |
|
|
if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
|
| 545 |
|
|
begin
|
| 546 |
|
|
//->tb.test_control.error_detected;
|
| 547 |
|
|
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
|
| 548 |
|
|
end
|
| 549 |
|
|
if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
|
| 550 |
|
|
begin
|
| 551 |
|
|
//->tb.test_control.error_detected;
|
| 552 |
|
|
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
|
| 553 |
|
|
end
|
| 554 |
|
|
if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
|
| 555 |
|
|
begin
|
| 556 |
|
|
//->tb.test_control.error_detected;
|
| 557 |
|
|
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
|
| 558 |
|
|
end
|
| 559 |
|
|
// Read Command
|
| 560 |
|
|
if (Read_enable == 1'b1) begin
|
| 561 |
|
|
// CAS Latency pipeline
|
| 562 |
|
|
if (Cas_latency_3 == 1'b1) begin
|
| 563 |
|
|
if (Addr[10] == 1'b1) begin
|
| 564 |
|
|
Command[2] = `READ_A;
|
| 565 |
|
|
end else begin
|
| 566 |
|
|
Command[2] = `READ;
|
| 567 |
|
|
end
|
| 568 |
|
|
Col_addr[2] = Addr;
|
| 569 |
|
|
Bank_addr[2] = Ba;
|
| 570 |
|
|
end else if (Cas_latency_2 == 1'b1) begin
|
| 571 |
|
|
if (Addr[10] == 1'b1) begin
|
| 572 |
|
|
Command[1] = `READ_A;
|
| 573 |
|
|
end else begin
|
| 574 |
|
|
Command[1] = `READ;
|
| 575 |
|
|
end
|
| 576 |
|
|
Col_addr[1] = Addr;
|
| 577 |
|
|
Bank_addr[1] = Ba;
|
| 578 |
|
|
end
|
| 579 |
|
|
|
| 580 |
|
|
// Read interrupt Write (terminate Write immediately)
|
| 581 |
|
|
if (Data_in_enable == 1'b1) begin
|
| 582 |
|
|
Data_in_enable = 1'b0;
|
| 583 |
|
|
end
|
| 584 |
|
|
|
| 585 |
|
|
// Write Command
|
| 586 |
|
|
end else if (Write_enable == 1'b1) begin
|
| 587 |
|
|
if (Addr[10] == 1'b1) begin
|
| 588 |
|
|
Command[0] = `WRITE_A;
|
| 589 |
|
|
end else begin
|
| 590 |
|
|
Command[0] = `SDRAM_WRITE;
|
| 591 |
|
|
end
|
| 592 |
|
|
Col_addr[0] = Addr;
|
| 593 |
|
|
Bank_addr[0] = Ba;
|
| 594 |
|
|
|
| 595 |
|
|
// Write interrupt Write (terminate Write immediately)
|
| 596 |
|
|
if (Data_in_enable == 1'b1) begin
|
| 597 |
|
|
Data_in_enable = 1'b0;
|
| 598 |
|
|
end
|
| 599 |
|
|
|
| 600 |
|
|
// Write interrupt Read (terminate Read immediately)
|
| 601 |
|
|
if (Data_out_enable == 1'b1) begin
|
| 602 |
|
|
Data_out_enable = 1'b0;
|
| 603 |
|
|
end
|
| 604 |
|
|
end
|
| 605 |
|
|
|
| 606 |
|
|
// Interrupting a Write with Autoprecharge
|
| 607 |
|
|
if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin
|
| 608 |
|
|
RW_interrupt_write[Bank] = 1'b1;
|
| 609 |
|
|
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank);
|
| 610 |
|
|
end
|
| 611 |
|
|
|
| 612 |
|
|
// Interrupting a Read with Autoprecharge
|
| 613 |
|
|
if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin
|
| 614 |
|
|
RW_interrupt_read[Bank] = 1'b1;
|
| 615 |
|
|
if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank);
|
| 616 |
|
|
end
|
| 617 |
|
|
|
| 618 |
|
|
// Read or Write with Auto Precharge
|
| 619 |
|
|
if (Addr[10] == 1'b1) begin
|
| 620 |
|
|
Auto_precharge[Ba] = 1'b1;
|
| 621 |
|
|
Count_precharge[Ba] = 0;
|
| 622 |
|
|
if (Read_enable == 1'b1) begin
|
| 623 |
|
|
Read_precharge[Ba] = 1'b1;
|
| 624 |
|
|
end else if (Write_enable == 1'b1) begin
|
| 625 |
|
|
Write_precharge[Ba] = 1'b1;
|
| 626 |
|
|
end
|
| 627 |
|
|
end
|
| 628 |
|
|
end
|
| 629 |
|
|
|
| 630 |
|
|
// Read with Auto Precharge Calculation
|
| 631 |
|
|
// The device start internal precharge:
|
| 632 |
|
|
// 1. CAS Latency - 1 cycles before last burst
|
| 633 |
|
|
// and 2. Meet minimum tRAS requirement
|
| 634 |
|
|
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
|
| 635 |
|
|
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
|
| 636 |
|
|
if ((($time - RAS_chk0 >= tRAS) && // Case 2
|
| 637 |
|
|
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1
|
| 638 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
|
| 639 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
|
| 640 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
|
| 641 |
|
|
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
|
| 642 |
|
|
Pc_b0 = 1'b1;
|
| 643 |
|
|
Act_b0 = 1'b0;
|
| 644 |
|
|
RP_chk0 = $time;
|
| 645 |
|
|
Auto_precharge[0] = 1'b0;
|
| 646 |
|
|
Read_precharge[0] = 1'b0;
|
| 647 |
|
|
RW_interrupt_read[0] = 1'b0;
|
| 648 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
|
| 649 |
|
|
end
|
| 650 |
|
|
end
|
| 651 |
|
|
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
|
| 652 |
|
|
if ((($time - RAS_chk1 >= tRAS) &&
|
| 653 |
|
|
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
|
| 654 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
|
| 655 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
|
| 656 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
|
| 657 |
|
|
(RW_interrupt_read[1] == 1'b1)) begin
|
| 658 |
|
|
Pc_b1 = 1'b1;
|
| 659 |
|
|
Act_b1 = 1'b0;
|
| 660 |
|
|
RP_chk1 = $time;
|
| 661 |
|
|
Auto_precharge[1] = 1'b0;
|
| 662 |
|
|
Read_precharge[1] = 1'b0;
|
| 663 |
|
|
RW_interrupt_read[1] = 1'b0;
|
| 664 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
|
| 665 |
|
|
end
|
| 666 |
|
|
end
|
| 667 |
|
|
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
|
| 668 |
|
|
if ((($time - RAS_chk2 >= tRAS) &&
|
| 669 |
|
|
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
|
| 670 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
|
| 671 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
|
| 672 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
|
| 673 |
|
|
(RW_interrupt_read[2] == 1'b1)) begin
|
| 674 |
|
|
Pc_b2 = 1'b1;
|
| 675 |
|
|
Act_b2 = 1'b0;
|
| 676 |
|
|
RP_chk2 = $time;
|
| 677 |
|
|
Auto_precharge[2] = 1'b0;
|
| 678 |
|
|
Read_precharge[2] = 1'b0;
|
| 679 |
|
|
RW_interrupt_read[2] = 1'b0;
|
| 680 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
|
| 681 |
|
|
end
|
| 682 |
|
|
end
|
| 683 |
|
|
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
|
| 684 |
|
|
if ((($time - RAS_chk3 >= tRAS) &&
|
| 685 |
|
|
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
|
| 686 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
|
| 687 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
|
| 688 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
|
| 689 |
|
|
(RW_interrupt_read[3] == 1'b1)) begin
|
| 690 |
|
|
Pc_b3 = 1'b1;
|
| 691 |
|
|
Act_b3 = 1'b0;
|
| 692 |
|
|
RP_chk3 = $time;
|
| 693 |
|
|
Auto_precharge[3] = 1'b0;
|
| 694 |
|
|
Read_precharge[3] = 1'b0;
|
| 695 |
|
|
RW_interrupt_read[3] = 1'b0;
|
| 696 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
|
| 697 |
|
|
end
|
| 698 |
|
|
end
|
| 699 |
|
|
|
| 700 |
|
|
// Internal Precharge or Bst
|
| 701 |
|
|
if (Command[0] == `SDRAM_PRECH) begin // Precharge terminate a read with same bank or all banks
|
| 702 |
|
|
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
|
| 703 |
|
|
if (Data_out_enable == 1'b1) begin
|
| 704 |
|
|
Data_out_enable = 1'b0;
|
| 705 |
|
|
end
|
| 706 |
|
|
end
|
| 707 |
|
|
end else if (Command[0] == `SDRAM_BST) begin // BST terminate a read to current bank
|
| 708 |
|
|
if (Data_out_enable == 1'b1) begin
|
| 709 |
|
|
Data_out_enable = 1'b0;
|
| 710 |
|
|
end
|
| 711 |
|
|
end
|
| 712 |
|
|
|
| 713 |
|
|
if (Data_out_enable == 1'b0) begin
|
| 714 |
|
|
Dq_reg <= #tOH {data_bits{1'bz}};
|
| 715 |
|
|
end
|
| 716 |
|
|
|
| 717 |
|
|
// Detect Read or Write command
|
| 718 |
|
|
if (Command[0] == `READ || Command[0] == `READ_A) begin
|
| 719 |
|
|
Bank = Bank_addr[0];
|
| 720 |
|
|
Col = Col_addr[0];
|
| 721 |
|
|
Col_brst = Col_addr[0];
|
| 722 |
|
|
if (Bank_addr[0] == 2'b00) begin
|
| 723 |
|
|
Row = B0_row_addr;
|
| 724 |
|
|
end else if (Bank_addr[0] == 2'b01) begin
|
| 725 |
|
|
Row = B1_row_addr;
|
| 726 |
|
|
end else if (Bank_addr[0] == 2'b10) begin
|
| 727 |
|
|
Row = B2_row_addr;
|
| 728 |
|
|
end else if (Bank_addr[0] == 2'b11) begin
|
| 729 |
|
|
Row = B3_row_addr;
|
| 730 |
|
|
end
|
| 731 |
|
|
Burst_counter = 0;
|
| 732 |
|
|
Data_in_enable = 1'b0;
|
| 733 |
|
|
Data_out_enable = 1'b1;
|
| 734 |
|
|
end else if (Command[0] == `SDRAM_WRITE || Command[0] == `WRITE_A) begin
|
| 735 |
|
|
Bank = Bank_addr[0];
|
| 736 |
|
|
Col = Col_addr[0];
|
| 737 |
|
|
Col_brst = Col_addr[0];
|
| 738 |
|
|
if (Bank_addr[0] == 2'b00) begin
|
| 739 |
|
|
Row = B0_row_addr;
|
| 740 |
|
|
end else if (Bank_addr[0] == 2'b01) begin
|
| 741 |
|
|
Row = B1_row_addr;
|
| 742 |
|
|
end else if (Bank_addr[0] == 2'b10) begin
|
| 743 |
|
|
Row = B2_row_addr;
|
| 744 |
|
|
end else if (Bank_addr[0] == 2'b11) begin
|
| 745 |
|
|
Row = B3_row_addr;
|
| 746 |
|
|
end
|
| 747 |
|
|
Burst_counter = 0;
|
| 748 |
|
|
Data_in_enable = 1'b1;
|
| 749 |
|
|
Data_out_enable = 1'b0;
|
| 750 |
|
|
end
|
| 751 |
|
|
|
| 752 |
|
|
// DQ buffer (Driver/Receiver)
|
| 753 |
|
|
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
|
| 754 |
|
|
// Array buffer
|
| 755 |
|
|
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
|
| 756 |
|
|
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
|
| 757 |
|
|
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
|
| 758 |
|
|
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
|
| 759 |
|
|
// Dqm operation
|
| 760 |
|
|
if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
|
| 761 |
|
|
// Write to memory
|
| 762 |
|
|
if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [15 : 0];
|
| 763 |
|
|
if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [15 : 0];
|
| 764 |
|
|
if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [15 : 0];
|
| 765 |
|
|
if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [15 : 0];
|
| 766 |
|
|
// Output result
|
| 767 |
|
|
if (Dqm == 1'b1) begin
|
| 768 |
|
|
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
|
| 769 |
|
|
end else begin
|
| 770 |
|
|
if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %h, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm);
|
| 771 |
|
|
// Record tWR time and reset counter
|
| 772 |
|
|
WR_chk [Bank] = $time;
|
| 773 |
|
|
WR_counter [Bank] = 0;
|
| 774 |
|
|
end
|
| 775 |
|
|
// Advance burst counter subroutine
|
| 776 |
|
|
#tHZ Burst;
|
| 777 |
|
|
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
|
| 778 |
|
|
// Array buffer
|
| 779 |
|
|
if (Bank == 2'b00) Dq_dqm [15 : 0] = Bank0 [{Row, Col}];
|
| 780 |
|
|
if (Bank == 2'b01) Dq_dqm [15 : 0] = Bank1 [{Row, Col}];
|
| 781 |
|
|
if (Bank == 2'b10) Dq_dqm [15 : 0] = Bank2 [{Row, Col}];
|
| 782 |
|
|
if (Bank == 2'b11) Dq_dqm [15 : 0] = Bank3 [{Row, Col}];
|
| 783 |
|
|
// Dqm operation
|
| 784 |
|
|
if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz;
|
| 785 |
|
|
// Display result
|
| 786 |
|
|
Dq_reg [15 : 0] = #tAC Dq_dqm [15 : 0];
|
| 787 |
|
|
if (Dqm_reg0 == 1'b1) begin
|
| 788 |
|
|
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
|
| 789 |
|
|
end else begin
|
| 790 |
|
|
if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %h, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0);
|
| 791 |
|
|
end
|
| 792 |
|
|
// Advance burst counter subroutine
|
| 793 |
|
|
Burst;
|
| 794 |
|
|
end
|
| 795 |
|
|
end
|
| 796 |
|
|
|
| 797 |
|
|
// Write with Auto Precharge Calculation
|
| 798 |
|
|
// The device start internal precharge:
|
| 799 |
|
|
// 1. tWR Clock after last burst
|
| 800 |
|
|
// and 2. Meet minimum tRAS requirement
|
| 801 |
|
|
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
|
| 802 |
|
|
always @ (WR_counter[0]) begin
|
| 803 |
|
|
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
|
| 804 |
|
|
if ((($time - RAS_chk0 >= tRAS) && // Case 2
|
| 805 |
|
|
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1
|
| 806 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
|
| 807 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
|
| 808 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
|
| 809 |
|
|
(RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt)
|
| 810 |
|
|
Auto_precharge[0] = 1'b0;
|
| 811 |
|
|
Write_precharge[0] = 1'b0;
|
| 812 |
|
|
RW_interrupt_write[0] = 1'b0;
|
| 813 |
|
|
#tWRa; // Wait for tWR
|
| 814 |
|
|
Pc_b0 = 1'b1;
|
| 815 |
|
|
Act_b0 = 1'b0;
|
| 816 |
|
|
RP_chk0 = $time;
|
| 817 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
|
| 818 |
|
|
end
|
| 819 |
|
|
end
|
| 820 |
|
|
end
|
| 821 |
|
|
always @ (WR_counter[1]) begin
|
| 822 |
|
|
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
|
| 823 |
|
|
if ((($time - RAS_chk1 >= tRAS) &&
|
| 824 |
|
|
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
|
| 825 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
|
| 826 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
|
| 827 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
|
| 828 |
|
|
(RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin
|
| 829 |
|
|
Auto_precharge[1] = 1'b0;
|
| 830 |
|
|
Write_precharge[1] = 1'b0;
|
| 831 |
|
|
RW_interrupt_write[1] = 1'b0;
|
| 832 |
|
|
#tWRa; // Wait for tWR
|
| 833 |
|
|
Pc_b1 = 1'b1;
|
| 834 |
|
|
Act_b1 = 1'b0;
|
| 835 |
|
|
RP_chk1 = $time;
|
| 836 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
|
| 837 |
|
|
end
|
| 838 |
|
|
end
|
| 839 |
|
|
end
|
| 840 |
|
|
always @ (WR_counter[2]) begin
|
| 841 |
|
|
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
|
| 842 |
|
|
if ((($time - RAS_chk2 >= tRAS) &&
|
| 843 |
|
|
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
|
| 844 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
|
| 845 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
|
| 846 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
|
| 847 |
|
|
(RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin
|
| 848 |
|
|
Auto_precharge[2] = 1'b0;
|
| 849 |
|
|
Write_precharge[2] = 1'b0;
|
| 850 |
|
|
RW_interrupt_write[2] = 1'b0;
|
| 851 |
|
|
#tWRa; // Wait for tWR
|
| 852 |
|
|
Pc_b2 = 1'b1;
|
| 853 |
|
|
Act_b2 = 1'b0;
|
| 854 |
|
|
RP_chk2 = $time;
|
| 855 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
|
| 856 |
|
|
end
|
| 857 |
|
|
end
|
| 858 |
|
|
end
|
| 859 |
|
|
always @ (WR_counter[3]) begin
|
| 860 |
|
|
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
|
| 861 |
|
|
if ((($time - RAS_chk3 >= tRAS) &&
|
| 862 |
|
|
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
|
| 863 |
|
|
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
|
| 864 |
|
|
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
|
| 865 |
|
|
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
|
| 866 |
|
|
(RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin
|
| 867 |
|
|
Auto_precharge[3] = 1'b0;
|
| 868 |
|
|
Write_precharge[3] = 1'b0;
|
| 869 |
|
|
RW_interrupt_write[3] = 1'b0;
|
| 870 |
|
|
#tWRa; // Wait for tWR
|
| 871 |
|
|
Pc_b3 = 1'b1;
|
| 872 |
|
|
Act_b3 = 1'b0;
|
| 873 |
|
|
RP_chk3 = $time;
|
| 874 |
|
|
if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
|
| 875 |
|
|
end
|
| 876 |
|
|
end
|
| 877 |
|
|
end
|
| 878 |
|
|
|
| 879 |
|
|
task Burst;
|
| 880 |
|
|
begin
|
| 881 |
|
|
// Advance Burst Counter
|
| 882 |
|
|
Burst_counter = Burst_counter + 1;
|
| 883 |
|
|
|
| 884 |
|
|
// Burst Type
|
| 885 |
|
|
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
|
| 886 |
|
|
Col_temp = Col + 1;
|
| 887 |
|
|
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
|
| 888 |
|
|
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
|
| 889 |
|
|
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
|
| 890 |
|
|
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
|
| 891 |
|
|
end
|
| 892 |
|
|
|
| 893 |
|
|
// Burst Length
|
| 894 |
|
|
if (Burst_length_2) begin // Burst Length = 2
|
| 895 |
|
|
Col [0] = Col_temp [0];
|
| 896 |
|
|
end else if (Burst_length_4) begin // Burst Length = 4
|
| 897 |
|
|
Col [1 : 0] = Col_temp [1 : 0];
|
| 898 |
|
|
end else if (Burst_length_8) begin // Burst Length = 8
|
| 899 |
|
|
Col [2 : 0] = Col_temp [2 : 0];
|
| 900 |
|
|
end else begin // Burst Length = FULL
|
| 901 |
|
|
Col = Col_temp;
|
| 902 |
|
|
end
|
| 903 |
|
|
|
| 904 |
|
|
// Burst Read Single Write
|
| 905 |
|
|
if (Write_burst_mode == 1'b1) begin
|
| 906 |
|
|
Data_in_enable = 1'b0;
|
| 907 |
|
|
end
|
| 908 |
|
|
|
| 909 |
|
|
// Data Counter
|
| 910 |
|
|
if (Burst_length_1 == 1'b1) begin
|
| 911 |
|
|
if (Burst_counter >= 1) begin
|
| 912 |
|
|
Data_in_enable = 1'b0;
|
| 913 |
|
|
Data_out_enable = 1'b0;
|
| 914 |
|
|
end
|
| 915 |
|
|
end else if (Burst_length_2 == 1'b1) begin
|
| 916 |
|
|
if (Burst_counter >= 2) begin
|
| 917 |
|
|
Data_in_enable = 1'b0;
|
| 918 |
|
|
Data_out_enable = 1'b0;
|
| 919 |
|
|
end
|
| 920 |
|
|
end else if (Burst_length_4 == 1'b1) begin
|
| 921 |
|
|
if (Burst_counter >= 4) begin
|
| 922 |
|
|
Data_in_enable = 1'b0;
|
| 923 |
|
|
Data_out_enable = 1'b0;
|
| 924 |
|
|
end
|
| 925 |
|
|
end else if (Burst_length_8 == 1'b1) begin
|
| 926 |
|
|
if (Burst_counter >= 8) begin
|
| 927 |
|
|
Data_in_enable = 1'b0;
|
| 928 |
|
|
Data_out_enable = 1'b0;
|
| 929 |
|
|
end
|
| 930 |
|
|
end
|
| 931 |
|
|
end
|
| 932 |
|
|
endtask
|
| 933 |
|
|
|
| 934 |
|
|
// Timing Parameters for -75 (PC133) and CAS Latency = 2
|
| 935 |
|
|
specify
|
| 936 |
|
|
specparam
|
| 937 |
|
|
tAH = 0.8, // Addr, Ba Hold Time
|
| 938 |
|
|
tAS = 1.5, // Addr, Ba Setup Time
|
| 939 |
|
|
tCH = 2.5, // Clock High-Level Width
|
| 940 |
|
|
tCL = 2.5, // Clock Low-Level Width
|
| 941 |
|
|
tCK = 10, // Clock Cycle Time
|
| 942 |
|
|
tDH = 0.8, // Data-in Hold Time
|
| 943 |
|
|
tDS = 1.5, // Data-in Setup Time
|
| 944 |
|
|
tCKH = 0.8, // CKE Hold Time
|
| 945 |
|
|
tCKS = 1.5, // CKE Setup Time
|
| 946 |
|
|
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
|
| 947 |
|
|
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
|
| 948 |
|
|
$width (posedge Clk, tCH);
|
| 949 |
|
|
$width (negedge Clk, tCL);
|
| 950 |
|
|
$period (negedge Clk, tCK);
|
| 951 |
|
|
$period (posedge Clk, tCK);
|
| 952 |
|
|
$setuphold(posedge Clk, Cke, tCKS, tCKH);
|
| 953 |
|
|
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
|
| 954 |
|
|
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
|
| 955 |
|
|
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
|
| 956 |
|
|
$setuphold(posedge Clk, We_n, tCMS, tCMH);
|
| 957 |
|
|
$setuphold(posedge Clk, Addr, tAS, tAH);
|
| 958 |
|
|
$setuphold(posedge Clk, Ba, tAS, tAH);
|
| 959 |
|
|
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
|
| 960 |
|
|
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
|
| 961 |
|
|
endspecify
|
| 962 |
|
|
|
| 963 |
|
|
endmodule
|
| 964 |
|
|
|
