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[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [read.me] - Blame information for rev 52

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Line No. Rev Author Line
1 5 dinesha
1. To run SDRM 16 Bit Test
2 45 dinesha
   run_modelsim top SDR_16BITa
3 5 dinesha
   Note: All the logs will be prefixed with SDR_16BBIT
4 45 dinesha
 
5
2. To run SDRAM top 32 Bit Test
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   run_modelsim top SDR_32BIT
7 5 dinesha
   Note: All the logs will be prefixed with SDR_32BBIT
8 45 dinesha
 
9
3. To run SDRM 8 Bit Test
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   run_modelsim top SDR_8BIT
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4. to debug the test in modelsim
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   ./compile_modelsim  
14 5 dinesha
   vsim tb_top &
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16 45 dinesha
5. to complile indipendently
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   ./compile_modelsim  
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6. To run SDRM 16 Bit Test at SDRAM Core level
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   run_modelsim core SDR_16BITa
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   Note: All the logs will be prefixed with SDR_16BBIT
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7. To run SDRAM top 32 Bit Test at SDRAM Core level
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   run_modelsim core SDR_32BIT
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   Note: All the logs will be prefixed with SDR_32BBIT
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8. To run SDRM 8 Bit Test  at SDRAM Core level
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   run_modelsim core SDR_8BIT
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