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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the SDRAM Controller project           ////
////  http://www.opencores.org/cores/sdr_ctrl/                    ////
////                                                              ////
////  Description                                                 ////
////  SDRAM CTRL definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
//   Version  :0.1 - Test Bench automation is improvised with     ////
//             seperate data,address,burst length fifo.           ////
//             Now user can create different write and            ////
//             read sequence                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// This testbench stand-alone verify the sdram core
 
`timescale 1ns/1ps
 
module tb_core;
 
parameter P_SYS  = 10;     //    100MHz
 
// General
reg            RESETN;
reg            sdram_clk;
 
initial sdram_clk = 0;
 
always #(P_SYS/2) sdram_clk = !sdram_clk;
 
parameter      dw              = 32;  // data width
parameter      tw              = 8;   // tag id width
parameter      bl              = 5;   // burst_lenght_width
 
//-------------------------------------------
// Application Interface bus
//-------------------------------------------
reg                   app_req            ; // Application Request
reg  [8:0]            app_req_len        ; // Burst Request length
wire                  app_req_ack        ; // Application Request Ack
reg [24:0]            app_req_addr       ; // Application Address
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
reg [dw-1:0]          app_wr_data        ; // Write Data
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
wire                  app_rd_valid       ; // Read Valid
wire                  app_last_rd        ; // Last Read Valid
wire                  app_last_wr        ; // Last Write Valid
wire [dw-1:0]         app_rd_data        ; // Read Data
 
//--------------------------------------------
// SDRAM I/F
//--------------------------------------------
 
`ifdef SDR_32BIT
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [31:0]           sdr_dout           ; // SDRAM Data Out
   wire [31:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [3:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
`elsif SDR_16BIT
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [15:0]           sdr_dout           ; // SDRAM Data Out
   wire [15:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [1:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
`else
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [7:0]           sdr_dout           ; // SDRAM Data Out
   wire [7:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(1.0) pad_clk     = sdram_clk_d;
 
`ifdef SDR_32BIT
 
   sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
`elsif SDR_16BIT
   sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
`else  // 8 BIT SDRAM
   sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
`endif
      // System
          .clk                (sdram_clk          ),
          .reset_n            (RESETN             ),
          .pad_clk            (pad_clk            ),
`ifdef SDR_32BIT
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
`elsif SDR_16BIT
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
`else
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
`endif
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
 
/* Request from app */
          .app_req            (app_req            ),    // Transfer Request
          .app_req_addr       (app_req_addr       ),    // SDRAM Address
          .app_req_len        (app_req_len        ),    // Burst Length (in 16 bit words)
          .app_req_wrap       (1'b0               ),    // Wrap mode request (xfr_len = 4)
          .app_req_wr_n       (app_req_wr_n       ),    // 0 => Write request, 1 => read req
          .app_req_ack        (app_req_ack        ),    // Request has been accepted
 
          .app_wr_data        (app_wr_data        ),
          .app_wr_en_n        (app_wr_en_n        ),
          .app_rd_data        (app_rd_data        ),
          .app_last_rd        (app_last_rd        ),
          .app_last_wr        (app_last_wr        ),
          .app_rd_valid       (app_rd_valid       ),
          .app_wr_next_req    (app_wr_next_req    ),
          .app_req_dma_last   (app_req            ),
 
/* Interface to SDRAMs */
          .sdr_cs_n           (sdr_cs_n           ),
          .sdr_cke            (sdr_cke            ),
          .sdr_ras_n          (sdr_ras_n          ),
          .sdr_cas_n          (sdr_cas_n          ),
          .sdr_we_n           (sdr_we_n           ),
          .sdr_dqm            (sdr_dqm            ),
          .sdr_ba             (sdr_ba             ),
          .sdr_addr           (sdr_addr           ),
          .pad_sdr_din        (Dq                 ),
          .sdr_dout           (sdr_dout           ),
          .sdr_den_n          (sdr_den_n          ),
 
    /* Parameters */
          .sdr_init_done      (sdr_init_done      ),
          .cfg_req_depth      (2'h3               ),            //how many req. buffer should hold
          .cfg_sdr_en         (1'b1               ),
          .cfg_sdr_mode_reg   (12'h033            ),
          .cfg_sdr_tras_d     (4'h4               ),
          .cfg_sdr_trp_d      (4'h2               ),
          .cfg_sdr_trcd_d     (4'h2               ),
          .cfg_sdr_cas        (3'h3               ),
          .cfg_sdr_trcar_d    (4'h7               ),
          .cfg_sdr_twr_d      (4'h1               ),
          .cfg_sdr_rfsh       (12'h100            ), // reduced from 12'hC35
          .cfg_sdr_rfmax      (3'h6               )
 
);
 
 
`ifdef SDR_32BIT
  assign Dq[7:0]    = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]   : 8'hZZ;
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
`elsif SDR_16BIT
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
 
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .casb               (sdr_cas_n          ),
          .web                (sdr_we_n           ),
          .dqm                (sdr_dqm            )
    );
`else
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
`endif
 
//--------------------
// data/address/burst length FIFO
//--------------------
int dfifo[$]; // data fifo
int afifo[$]; // address  fifo
int bfifo[$]; // Burst Length fifo
 
reg [31:0] read_data;
reg [31:0] ErrCnt;
int k;
reg [31:0] StartAddr;
/////////////////////////////////////////////////////////////////////////
// Test Case
/////////////////////////////////////////////////////////////////////////
 
initial begin //{
  ErrCnt          = 0;
   app_req_addr  = 0;
   app_wr_data    = 0;
   app_wr_en_n    = 4'hF;
   app_req_wr_n   = 0;
   app_req        = 0;
   app_req_len    = 0;
 
  RESETN    = 1'h1;
 
 #100
  // Applying reset
  RESETN    = 1'h0;
  #10000;
  // Releasing reset
  RESETN    = 1'h1;
  #1000;
  wait(u_dut.sdr_init_done == 1);
 
  #1000;
  $display("-------------------------------------- ");
  $display(" Case-1: Single Write/Read Case        ");
  $display("-------------------------------------- ");
 
  burst_write(32'h4_0000,8'h4);
 #1000;
  burst_read();
 
  // Repeat one more time to analysis the
  // SDRAM state change for same col/row address
  $display("-------------------------------------- ");
  $display(" Case-2: Repeat same transfer once again ");
  $display("----------------------------------------");
  burst_write(32'h4_0000,8'h4);
  burst_read();
  burst_write(32'h0040_0000,8'h5);
  burst_read();
  $display("----------------------------------------");
  $display(" Case-3 Create a Page Cross Over        ");
  $display("----------------------------------------");
  burst_write(32'h0000_0FF0,8'h8);
  burst_write(32'h0001_0FF4,8'hF);
  burst_write(32'h0002_0FF8,8'hF);
  burst_write(32'h0003_0FFC,8'hF);
  burst_write(32'h0004_0FE0,8'hF);
  burst_write(32'h0005_0FE4,8'hF);
  burst_write(32'h0006_0FE8,8'hF);
  burst_write(32'h0007_0FEC,8'hF);
  burst_write(32'h0008_0FD0,8'hF);
  burst_write(32'h0009_0FD4,8'hF);
  burst_write(32'h000A_0FD8,8'hF);
  burst_write(32'h000B_0FDC,8'hF);
  burst_write(32'h000C_0FC0,8'hF);
  burst_write(32'h000D_0FC4,8'hF);
  burst_write(32'h000E_0FC8,8'hF);
  burst_write(32'h000F_0FCC,8'hF);
  burst_write(32'h0010_0FB0,8'hF);
  burst_write(32'h0011_0FB4,8'hF);
  burst_write(32'h0012_0FB8,8'hF);
  burst_write(32'h0013_0FBC,8'hF);
  burst_write(32'h0014_0FA0,8'hF);
  burst_write(32'h0015_0FA4,8'hF);
  burst_write(32'h0016_0FA8,8'hF);
  burst_write(32'h0017_0FAC,8'hF);
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
  $display("----------------------------------------");
  $display(" Case:4 4 Write & 4 Read                ");
  $display("----------------------------------------");
  burst_write(32'h4_0000,8'h4);
  burst_write(32'h5_0000,8'h5);
  burst_write(32'h6_0000,8'h6);
  burst_write(32'h7_0000,8'h7);
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
  $display("---------------------------------------");
  $display(" Case:5 24 Write & 24 Read With Different Bank and Row ");
  $display("---------------------------------------");
  //----------------------------------------
  // Address Decodeing:
  //  with cfg_col bit configured as: 00
  //    <12 Bit Row> <2 Bit Bank> <8 Bit Column> <2'b00>
  //
  burst_write({12'h000,2'b00,8'h00,2'b00},8'h4);   // Row: 0 Bank : 0
  burst_write({12'h000,2'b01,8'h00,2'b00},8'h5);   // Row: 0 Bank : 1
  burst_write({12'h000,2'b10,8'h00,2'b00},8'h6);   // Row: 0 Bank : 2
  burst_write({12'h000,2'b11,8'h00,2'b00},8'h7);   // Row: 0 Bank : 3
  burst_write({12'h001,2'b00,8'h00,2'b00},8'h4);   // Row: 1 Bank : 0
  burst_write({12'h001,2'b01,8'h00,2'b00},8'h5);   // Row: 1 Bank : 1
  burst_write({12'h001,2'b10,8'h00,2'b00},8'h6);   // Row: 1 Bank : 2
  burst_write({12'h001,2'b11,8'h00,2'b00},8'h7);   // Row: 1 Bank : 3
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
  burst_write({12'h002,2'b00,8'h00,2'b00},8'h4);   // Row: 2 Bank : 0
  burst_write({12'h002,2'b01,8'h00,2'b00},8'h5);   // Row: 2 Bank : 1
  burst_write({12'h002,2'b10,8'h00,2'b00},8'h6);   // Row: 2 Bank : 2
  burst_write({12'h002,2'b11,8'h00,2'b00},8'h7);   // Row: 2 Bank : 3
  burst_write({12'h003,2'b00,8'h00,2'b00},8'h4);   // Row: 3 Bank : 0
  burst_write({12'h003,2'b01,8'h00,2'b00},8'h5);   // Row: 3 Bank : 1
  burst_write({12'h003,2'b10,8'h00,2'b00},8'h6);   // Row: 3 Bank : 2
  burst_write({12'h003,2'b11,8'h00,2'b00},8'h7);   // Row: 3 Bank : 3
 
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
 
  burst_write({12'h002,2'b00,8'h00,2'b00},8'h4);   // Row: 2 Bank : 0
  burst_write({12'h002,2'b01,8'h01,2'b00},8'h5);   // Row: 2 Bank : 1
  burst_write({12'h002,2'b10,8'h02,2'b00},8'h6);   // Row: 2 Bank : 2
  burst_write({12'h002,2'b11,8'h03,2'b00},8'h7);   // Row: 2 Bank : 3
  burst_write({12'h003,2'b00,8'h04,2'b00},8'h4);   // Row: 3 Bank : 0
  burst_write({12'h003,2'b01,8'h05,2'b00},8'h5);   // Row: 3 Bank : 1
  burst_write({12'h003,2'b10,8'h06,2'b00},8'h6);   // Row: 3 Bank : 2
  burst_write({12'h003,2'b11,8'h07,2'b00},8'h7);   // Row: 3 Bank : 3
 
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
  $display("---------------------------------------------------");
  $display(" Case: 6 Random 2 write and 2 read random");
  $display("---------------------------------------------------");
  for(k=0; k < 20; k++) begin
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h0f)+1);
 #100;
 
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h0f)+1);
 #100;
     burst_read();
 #100;
     burst_read();
 #100;
  end
 
 
  #10000;
 
        $display("###############################");
    if(ErrCnt == 0)
        $display("STATUS: SDRAM Write/Read TEST PASSED");
    else
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
        $display("###############################");
 
    $finish;
end
 
 
task burst_write;
input [31:0] Address;
input [7:0]  bl;
int i;
begin
  afifo.push_back(Address);
  bfifo.push_back(bl);
 
   @ (negedge sdram_clk);
   app_req        = 1;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1'b0;
   app_req_addr   = Address[31:2];
   app_req_len    = bl;
   $display("Write Address: %x, Burst Size: %d",Address,bl);
 
   // wait for app_req_ack == 1
   do begin
       @ (posedge sdram_clk);
   end while(app_req_ack == 1'b0);
   @ (negedge sdram_clk);
   app_req           = 0;
 
   for(i=0; i < bl; i++) begin
      app_wr_data        = $random & 32'hFFFFFFFF;
      dfifo.push_back(app_wr_data);
 
      do begin
          @ (posedge sdram_clk);
      end while(app_wr_next_req == 1'b0);
          @ (negedge sdram_clk);
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
   end
   app_req        = 0;
   app_wr_en_n    = 'hx;
   app_req_wr_n   = 'hx;
   app_req_addr   = 'hx;
   app_req_len    = 'hx;
 
 
end
endtask
 
task burst_read;
reg [31:0] Address;
reg [7:0]  bl;
 
int i,j;
reg [31:0]   exp_data;
begin
 
   Address = afifo.pop_front();
   bl      = bfifo.pop_front();
 
   @ (negedge sdram_clk);
   app_req        = 1;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1;
   app_req_addr   = Address[29:2];
   app_req_len    = bl;
 
      // wait for app_req_ack == 1
      do begin
          @ (posedge sdram_clk);
      end while(app_req_ack == 1'b0);
      @ (negedge sdram_clk);
      app_req        = 0;
      app_wr_en_n    = 'hx;
      app_req_wr_n   = 'hx;
      app_req_addr   = 'hx;
      app_req_len    = 'hx;
 
      for(j=0; j < bl; j++) begin
         wait(app_rd_valid == 1);
         exp_data        = dfifo.pop_front(); // Exptected Read Data
         if(app_rd_data !== exp_data) begin
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,exp_data);
             ErrCnt = ErrCnt+1;
         end else begin
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
         end
         @ (posedge sdram_clk);
         @ (negedge sdram_clk);
      end
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	30	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the SDRAM Controller project ////`
5			`//// http://www.opencores.org/cores/sdr_ctrl/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// SDRAM CTRL definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12	43	dinesha	`// Version :0.1 - Test Bench automation is improvised with ////`
13			`// seperate data,address,burst length fifo. ////`
14			`// Now user can create different write and ////`
15			`// read sequence ////`
16	30	dinesha	`//// ////`
17			`//// Author(s): ////`
18			`//// - Dinesh Annayya, dinesha@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46
47			`// This testbench stand-alone verify the sdram core`
48
49			`timescale 1ns/1ps
50
51			`module tb_core;`
52
53			`parameter P_SYS = 10; // 100MHz`
54
55			`// General`
56			`reg RESETN;`
57			`reg sdram_clk;`
58
59			`initial sdram_clk = 0;`
60
61			`always #(P_SYS/2) sdram_clk = !sdram_clk;`
62
63			`parameter dw = 32; // data width`
64			`parameter tw = 8; // tag id width`
65			`parameter bl = 5; // burst_lenght_width`
66
67			`//-------------------------------------------`
68			`// Application Interface bus`
69			`//-------------------------------------------`
70			`reg app_req ; // Application Request`
71			`reg [8:0] app_req_len ; // Burst Request length`
72			`wire app_req_ack ; // Application Request Ack`
73	56	dinesha	`reg [24:0] app_req_addr ; // Application Address`
74	30	dinesha	`reg app_req_wr_n ; // 1 -> Read, 0 -> Write`
75			`reg [dw-1:0] app_wr_data ; // Write Data`
76			`reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low`
77			`wire app_rd_valid ; // Read Valid`
78			`wire app_last_rd ; // Last Read Valid`
79	46	dinesha	`wire app_last_wr ; // Last Write Valid`
80	30	dinesha	`wire [dw-1:0] app_rd_data ; // Read Data`
81
82			`//--------------------------------------------`
83			`// SDRAM I/F`
84			`//--------------------------------------------`
85
86			`ifdef SDR_32BIT
87			`wire [31:0] Dq ; // SDRAM Read/Write Data Bus`
88			`wire [31:0] sdr_dout ; // SDRAM Data Out`
89			`wire [31:0] pad_sdr_din ; // SDRAM Data Input`
90			`wire [3:0] sdr_den_n ; // SDRAM Data Enable`
91			`wire [3:0] sdr_dqm ; // SDRAM DATA Mask`
92			`elsif SDR_16BIT
93			`wire [15:0] Dq ; // SDRAM Read/Write Data Bus`
94			`wire [15:0] sdr_dout ; // SDRAM Data Out`
95			`wire [15:0] pad_sdr_din ; // SDRAM Data Input`
96			`wire [1:0] sdr_den_n ; // SDRAM Data Enable`
97			`wire [1:0] sdr_dqm ; // SDRAM DATA Mask`
98			`else
99			`wire [7:0] Dq ; // SDRAM Read/Write Data Bus`
100			`wire [7:0] sdr_dout ; // SDRAM Data Out`
101			`wire [7:0] pad_sdr_din ; // SDRAM Data Input`
102			`wire [0:0] sdr_den_n ; // SDRAM Data Enable`
103			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
104			`endif
105
106			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
107			`wire [11:0] sdr_addr ; // SDRAM ADRESS`
108			`wire sdr_init_done ; // SDRAM Init Done`
109
110			`// to fix the sdram interface timing issue`
111			`wire #(2.0) sdram_clk_d = sdram_clk;`
112			`wire #(1.0) pad_clk = sdram_clk_d;`
113
114			`ifdef SDR_32BIT
115
116			`sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(`
117			`elsif SDR_16BIT
118			`sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(`
119			`else // 8 BIT SDRAM
120			`sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(`
121			`endif
122			`// System`
123			`.clk (sdram_clk ),`
124			`.reset_n (RESETN ),`
125			`.pad_clk (pad_clk ),`
126			`ifdef SDR_32BIT
127			`.sdr_width (2'b00 ), // 32 BIT SDRAM`
128			`elsif SDR_16BIT
129			`.sdr_width (2'b01 ), // 16 BIT SDRAM`
130			`else
131			`.sdr_width (2'b10 ), // 8 BIT SDRAM`
132			`endif
133			`.cfg_colbits (2'b00 ), // 8 Bit Column Address`
134
135
136			`/* Request from app */`
137			`.app_req (app_req ), // Transfer Request`
138			`.app_req_addr (app_req_addr ), // SDRAM Address`
139			`.app_req_len (app_req_len ), // Burst Length (in 16 bit words)`
140			`.app_req_wrap (1'b0 ), // Wrap mode request (xfr_len = 4)`
141			`.app_req_wr_n (app_req_wr_n ), // 0 => Write request, 1 => read req`
142			`.app_req_ack (app_req_ack ), // Request has been accepted`
143
144			`.app_wr_data (app_wr_data ),`
145			`.app_wr_en_n (app_wr_en_n ),`
146			`.app_rd_data (app_rd_data ),`
147			`.app_last_rd (app_last_rd ),`
148	46	dinesha	`.app_last_wr (app_last_wr ),`
149	30	dinesha	`.app_rd_valid (app_rd_valid ),`
150			`.app_wr_next_req (app_wr_next_req ),`
151			`.app_req_dma_last (app_req ),`
152
153			`/* Interface to SDRAMs */`
154			`.sdr_cs_n (sdr_cs_n ),`
155			`.sdr_cke (sdr_cke ),`
156			`.sdr_ras_n (sdr_ras_n ),`
157			`.sdr_cas_n (sdr_cas_n ),`
158			`.sdr_we_n (sdr_we_n ),`
159			`.sdr_dqm (sdr_dqm ),`
160			`.sdr_ba (sdr_ba ),`
161			`.sdr_addr (sdr_addr ),`
162			`.pad_sdr_din (Dq ),`
163			`.sdr_dout (sdr_dout ),`
164			`.sdr_den_n (sdr_den_n ),`
165
166			`/* Parameters */`
167			`.sdr_init_done (sdr_init_done ),`
168	44	dinesha	`.cfg_req_depth (2'h3 ), //how many req. buffer should hold`
169	30	dinesha	`.cfg_sdr_en (1'b1 ),`
170			`.cfg_sdr_mode_reg (12'h033 ),`
171			`.cfg_sdr_tras_d (4'h4 ),`
172			`.cfg_sdr_trp_d (4'h2 ),`
173			`.cfg_sdr_trcd_d (4'h2 ),`
174			`.cfg_sdr_cas (3'h3 ),`
175			`.cfg_sdr_trcar_d (4'h7 ),`
176			`.cfg_sdr_twr_d (4'h1 ),`
177	45	dinesha	`.cfg_sdr_rfsh (12'h100 ), // reduced from 12'hC35`
178	30	dinesha	`.cfg_sdr_rfmax (3'h6 )`
179
180			`);`
181
182
183			`ifdef SDR_32BIT
184			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
185			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
186			`assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;`
187			`assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;`
188			`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`
189			`.Dq (Dq ) ,`
190			`.Addr (sdr_addr ),`
191			`.Ba (sdr_ba ),`
192			`.Clk (sdram_clk_d ),`
193			`.Cke (sdr_cke ),`
194			`.Cs_n (sdr_cs_n ),`
195			`.Ras_n (sdr_ras_n ),`
196			`.Cas_n (sdr_cas_n ),`
197			`.We_n (sdr_we_n ),`
198			`.Dqm (sdr_dqm )`
199			`);`
200
201			`elsif SDR_16BIT
202
203			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
204			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
205
206			`IS42VM16400K u_sdram16 (`
207			`.dq (Dq ),`
208			`.addr (sdr_addr ),`
209			`.ba (sdr_ba ),`
210			`.clk (sdram_clk_d ),`
211			`.cke (sdr_cke ),`
212			`.csb (sdr_cs_n ),`
213			`.rasb (sdr_ras_n ),`
214			`.casb (sdr_cas_n ),`
215			`.web (sdr_we_n ),`
216			`.dqm (sdr_dqm )`
217			`);`
218			`else
219
220			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
221
222			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
223			`.Dq (Dq ) ,`
224			`.Addr (sdr_addr ),`
225			`.Ba (sdr_ba ),`
226			`.Clk (sdram_clk_d ),`
227			`.Cke (sdr_cke ),`
228			`.Cs_n (sdr_cs_n ),`
229			`.Ras_n (sdr_ras_n ),`
230			`.Cas_n (sdr_cas_n ),`
231			`.We_n (sdr_we_n ),`
232			`.Dqm (sdr_dqm )`
233			`);`
234			`endif
235
236			`//--------------------`
237	43	dinesha	`// data/address/burst length FIFO`
238	30	dinesha	`//--------------------`
239	43	dinesha	`int dfifo[$]; // data fifo`
240			`int afifo[$]; // address fifo`
241			`int bfifo[$]; // Burst Length fifo`
242	30	dinesha
243			`reg [31:0] read_data;`
244			`reg [31:0] ErrCnt;`
245			`int k;`
246			`reg [31:0] StartAddr;`
247			`/////////////////////////////////////////////////////////////////////////`
248			`// Test Case`
249			`/////////////////////////////////////////////////////////////////////////`
250
251			`initial begin //{`
252			`ErrCnt = 0;`
253			`app_req_addr = 0;`
254			`app_wr_data = 0;`
255			`app_wr_en_n = 4'hF;`
256			`app_req_wr_n = 0;`
257			`app_req = 0;`
258			`app_req_len = 0;`
259
260			`RESETN = 1'h1;`
261
262			`#100`
263			`// Applying reset`
264			`RESETN = 1'h0;`
265			`#10000;`
266			`// Releasing reset`
267			`RESETN = 1'h1;`
268			`#1000;`
269			`wait(u_dut.sdr_init_done == 1);`
270
271			`#1000;`
272	46	dinesha	`$display("-------------------------------------- ");`
273			`$display(" Case-1: Single Write/Read Case ");`
274			`$display("-------------------------------------- ");`
275
276			`burst_write(32'h4_0000,8'h4);`
277	30	dinesha	`#1000;`
278	43	dinesha	`burst_read();`
279	30	dinesha
280	46	dinesha	`// Repeat one more time to analysis the`
281			`// SDRAM state change for same col/row address`
282			`$display("-------------------------------------- ");`
283			`$display(" Case-2: Repeat same transfer once again ");`
284			`$display("----------------------------------------");`
285			`burst_write(32'h4_0000,8'h4);`
286	43	dinesha	`burst_read();`
287	46	dinesha	`burst_write(32'h0040_0000,8'h5);`
288			`burst_read();`
289			`$display("----------------------------------------");`
290			`$display(" Case-3 Create a Page Cross Over ");`
291			`$display("----------------------------------------");`
292	53	dinesha	`burst_write(32'h0000_0FF0,8'h8);`
293			`burst_write(32'h0001_0FF4,8'hF);`
294			`burst_write(32'h0002_0FF8,8'hF);`
295			`burst_write(32'h0003_0FFC,8'hF);`
296			`burst_write(32'h0004_0FE0,8'hF);`
297			`burst_write(32'h0005_0FE4,8'hF);`
298			`burst_write(32'h0006_0FE8,8'hF);`
299			`burst_write(32'h0007_0FEC,8'hF);`
300			`burst_write(32'h0008_0FD0,8'hF);`
301			`burst_write(32'h0009_0FD4,8'hF);`
302			`burst_write(32'h000A_0FD8,8'hF);`
303			`burst_write(32'h000B_0FDC,8'hF);`
304			`burst_write(32'h000C_0FC0,8'hF);`
305			`burst_write(32'h000D_0FC4,8'hF);`
306			`burst_write(32'h000E_0FC8,8'hF);`
307			`burst_write(32'h000F_0FCC,8'hF);`
308			`burst_write(32'h0010_0FB0,8'hF);`
309			`burst_write(32'h0011_0FB4,8'hF);`
310			`burst_write(32'h0012_0FB8,8'hF);`
311			`burst_write(32'h0013_0FBC,8'hF);`
312			`burst_write(32'h0014_0FA0,8'hF);`
313			`burst_write(32'h0015_0FA4,8'hF);`
314			`burst_write(32'h0016_0FA8,8'hF);`
315			`burst_write(32'h0017_0FAC,8'hF);`
316	43	dinesha	`burst_read();`
317			`burst_read();`
318	53	dinesha	`burst_read();`
319			`burst_read();`
320			`burst_read();`
321			`burst_read();`
322			`burst_read();`
323			`burst_read();`
324			`burst_read();`
325			`burst_read();`
326			`burst_read();`
327			`burst_read();`
328			`burst_read();`
329			`burst_read();`
330			`burst_read();`
331			`burst_read();`
332			`burst_read();`
333			`burst_read();`
334			`burst_read();`
335			`burst_read();`
336			`burst_read();`
337			`burst_read();`
338			`burst_read();`
339			`burst_read();`
340	49	dinesha
341	46	dinesha	`$display("----------------------------------------");`
342			`$display(" Case:4 4 Write & 4 Read ");`
343			`$display("----------------------------------------");`
344			`burst_write(32'h4_0000,8'h4);`
345			`burst_write(32'h5_0000,8'h5);`
346			`burst_write(32'h6_0000,8'h6);`
347			`burst_write(32'h7_0000,8'h7);`
348	43	dinesha	`burst_read();`
349			`burst_read();`
350	46	dinesha	`burst_read();`
351			`burst_read();`
352	43	dinesha
353	46	dinesha	`$display("---------------------------------------");`
354	53	dinesha	`$display(" Case:5 24 Write & 24 Read With Different Bank and Row ");`
355	46	dinesha	`$display("---------------------------------------");`
356			`//----------------------------------------`
357			`// Address Decodeing:`
358			`// with cfg_col bit configured as: 00`
359			`// <12 Bit Row> <2 Bit Bank> <8 Bit Column> <2'b00>`
360			`//`
361			`burst_write({12'h000,2'b00,8'h00,2'b00},8'h4); // Row: 0 Bank : 0`
362			`burst_write({12'h000,2'b01,8'h00,2'b00},8'h5); // Row: 0 Bank : 1`
363			`burst_write({12'h000,2'b10,8'h00,2'b00},8'h6); // Row: 0 Bank : 2`
364			`burst_write({12'h000,2'b11,8'h00,2'b00},8'h7); // Row: 0 Bank : 3`
365			`burst_write({12'h001,2'b00,8'h00,2'b00},8'h4); // Row: 1 Bank : 0`
366			`burst_write({12'h001,2'b01,8'h00,2'b00},8'h5); // Row: 1 Bank : 1`
367			`burst_write({12'h001,2'b10,8'h00,2'b00},8'h6); // Row: 1 Bank : 2`
368			`burst_write({12'h001,2'b11,8'h00,2'b00},8'h7); // Row: 1 Bank : 3`
369			`burst_read();`
370			`burst_read();`
371			`burst_read();`
372			`burst_read();`
373			`burst_read();`
374			`burst_read();`
375			`burst_read();`
376			`burst_read();`
377	43	dinesha
378	46	dinesha	`burst_write({12'h002,2'b00,8'h00,2'b00},8'h4); // Row: 2 Bank : 0`
379			`burst_write({12'h002,2'b01,8'h00,2'b00},8'h5); // Row: 2 Bank : 1`
380			`burst_write({12'h002,2'b10,8'h00,2'b00},8'h6); // Row: 2 Bank : 2`
381			`burst_write({12'h002,2'b11,8'h00,2'b00},8'h7); // Row: 2 Bank : 3`
382			`burst_write({12'h003,2'b00,8'h00,2'b00},8'h4); // Row: 3 Bank : 0`
383			`burst_write({12'h003,2'b01,8'h00,2'b00},8'h5); // Row: 3 Bank : 1`
384			`burst_write({12'h003,2'b10,8'h00,2'b00},8'h6); // Row: 3 Bank : 2`
385			`burst_write({12'h003,2'b11,8'h00,2'b00},8'h7); // Row: 3 Bank : 3`
386	43	dinesha
387	46	dinesha	`burst_read();`
388			`burst_read();`
389			`burst_read();`
390			`burst_read();`
391			`burst_read();`
392			`burst_read();`
393			`burst_read();`
394			`burst_read();`
395
396	53	dinesha
397			`burst_write({12'h002,2'b00,8'h00,2'b00},8'h4); // Row: 2 Bank : 0`
398			`burst_write({12'h002,2'b01,8'h01,2'b00},8'h5); // Row: 2 Bank : 1`
399			`burst_write({12'h002,2'b10,8'h02,2'b00},8'h6); // Row: 2 Bank : 2`
400			`burst_write({12'h002,2'b11,8'h03,2'b00},8'h7); // Row: 2 Bank : 3`
401			`burst_write({12'h003,2'b00,8'h04,2'b00},8'h4); // Row: 3 Bank : 0`
402			`burst_write({12'h003,2'b01,8'h05,2'b00},8'h5); // Row: 3 Bank : 1`
403			`burst_write({12'h003,2'b10,8'h06,2'b00},8'h6); // Row: 3 Bank : 2`
404			`burst_write({12'h003,2'b11,8'h07,2'b00},8'h7); // Row: 3 Bank : 3`
405
406			`burst_read();`
407			`burst_read();`
408			`burst_read();`
409			`burst_read();`
410			`burst_read();`
411			`burst_read();`
412			`burst_read();`
413			`burst_read();`
414
415	46	dinesha	`$display("---------------------------------------------------");`
416			`$display(" Case: 6 Random 2 write and 2 read random");`
417			`$display("---------------------------------------------------");`
418	30	dinesha	`for(k=0; k < 20; k++) begin`
419	43	dinesha	`StartAddr = $random & 32'h003FFFFF;`
420	53	dinesha	`burst_write(StartAddr,($random & 8'h0f)+1);`
421	43	dinesha	`#100;`
422
423			`StartAddr = $random & 32'h003FFFFF;`
424	53	dinesha	`burst_write(StartAddr,($random & 8'h0f)+1);`
425	43	dinesha	`#100;`
426			`burst_read();`
427			`#100;`
428			`burst_read();`
429			`#100;`
430	30	dinesha	`end`
431
432
433			`#10000;`
434
435			`$display("###############################");`
436			`if(ErrCnt == 0)`
437			`$display("STATUS: SDRAM Write/Read TEST PASSED");`
438			`else`
439			`$display("ERROR: SDRAM Write/Read TEST FAILED");`
440			`$display("###############################");`
441
442			`$finish;`
443			`end`
444
445	43	dinesha
446	30	dinesha	`task burst_write;`
447			`input [31:0] Address;`
448	43	dinesha	`input [7:0] bl;`
449	30	dinesha	`int i;`
450			`begin`
451	43	dinesha	`afifo.push_back(Address);`
452			`bfifo.push_back(bl);`
453
454	30	dinesha	`@ (negedge sdram_clk);`
455			`app_req = 1;`
456			`app_wr_en_n = 0;`
457			`app_req_wr_n = 1'b0;`
458	43	dinesha	`app_req_addr = Address[31:2];`
459			`app_req_len = bl;`
460			`$display("Write Address: %x, Burst Size: %d",Address,bl);`
461	30	dinesha
462			`// wait for app_req_ack == 1`
463			`do begin`
464			`@ (posedge sdram_clk);`
465			`end while(app_req_ack == 1'b0);`
466			`@ (negedge sdram_clk);`
467			`app_req = 0;`
468
469	43	dinesha	`for(i=0; i < bl; i++) begin`
470			`app_wr_data = $random & 32'hFFFFFFFF;`
471			`dfifo.push_back(app_wr_data);`
472	30	dinesha
473			`do begin`
474			`@ (posedge sdram_clk);`
475			`end while(app_wr_next_req == 1'b0);`
476			`@ (negedge sdram_clk);`
477
478			`$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);`
479			`end`
480	56	dinesha	`app_req = 0;`
481			`app_wr_en_n = 'hx;`
482			`app_req_wr_n = 'hx;`
483			`app_req_addr = 'hx;`
484			`app_req_len = 'hx;`
485	43	dinesha
486
487	30	dinesha	`end`
488			`endtask`
489
490			`task burst_read;`
491	43	dinesha	`reg [31:0] Address;`
492			`reg [7:0] bl;`
493	30	dinesha
494			`int i,j;`
495	43	dinesha	`reg [31:0] exp_data;`
496	30	dinesha	`begin`
497	43	dinesha
498			`Address = afifo.pop_front();`
499			`bl = bfifo.pop_front();`
500	30	dinesha

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