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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the SDRAM Controller project           ////
////  http://www.opencores.org/cores/sdr_ctrl/                    ////
////                                                              ////
////  Description                                                 ////
////  SDRAM CTRL definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/1ps
 
// This testbench verify with SDRAM TOP
 
module tb_top;
 
parameter P_SYS  = 10;     //    100MHz
 
// General
reg            RESETN;
reg            sdram_clk;
 
initial sdram_clk = 0;
 
always #(P_SYS/2) sdram_clk = !sdram_clk;
 
parameter      dw              = 32;  // data width
parameter      tw              = 8;   // tag id width
parameter      bl              = 5;   // burst_lenght_width
 
//-------------------------------------------
// Application Interface bus
//-------------------------------------------
reg                   app_req            ; // Application Request
reg  [8:0]            app_req_len        ; // Burst Request length
wire                  app_req_ack        ; // Application Request Ack
reg [29:0]            app_req_addr       ; // Application Address
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
reg [dw-1:0]          app_wr_data        ; // Write Data
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
wire                  app_rd_valid       ; // Read Valid
wire [dw-1:0]         app_rd_data        ; // Read Data
 
//--------------------------------------------
// SDRAM I/F
//--------------------------------------------
 
`ifdef SDR_32BIT
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [31:0]           sdr_dout           ; // SDRAM Data Out
   wire [31:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [3:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
`elsif SDR_16BIT
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [15:0]           sdr_dout           ; // SDRAM Data Out
   wire [15:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [1:0]            sdr_den_n          ; // SDRAM Data Enable
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
`else
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [7:0]           sdr_dout           ; // SDRAM Data Out
   wire [7:0]           pad_sdr_din        ; // SDRAM Data Input
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(1.0) pad_clk     = sdram_clk_d;
 
`ifdef SDR_32BIT
 
   sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
`elsif SDR_16BIT
   sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
`else  // 8 BIT SDRAM
   sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
`endif
      // System
          .clk                (sdram_clk          ),
          .reset_n            (RESETN             ),
          .pad_clk            (pad_clk            ),
`ifdef SDR_32BIT
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
`elsif SDR_16BIT
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
`else
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
`endif
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
 
/* Request from app */
          .app_req            (app_req            ),    // Transfer Request
          .app_req_addr       (app_req_addr       ),    // SDRAM Address
          .app_req_addr_mask  (29'h1FFF_FFFF      ),    // Address mask for queue wrap
          .app_req_len        (app_req_len        ),    // Burst Length (in 16 bit words)
          .app_req_wrap       (1'b0               ),    // Wrap mode request (xfr_len = 4)
          .app_req_wr_n       (app_req_wr_n       ),    // 0 => Write request, 1 => read req
          .app_req_ack        (app_req_ack        ),    // Request has been accepted
          .sdr_core_busy_n    (                   ),    // OK to arbitrate next request
 
          .app_wr_data        (app_wr_data        ),
          .app_wr_en_n        (app_wr_en_n        ),
          .app_rd_data        (app_rd_data        ),
          .app_rd_valid       (app_rd_valid       ),
          .app_wr_next_req    (app_wr_next_req    ),
          .app_req_dma_last   (app_req            ),
 
/* Interface to SDRAMs */
          .sdr_cs_n           (sdr_cs_n           ),
          .sdr_cke            (sdr_cke            ),
          .sdr_ras_n          (sdr_ras_n          ),
          .sdr_cas_n          (sdr_cas_n          ),
          .sdr_we_n           (sdr_we_n           ),
          .sdr_dqm            (sdr_dqm            ),
          .sdr_ba             (sdr_ba             ),
          .sdr_addr           (sdr_addr           ),
          .pad_sdr_din        (Dq                 ),
          .sdr_dout           (sdr_dout           ),
          .sdr_den_n          (sdr_den_n          ),
 
    /* Parameters */
          .sdr_init_done      (sdr_init_done      ),
          .cfg_req_depth      (2'h2               ),            //how many req. buffer should hold
          .cfg_sdr_en         (1'b1               ),
          .cfg_sdr_mode_reg   (12'h033            ),
          .cfg_sdr_tras_d     (4'h4               ),
          .cfg_sdr_trp_d      (4'h2               ),
          .cfg_sdr_trcd_d     (4'h2               ),
          .cfg_sdr_cas        (3'h3               ),
          .cfg_sdr_trcar_d    (4'h7               ),
          .cfg_sdr_twr_d      (4'h1               ),
          .cfg_sdr_rfsh       (12'hC35            ),
          .cfg_sdr_rfmax      (3'h6               )
 
);
 
 
`ifdef SDR_32BIT
  assign Dq[7:0]    = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]   : 8'hZZ;
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
`elsif SDR_16BIT
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
 
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .casb               (sdr_cas_n          ),
          .web                (sdr_we_n           ),
          .dqm                (sdr_dqm            )
    );
`else
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
`endif
 
//--------------------
// Write/Read Burst FIFO
//--------------------
int wrdfifo[$]; // write data fifo
int rddfifo[$]; // read data fifo
 
reg [31:0] read_data;
reg [31:0] ErrCnt;
int k;
reg [31:0] StartAddr;
/////////////////////////////////////////////////////////////////////////
// Test Case
/////////////////////////////////////////////////////////////////////////
 
initial begin //{
  ErrCnt          = 0;
   app_req_addr  = 0;
   app_wr_data    = 0;
   app_wr_en_n    = 4'hF;
   app_req_wr_n   = 0;
   app_req        = 0;
   app_req_len    = 0;
 
  RESETN    = 1'h1;
 
 #100
  // Applying reset
  RESETN    = 1'h0;
  #10000;
  // Releasing reset
  RESETN    = 1'h1;
  #1000;
  wait(u_dut.sdr_init_done == 1);
 
  #1000;
 
  wrdfifo.push_back(32'h11223344);
  wrdfifo.push_back(32'h22334455);
  wrdfifo.push_back(32'h33445566);
  wrdfifo.push_back(32'h44556677);
  wrdfifo.push_back(32'h55667788);
 
  burst_write(32'h40000);
 #1000;
  burst_read(32'h40000);
 
 #1000;
  burst_write(32'h7000_0000);
 #1000;
  burst_read(32'h7000_0000);
 
  for(k=0; k < 20; k++) begin
     StartAddr = $random & 32'h07FFFFFF;
     burst_write(StartAddr);
    #1000;
     burst_read(StartAddr);
  end
 
 
  #10000;
 
        $display("###############################");
    if(ErrCnt == 0)
        $display("STATUS: SDRAM Write/Read TEST PASSED");
    else
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
        $display("###############################");
 
    $finish;
end
 
task burst_write;
input [31:0] Address;
int i;
begin
   @ (negedge sdram_clk);
   app_req        = 1;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1'b0;
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
   app_req_addr  = Address[31:2];
   app_req_len    = wrdfifo.size;
 
   // wait for app_req_ack == 1
   do begin
       @ (posedge sdram_clk);
   end while(app_req_ack == 1'b0);
   @ (negedge sdram_clk);
   app_req           = 0;
 
   for(i=0; i < wrdfifo.size; i++) begin
      app_wr_data     = wrdfifo[i];
 
      do begin
          @ (posedge sdram_clk);
      end while(app_wr_next_req == 1'b0);
          @ (negedge sdram_clk);
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
   end
   app_req           = 0;
   app_wr_en_n       = 4'hF;
end
endtask
 
task burst_read;
input [31:0] Address;
 
int i,j;
reg [31:0]   rd_data;
begin
   @ (negedge sdram_clk);
 
      app_req        = 1;
      app_wr_en_n    = 0;
      app_req_wr_n   = 1;
      app_req_addr   = Address[29:2];
      app_req_len    = wrdfifo.size;
      // wait for app_req_ack == 1
      do begin
          @ (posedge sdram_clk);
      end while(app_req_ack == 1'b0);
      @ (negedge sdram_clk);
      app_req           = 0;
 
      for(j=0; j < wrdfifo.size; j++) begin
         wait(app_rd_valid == 1);
         if(app_rd_data !== wrdfifo[j]) begin
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
             ErrCnt = ErrCnt+1;
         end else begin
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
         end
         @ (posedge sdram_clk);
         @ (negedge sdram_clk);
      end
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	8	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the SDRAM Controller project ////`
5			`//// http://www.opencores.org/cores/sdr_ctrl/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// SDRAM CTRL definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12			`//// ////`
13			`//// Author(s): ////`
14			`//// - Dinesh Annayya, dinesha@opencores.org ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43
44			`timescale 1ns/1ps
45
46	24	dinesha	`// This testbench verify with SDRAM TOP`
47
48	8	dinesha	`module tb_top;`
49
50			`parameter P_SYS = 10; // 100MHz`
51
52			`// General`
53			`reg RESETN;`
54			`reg sdram_clk;`
55
56			`initial sdram_clk = 0;`
57
58			`always #(P_SYS/2) sdram_clk = !sdram_clk;`
59
60			`parameter dw = 32; // data width`
61			`parameter tw = 8; // tag id width`
62			`parameter bl = 5; // burst_lenght_width`
63
64			`//-------------------------------------------`
65			`// Application Interface bus`
66			`//-------------------------------------------`
67			`reg app_req ; // Application Request`
68			`reg [8:0] app_req_len ; // Burst Request length`
69			`wire app_req_ack ; // Application Request Ack`
70			`reg [29:0] app_req_addr ; // Application Address`
71			`reg app_req_wr_n ; // 1 -> Read, 0 -> Write`
72			`reg [dw-1:0] app_wr_data ; // Write Data`
73			`reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low`
74			`wire app_rd_valid ; // Read Valid`
75			`wire [dw-1:0] app_rd_data ; // Read Data`
76
77			`//--------------------------------------------`
78			`// SDRAM I/F`
79			`//--------------------------------------------`
80
81			`ifdef SDR_32BIT
82			`wire [31:0] Dq ; // SDRAM Read/Write Data Bus`
83			`wire [31:0] sdr_dout ; // SDRAM Data Out`
84			`wire [31:0] pad_sdr_din ; // SDRAM Data Input`
85			`wire [3:0] sdr_den_n ; // SDRAM Data Enable`
86			`wire [3:0] sdr_dqm ; // SDRAM DATA Mask`
87	18	dinesha	`elsif SDR_16BIT
88	8	dinesha	`wire [15:0] Dq ; // SDRAM Read/Write Data Bus`
89			`wire [15:0] sdr_dout ; // SDRAM Data Out`
90			`wire [15:0] pad_sdr_din ; // SDRAM Data Input`
91			`wire [1:0] sdr_den_n ; // SDRAM Data Enable`
92			`wire [1:0] sdr_dqm ; // SDRAM DATA Mask`
93	18	dinesha	`else
94			`wire [7:0] Dq ; // SDRAM Read/Write Data Bus`
95			`wire [7:0] sdr_dout ; // SDRAM Data Out`
96			`wire [7:0] pad_sdr_din ; // SDRAM Data Input`
97			`wire [0:0] sdr_den_n ; // SDRAM Data Enable`
98			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
99	8	dinesha	`endif
100
101			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
102			`wire [11:0] sdr_addr ; // SDRAM ADRESS`
103			`wire sdr_init_done ; // SDRAM Init Done`
104
105			`// to fix the sdram interface timing issue`
106	22	dinesha	`wire #(2.0) sdram_clk_d = sdram_clk;`
107			`wire #(1.0) pad_clk = sdram_clk_d;`
108	8	dinesha
109			`ifdef SDR_32BIT
110
111			`sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(`
112	18	dinesha	`elsif SDR_16BIT
113	8	dinesha	`sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(`
114	18	dinesha	`else // 8 BIT SDRAM
115			`sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(`
116	8	dinesha	`endif
117			`// System`
118	22	dinesha	`.clk (sdram_clk ),`
119	8	dinesha	`.reset_n (RESETN ),`
120	22	dinesha	`.pad_clk (pad_clk ),`
121	8	dinesha	`ifdef SDR_32BIT
122	18	dinesha	`.sdr_width (2'b00 ), // 32 BIT SDRAM`
123			`elsif SDR_16BIT
124			`.sdr_width (2'b01 ), // 16 BIT SDRAM`
125			`else
126			`.sdr_width (2'b10 ), // 8 BIT SDRAM`
127	8	dinesha	`endif
128	12	dinesha	`.cfg_colbits (2'b00 ), // 8 Bit Column Address`
129	8	dinesha
130
131			`/* Request from app */`
132			`.app_req (app_req ), // Transfer Request`
133			`.app_req_addr (app_req_addr ), // SDRAM Address`
134			`.app_req_addr_mask (29'h1FFF_FFFF ), // Address mask for queue wrap`
135			`.app_req_len (app_req_len ), // Burst Length (in 16 bit words)`
136			`.app_req_wrap (1'b0 ), // Wrap mode request (xfr_len = 4)`
137			`.app_req_wr_n (app_req_wr_n ), // 0 => Write request, 1 => read req`
138			`.app_req_ack (app_req_ack ), // Request has been accepted`
139			`.sdr_core_busy_n ( ), // OK to arbitrate next request`
140
141			`.app_wr_data (app_wr_data ),`
142			`.app_wr_en_n (app_wr_en_n ),`
143			`.app_rd_data (app_rd_data ),`
144			`.app_rd_valid (app_rd_valid ),`
145			`.app_wr_next_req (app_wr_next_req ),`
146			`.app_req_dma_last (app_req ),`
147
148			`/* Interface to SDRAMs */`
149			`.sdr_cs_n (sdr_cs_n ),`
150			`.sdr_cke (sdr_cke ),`
151			`.sdr_ras_n (sdr_ras_n ),`
152			`.sdr_cas_n (sdr_cas_n ),`
153			`.sdr_we_n (sdr_we_n ),`
154			`.sdr_dqm (sdr_dqm ),`
155			`.sdr_ba (sdr_ba ),`
156			`.sdr_addr (sdr_addr ),`
157			`.pad_sdr_din (Dq ),`
158			`.sdr_dout (sdr_dout ),`
159			`.sdr_den_n (sdr_den_n ),`
160
161			`/* Parameters */`
162			`.sdr_init_done (sdr_init_done ),`
163			`.cfg_req_depth (2'h2 ), //how many req. buffer should hold`
164			`.cfg_sdr_en (1'b1 ),`
165			`.cfg_sdr_mode_reg (12'h033 ),`
166			`.cfg_sdr_tras_d (4'h4 ),`
167			`.cfg_sdr_trp_d (4'h2 ),`
168			`.cfg_sdr_trcd_d (4'h2 ),`
169	22	dinesha	`.cfg_sdr_cas (3'h3 ),`
170	8	dinesha	`.cfg_sdr_trcar_d (4'h7 ),`
171			`.cfg_sdr_twr_d (4'h1 ),`
172			`.cfg_sdr_rfsh (12'hC35 ),`
173			`.cfg_sdr_rfmax (3'h6 )`
174
175			`);`
176
177
178			`ifdef SDR_32BIT
179			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
180			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
181			`assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;`
182			`assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;`
183			`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`
184			`.Dq (Dq ) ,`
185			`.Addr (sdr_addr ),`
186			`.Ba (sdr_ba ),`
187	22	dinesha	`.Clk (sdram_clk_d ),`
188	8	dinesha	`.Cke (sdr_cke ),`
189			`.Cs_n (sdr_cs_n ),`
190			`.Ras_n (sdr_ras_n ),`
191			`.Cas_n (sdr_cas_n ),`
192			`.We_n (sdr_we_n ),`
193			`.Dqm (sdr_dqm )`
194			`);`
195
196	18	dinesha	`elsif SDR_16BIT
197	8	dinesha
198			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
199			`assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;`
200
201			`IS42VM16400K u_sdram16 (`
202			`.dq (Dq ),`
203			`.addr (sdr_addr ),`
204			`.ba (sdr_ba ),`
205	22	dinesha	`.clk (sdram_clk_d ),`
206	8	dinesha	`.cke (sdr_cke ),`
207			`.csb (sdr_cs_n ),`
208			`.rasb (sdr_ras_n ),`
209			`.casb (sdr_cas_n ),`
210			`.web (sdr_we_n ),`
211			`.dqm (sdr_dqm )`
212			`);`
213	18	dinesha	`else
214
215			`assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;`
216
217			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
218			`.Dq (Dq ) ,`
219			`.Addr (sdr_addr ),`
220			`.Ba (sdr_ba ),`
221	22	dinesha	`.Clk (sdram_clk_d ),`
222	18	dinesha	`.Cke (sdr_cke ),`
223			`.Cs_n (sdr_cs_n ),`
224			`.Ras_n (sdr_ras_n ),`
225			`.Cas_n (sdr_cas_n ),`
226			`.We_n (sdr_we_n ),`
227			`.Dqm (sdr_dqm )`
228			`);`
229	8	dinesha	`endif
230
231			`//--------------------`
232			`// Write/Read Burst FIFO`
233			`//--------------------`
234			`int wrdfifo[$]; // write data fifo`
235			`int rddfifo[$]; // read data fifo`
236
237			`reg [31:0] read_data;`
238			`reg [31:0] ErrCnt;`
239			`int k;`
240			`reg [31:0] StartAddr;`
241			`/////////////////////////////////////////////////////////////////////////`
242			`// Test Case`
243			`/////////////////////////////////////////////////////////////////////////`
244
245			`initial begin //{`
246			`ErrCnt = 0;`
247			`app_req_addr = 0;`
248			`app_wr_data = 0;`
249			`app_wr_en_n = 4'hF;`
250			`app_req_wr_n = 0;`
251			`app_req = 0;`
252			`app_req_len = 0;`
253
254			`RESETN = 1'h1;`
255
256			`#100`
257			`// Applying reset`
258			`RESETN = 1'h0;`
259			`#10000;`
260			`// Releasing reset`
261			`RESETN = 1'h1;`
262			`#1000;`
263			`wait(u_dut.sdr_init_done == 1);`
264
265			`#1000;`
266
267			`wrdfifo.push_back(32'h11223344);`
268			`wrdfifo.push_back(32'h22334455);`
269			`wrdfifo.push_back(32'h33445566);`
270			`wrdfifo.push_back(32'h44556677);`
271			`wrdfifo.push_back(32'h55667788);`
272
273			`burst_write(32'h40000);`
274			`#1000;`
275			`burst_read(32'h40000);`
276
277			`#1000;`
278			`burst_write(32'h7000_0000);`
279			`#1000;`
280			`burst_read(32'h7000_0000);`
281
282			`for(k=0; k < 20; k++) begin`
283			`StartAddr = $random & 32'h07FFFFFF;`
284			`burst_write(StartAddr);`
285			`#1000;`
286			`burst_read(StartAddr);`
287			`end`
288
289
290			`#10000;`
291
292			`$display("###############################");`
293			`if(ErrCnt == 0)`
294			`$display("STATUS: SDRAM Write/Read TEST PASSED");`
295			`else`
296			`$display("ERROR: SDRAM Write/Read TEST FAILED");`
297			`$display("###############################");`
298
299			`$finish;`
300			`end`
301
302			`task burst_write;`
303			`input [31:0] Address;`
304			`int i;`
305			`begin`
306			`@ (negedge sdram_clk);`
307			`app_req = 1;`
308			`app_wr_en_n = 0;`
309			`app_req_wr_n = 1'b0;`
310			`$display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);`
311			`app_req_addr = Address[31:2];`
312			`app_req_len = wrdfifo.size;`
313
314			`// wait for app_req_ack == 1`
315			`do begin`
316			`@ (posedge sdram_clk);`
317			`end while(app_req_ack == 1'b0);`
318			`@ (negedge sdram_clk);`
319			`app_req = 0;`
320
321			`for(i=0; i < wrdfifo.size; i++) begin`
322			`app_wr_data = wrdfifo[i];`
323
324			`do begin`
325			`@ (posedge sdram_clk);`
326			`end while(app_wr_next_req == 1'b0);`
327			`@ (negedge sdram_clk);`
328
329			`$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);`
330			`end`
331			`app_req = 0;`
332			`app_wr_en_n = 4'hF;`
333			`end`
334			`endtask`
335
336			`task burst_read;`
337			`input [31:0] Address;`
338
339			`int i,j;`
340			`reg [31:0] rd_data;`
341			`begin`
342			`@ (negedge sdram_clk);`
343
344			`app_req = 1;`
345			`app_wr_en_n = 0;`
346			`app_req_wr_n = 1;`
347			`app_req_addr = Address[29:2];`
348			`app_req_len = wrdfifo.size;`
349			`// wait for app_req_ack == 1`
350			`do begin`
351			`@ (posedge sdram_clk);`
352			`end while(app_req_ack == 1'b0);`
353			`@ (negedge sdram_clk);`
354			`app_req = 0;`
355
356			`for(j=0; j < wrdfifo.size; j++) begin`
357			`wait(app_rd_valid == 1);`
358	22	dinesha	`if(app_rd_data !== wrdfifo[j]) begin`
359	8	dinesha	`$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);`
360			`ErrCnt = ErrCnt+1;`
361			`end else begin`
362			`$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);`
363			`end`
364	22	dinesha	`@ (posedge sdram_clk);`
365	8	dinesha	`@ (negedge sdram_clk);`
366			`end`
367			`end`
368			`endtask`
369
370
371			`endmodule`

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