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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the SDRAM Controller project           ////
////  http://www.opencores.org/cores/sdr_ctrl/                    ////
////                                                              ////
////  Description                                                 ////
////  SDRAM CTRL definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
//   Version  :0.1 - Test Bench automation is improvised with     ////
//             seperate data,address,burst length fifo.           ////
//             Now user can create different write and            ////
//             read sequence                                      ////
//                                                                ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/1ps
 
// This testbench verify with SDRAM TOP
 
module tb_top;
 
parameter P_SYS  = 10;     //    200MHz
parameter P_SDR  = 20;     //    100MHz
 
// General
reg            RESETN;
reg            sdram_clk;
reg            sys_clk;
 
initial sys_clk = 0;
initial sdram_clk = 0;
 
always #(P_SYS/2) sys_clk = !sys_clk;
always #(P_SDR/2) sdram_clk = !sdram_clk;
 
parameter      dw              = 32;  // data width
parameter      tw              = 8;   // tag id width
parameter      bl              = 5;   // burst_lenght_width
 
//-------------------------------------------
// WISH BONE Interface
//-------------------------------------------
//--------------------------------------
// Wish Bone Interface
// -------------------------------------
reg             wb_stb_i           ;
wire            wb_ack_o           ;
reg  [29:0]     wb_addr_i          ;
reg             wb_we_i            ; // 1 - Write, 0 - Read
reg  [dw-1:0]   wb_dat_i           ;
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
wire  [dw-1:0]  wb_dat_o           ;
reg             wb_cyc_i           ;
reg   [2:0]     wb_cti_i           ;
 
 
 
//--------------------------------------------
// SDRAM I/F
//--------------------------------------------
 
`ifdef SDR_32BIT
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
`elsif SDR_16BIT
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
`else
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d   = sdram_clk;
 
`ifdef SDR_32BIT
 
   sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
`elsif SDR_16BIT
   sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
`else  // 8 BIT SDRAM
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
`endif
      // System
`ifdef SDR_32BIT
          .cfg_sdr_width      (2'b00              ), // 32 BIT SDRAM
`elsif SDR_16BIT
          .cfg_sdr_width      (2'b01              ), // 16 BIT SDRAM
`else
          .cfg_sdr_width      (2'b10              ), // 8 BIT SDRAM
`endif
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
/* WISH BONE */
          .wb_rst_i           (!RESETN            ),
          .wb_clk_i           (sys_clk            ),
 
          .wb_stb_i           (wb_stb_i           ),
          .wb_ack_o           (wb_ack_o           ),
          .wb_addr_i          (wb_addr_i          ),
          .wb_we_i            (wb_we_i            ),
          .wb_dat_i           (wb_dat_i           ),
          .wb_sel_i           (wb_sel_i           ),
          .wb_dat_o           (wb_dat_o           ),
          .wb_cyc_i           (wb_cyc_i           ),
          .wb_cti_i           (wb_cti_i           ),
 
/* Interface to SDRAMs */
          .sdram_clk          (sdram_clk          ),
          .sdram_resetn       (RESETN             ),
          .sdr_cs_n           (sdr_cs_n           ),
          .sdr_cke            (sdr_cke            ),
          .sdr_ras_n          (sdr_ras_n          ),
          .sdr_cas_n          (sdr_cas_n          ),
          .sdr_we_n           (sdr_we_n           ),
          .sdr_dqm            (sdr_dqm            ),
          .sdr_ba             (sdr_ba             ),
          .sdr_addr           (sdr_addr           ),
          .sdr_dq             (Dq                 ),
 
    /* Parameters */
          .sdr_init_done      (sdr_init_done      ),
          .cfg_req_depth      (2'h3               ),            //how many req. buffer should hold
          .cfg_sdr_en         (1'b1               ),
          .cfg_sdr_mode_reg   (12'h033            ),
          .cfg_sdr_tras_d     (4'h4               ),
          .cfg_sdr_trp_d      (4'h2               ),
          .cfg_sdr_trcd_d     (4'h2               ),
          .cfg_sdr_cas        (3'h3               ),
          .cfg_sdr_trcar_d    (4'h7               ),
          .cfg_sdr_twr_d      (4'h1               ),
          .cfg_sdr_rfsh       (12'h100            ), // reduced from 12'hC35
          .cfg_sdr_rfmax      (3'h6               )
 
);
 
 
`ifdef SDR_32BIT
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
`elsif SDR_16BIT
 
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .casb               (sdr_cas_n          ),
          .web                (sdr_we_n           ),
          .dqm                (sdr_dqm            )
    );
`else
 
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
`endif
 
//--------------------
// data/address/burst length FIFO
//--------------------
int dfifo[$]; // data fifo
int afifo[$]; // address  fifo
int bfifo[$]; // Burst Length fifo
 
reg [31:0] read_data;
reg [31:0] ErrCnt;
int k;
reg [31:0] StartAddr;
/////////////////////////////////////////////////////////////////////////
// Test Case
/////////////////////////////////////////////////////////////////////////
 
initial begin //{
  ErrCnt          = 0;
   wb_addr_i      = 0;
   wb_dat_i      = 0;
   wb_sel_i       = 4'h0;
   wb_we_i        = 0;
   wb_stb_i       = 0;
   wb_cyc_i       = 0;
 
  RESETN    = 1'h1;
 
 #100
  // Applying reset
  RESETN    = 1'h0;
  #10000;
  // Releasing reset
  RESETN    = 1'h1;
  #1000;
  wait(u_dut.sdr_init_done == 1);
 
  #1000;
 
 
  burst_write(32'h4_0000,8'h4);
 #1000;
  burst_read();
 
  // Repeat one more time to analysis the
  // SDRAM state change for same col/row address
  burst_write(32'h4_0000,8'h4);
 #1000;
 #1000;
  burst_write(32'h0040_0000,8'h5);
 
 #1000;
  burst_read();
 
  // 4 Write & 4 Read
  burst_write(32'h4_0000,8'h4);
  burst_write(32'h5_0000,8'h5);
  burst_write(32'h6_0000,8'h6);
  burst_write(32'h7_0000,8'h7);
  burst_read();
  burst_read();
  burst_read();
  burst_read();
 
 
  // 2 write and 2 read random
 
  for(k=0; k < 20; k++) begin
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h3f)+1);
 #100;
 
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr,($random & 8'h3f)+1);
 #100;
     burst_read();
 #100;
     burst_read();
 #100;
  end
 
 
  #10000;
 
        $display("###############################");
    if(ErrCnt == 0)
        $display("STATUS: SDRAM Write/Read TEST PASSED");
    else
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
        $display("###############################");
 
    $finish;
end
 
task burst_write;
input [31:0] Address;
input [7:0]  bl;
int i;
begin
  afifo.push_back(Address);
  bfifo.push_back(bl);
 
   @ (negedge sys_clk);
   $display("Write Address: %x, Burst Size: %d",Address,bl);
 
   for(i=0; i < bl; i++) begin
      wb_stb_i        = 1;
      wb_cyc_i        = 1;
      wb_we_i         = 1;
      wb_sel_i        = 4'b1111;
      wb_addr_i       = Address[31:2]+i;
      wb_dat_i        = $random & 32'hFFFFFFFF;
      dfifo.push_back(wb_dat_i);
 
      do begin
          @ (posedge sys_clk);
      end while(wb_ack_o == 1'b0);
          @ (negedge sys_clk);
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
   end
   wb_stb_i           = 0;
   wb_cyc_i           = 0;
end
endtask
 
task burst_read;
reg [31:0] Address;
reg [7:0]  bl;
 
int i,j;
reg [31:0]   exp_data;
begin
 
   Address = afifo.pop_front();
   bl      = bfifo.pop_front();
   @ (negedge sys_clk);
 
      for(j=0; j < bl; j++) begin
         wb_stb_i        = 1;
         wb_cyc_i        = 1;
         wb_we_i         = 0;
         wb_addr_i       = Address[31:2]+j;
 
         exp_data        = dfifo.pop_front(); // Exptected Read Data
         do begin
             @ (posedge sys_clk);
         end while(wb_ack_o == 1'b0);
         if(wb_dat_o !== exp_data) begin
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,exp_data);
             ErrCnt = ErrCnt+1;
         end else begin
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
         end
         @ (negedge sdram_clk);
      end
   wb_stb_i           = 0;
   wb_cyc_i           = 0;
end
endtask
 
 
endmodule

Line No.	Rev	Author	Line
1	8	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the SDRAM Controller project ////`
5			`//// http://www.opencores.org/cores/sdr_ctrl/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// SDRAM CTRL definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12			`//// ////`
13	43	dinesha	`// Version :0.1 - Test Bench automation is improvised with ////`
14			`// seperate data,address,burst length fifo. ////`
15			`// Now user can create different write and ////`
16			`// read sequence ////`
17			`// ////`
18	8	dinesha	`//// Author(s): ////`
19			`//// - Dinesh Annayya, dinesha@opencores.org ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47
48
49			`timescale 1ns/1ps
50
51	24	dinesha	`// This testbench verify with SDRAM TOP`
52
53	8	dinesha	`module tb_top;`
54
55	30	dinesha	`parameter P_SYS = 10; // 200MHz`
56			`parameter P_SDR = 20; // 100MHz`
57	8	dinesha
58			`// General`
59			`reg RESETN;`
60			`reg sdram_clk;`
61	30	dinesha	`reg sys_clk;`
62	8	dinesha
63	30	dinesha	`initial sys_clk = 0;`
64	8	dinesha	`initial sdram_clk = 0;`
65
66	30	dinesha	`always #(P_SYS/2) sys_clk = !sys_clk;`
67			`always #(P_SDR/2) sdram_clk = !sdram_clk;`
68	8	dinesha
69			`parameter dw = 32; // data width`
70			`parameter tw = 8; // tag id width`
71			`parameter bl = 5; // burst_lenght_width`
72
73			`//-------------------------------------------`
74	30	dinesha	`// WISH BONE Interface`
75	8	dinesha	`//-------------------------------------------`
76	30	dinesha	`//--------------------------------------`
77			`// Wish Bone Interface`
78			`// -------------------------------------`
79			`reg wb_stb_i ;`
80			`wire wb_ack_o ;`
81			`reg [29:0] wb_addr_i ;`
82			`reg wb_we_i ; // 1 - Write, 0 - Read`
83			`reg [dw-1:0] wb_dat_i ;`
84			`reg [dw/8-1:0] wb_sel_i ; // Byte enable`
85			`wire [dw-1:0] wb_dat_o ;`
86			`reg wb_cyc_i ;`
87			`reg [2:0] wb_cti_i ;`
88	8	dinesha
89	30	dinesha
90
91	8	dinesha	`//--------------------------------------------`
92			`// SDRAM I/F`
93			`//--------------------------------------------`
94
95			`ifdef SDR_32BIT
96			`wire [31:0] Dq ; // SDRAM Read/Write Data Bus`
97			`wire [3:0] sdr_dqm ; // SDRAM DATA Mask`
98	18	dinesha	`elsif SDR_16BIT
99	8	dinesha	`wire [15:0] Dq ; // SDRAM Read/Write Data Bus`
100			`wire [1:0] sdr_dqm ; // SDRAM DATA Mask`
101	18	dinesha	`else
102			`wire [7:0] Dq ; // SDRAM Read/Write Data Bus`
103			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
104	8	dinesha	`endif
105
106			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
107			`wire [11:0] sdr_addr ; // SDRAM ADRESS`
108			`wire sdr_init_done ; // SDRAM Init Done`
109
110			`// to fix the sdram interface timing issue`
111	30	dinesha	`wire #(2.0) sdram_clk_d = sdram_clk;`
112	8	dinesha
113			`ifdef SDR_32BIT
114
115	30	dinesha	`sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(`
116	18	dinesha	`elsif SDR_16BIT
117	30	dinesha	`sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(`
118	18	dinesha	`else // 8 BIT SDRAM
119	30	dinesha	`sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(`
120	8	dinesha	`endif
121			`// System`
122			`ifdef SDR_32BIT
123	38	dinesha	`.cfg_sdr_width (2'b00 ), // 32 BIT SDRAM`
124	18	dinesha	`elsif SDR_16BIT
125	38	dinesha	`.cfg_sdr_width (2'b01 ), // 16 BIT SDRAM`
126	18	dinesha	`else
127	38	dinesha	`.cfg_sdr_width (2'b10 ), // 8 BIT SDRAM`
128	8	dinesha	`endif
129	12	dinesha	`.cfg_colbits (2'b00 ), // 8 Bit Column Address`
130	8	dinesha
131	30	dinesha	`/* WISH BONE */`
132			`.wb_rst_i (!RESETN ),`
133			`.wb_clk_i (sys_clk ),`
134	8	dinesha
135	30	dinesha	`.wb_stb_i (wb_stb_i ),`
136			`.wb_ack_o (wb_ack_o ),`
137			`.wb_addr_i (wb_addr_i ),`
138			`.wb_we_i (wb_we_i ),`
139			`.wb_dat_i (wb_dat_i ),`
140			`.wb_sel_i (wb_sel_i ),`
141			`.wb_dat_o (wb_dat_o ),`
142			`.wb_cyc_i (wb_cyc_i ),`
143			`.wb_cti_i (wb_cti_i ),`
144	8	dinesha
145			`/* Interface to SDRAMs */`
146	30	dinesha	`.sdram_clk (sdram_clk ),`
147			`.sdram_resetn (RESETN ),`
148	8	dinesha	`.sdr_cs_n (sdr_cs_n ),`
149			`.sdr_cke (sdr_cke ),`
150			`.sdr_ras_n (sdr_ras_n ),`
151			`.sdr_cas_n (sdr_cas_n ),`
152			`.sdr_we_n (sdr_we_n ),`
153			`.sdr_dqm (sdr_dqm ),`
154			`.sdr_ba (sdr_ba ),`
155			`.sdr_addr (sdr_addr ),`
156	37	dinesha	`.sdr_dq (Dq ),`
157	8	dinesha
158			`/* Parameters */`
159			`.sdr_init_done (sdr_init_done ),`
160	44	dinesha	`.cfg_req_depth (2'h3 ), //how many req. buffer should hold`
161	8	dinesha	`.cfg_sdr_en (1'b1 ),`
162			`.cfg_sdr_mode_reg (12'h033 ),`
163			`.cfg_sdr_tras_d (4'h4 ),`
164			`.cfg_sdr_trp_d (4'h2 ),`
165			`.cfg_sdr_trcd_d (4'h2 ),`
166	22	dinesha	`.cfg_sdr_cas (3'h3 ),`
167	8	dinesha	`.cfg_sdr_trcar_d (4'h7 ),`
168			`.cfg_sdr_twr_d (4'h1 ),`
169	45	dinesha	`.cfg_sdr_rfsh (12'h100 ), // reduced from 12'hC35`
170	8	dinesha	`.cfg_sdr_rfmax (3'h6 )`
171
172			`);`
173
174
175			`ifdef SDR_32BIT
176			`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`
177			`.Dq (Dq ) ,`
178			`.Addr (sdr_addr ),`
179			`.Ba (sdr_ba ),`
180	22	dinesha	`.Clk (sdram_clk_d ),`
181	8	dinesha	`.Cke (sdr_cke ),`
182			`.Cs_n (sdr_cs_n ),`
183			`.Ras_n (sdr_ras_n ),`
184			`.Cas_n (sdr_cas_n ),`
185			`.We_n (sdr_we_n ),`
186			`.Dqm (sdr_dqm )`
187			`);`
188
189	18	dinesha	`elsif SDR_16BIT
190	8	dinesha
191			`IS42VM16400K u_sdram16 (`
192			`.dq (Dq ),`
193			`.addr (sdr_addr ),`
194			`.ba (sdr_ba ),`
195	22	dinesha	`.clk (sdram_clk_d ),`
196	8	dinesha	`.cke (sdr_cke ),`
197			`.csb (sdr_cs_n ),`
198			`.rasb (sdr_ras_n ),`
199			`.casb (sdr_cas_n ),`
200			`.web (sdr_we_n ),`
201			`.dqm (sdr_dqm )`
202			`);`
203	18	dinesha	`else
204
205
206			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
207			`.Dq (Dq ) ,`
208			`.Addr (sdr_addr ),`
209			`.Ba (sdr_ba ),`
210	22	dinesha	`.Clk (sdram_clk_d ),`
211	18	dinesha	`.Cke (sdr_cke ),`
212			`.Cs_n (sdr_cs_n ),`
213			`.Ras_n (sdr_ras_n ),`
214			`.Cas_n (sdr_cas_n ),`
215			`.We_n (sdr_we_n ),`
216			`.Dqm (sdr_dqm )`
217			`);`
218	8	dinesha	`endif
219
220			`//--------------------`
221	43	dinesha	`// data/address/burst length FIFO`
222	8	dinesha	`//--------------------`
223	43	dinesha	`int dfifo[$]; // data fifo`
224			`int afifo[$]; // address fifo`
225			`int bfifo[$]; // Burst Length fifo`
226	8	dinesha
227			`reg [31:0] read_data;`
228			`reg [31:0] ErrCnt;`
229			`int k;`
230			`reg [31:0] StartAddr;`
231			`/////////////////////////////////////////////////////////////////////////`
232			`// Test Case`
233			`/////////////////////////////////////////////////////////////////////////`
234
235			`initial begin //{`
236			`ErrCnt = 0;`
237	30	dinesha	`wb_addr_i = 0;`
238			`wb_dat_i = 0;`
239			`wb_sel_i = 4'h0;`
240			`wb_we_i = 0;`
241			`wb_stb_i = 0;`
242			`wb_cyc_i = 0;`
243	8	dinesha
244			`RESETN = 1'h1;`
245
246			`#100`
247			`// Applying reset`
248			`RESETN = 1'h0;`
249			`#10000;`
250			`// Releasing reset`
251			`RESETN = 1'h1;`
252			`#1000;`
253			`wait(u_dut.sdr_init_done == 1);`
254
255			`#1000;`
256
257
258	43	dinesha	`burst_write(32'h4_0000,8'h4);`
259	8	dinesha	`#1000;`
260	43	dinesha	`burst_read();`
261	8	dinesha
262	45	dinesha	`// Repeat one more time to analysis the`
263			`// SDRAM state change for same col/row address`
264			`burst_write(32'h4_0000,8'h4);`
265	8	dinesha	`#1000;`
266	45	dinesha	`#1000;`
267	43	dinesha	`burst_write(32'h0040_0000,8'h5);`
268	45	dinesha
269	8	dinesha	`#1000;`
270	43	dinesha	`burst_read();`
271	8	dinesha
272	43	dinesha	`// 4 Write & 4 Read`
273			`burst_write(32'h4_0000,8'h4);`
274			`burst_write(32'h5_0000,8'h5);`
275			`burst_write(32'h6_0000,8'h6);`
276			`burst_write(32'h7_0000,8'h7);`
277			`burst_read();`
278			`burst_read();`
279			`burst_read();`
280			`burst_read();`
281
282
283			`// 2 write and 2 read random`
284
285	8	dinesha	`for(k=0; k < 20; k++) begin`
286	43	dinesha	`StartAddr = $random & 32'h003FFFFF;`
287			`burst_write(StartAddr,($random & 8'h3f)+1);`
288			`#100;`
289
290			`StartAddr = $random & 32'h003FFFFF;`
291			`burst_write(StartAddr,($random & 8'h3f)+1);`
292			`#100;`
293			`burst_read();`
294			`#100;`
295			`burst_read();`
296			`#100;`
297	8	dinesha	`end`
298
299
300			`#10000;`
301
302			`$display("###############################");`
303			`if(ErrCnt == 0)`
304			`$display("STATUS: SDRAM Write/Read TEST PASSED");`
305			`else`
306			`$display("ERROR: SDRAM Write/Read TEST FAILED");`
307			`$display("###############################");`
308
309			`$finish;`
310			`end`
311
312			`task burst_write;`
313			`input [31:0] Address;`
314	43	dinesha	`input [7:0] bl;`
315	8	dinesha	`int i;`
316			`begin`
317	43	dinesha	`afifo.push_back(Address);`
318			`bfifo.push_back(bl);`
319
320	30	dinesha	`@ (negedge sys_clk);`
321	43	dinesha	`$display("Write Address: %x, Burst Size: %d",Address,bl);`
322	8	dinesha
323	43	dinesha	`for(i=0; i < bl; i++) begin`
324	30	dinesha	`wb_stb_i = 1;`
325			`wb_cyc_i = 1;`
326			`wb_we_i = 1;`
327			`wb_sel_i = 4'b1111;`
328			`wb_addr_i = Address[31:2]+i;`
329	43	dinesha	`wb_dat_i = $random & 32'hFFFFFFFF;`
330			`dfifo.push_back(wb_dat_i);`
331	8	dinesha
332			`do begin`
333	30	dinesha	`@ (posedge sys_clk);`
334			`end while(wb_ack_o == 1'b0);`
335			`@ (negedge sys_clk);`
336	8	dinesha
337	30	dinesha	`$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,wb_addr_i,wb_dat_i);`
338	8	dinesha	`end`
339	30	dinesha	`wb_stb_i = 0;`
340			`wb_cyc_i = 0;`
341	8	dinesha	`end`
342			`endtask`
343
344			`task burst_read;`
345	43	dinesha	`reg [31:0] Address;`
346			`reg [7:0] bl;`
347	8	dinesha
348			`int i,j;`
349	43	dinesha	`reg [31:0] exp_data;`
350	8	dinesha	`begin`
351	43	dinesha
352			`Address = afifo.pop_front();`
353			`bl = bfifo.pop_front();`
354	30	dinesha	`@ (negedge sys_clk);`
355	8	dinesha
356	43	dinesha	`for(j=0; j < bl; j++) begin`
357	30	dinesha	`wb_stb_i = 1;`
358			`wb_cyc_i = 1;`
359			`wb_we_i = 0;`
360			`wb_addr_i = Address[31:2]+j;`
361	8	dinesha
362	43	dinesha	`exp_data = dfifo.pop_front(); // Exptected Read Data`
363	30	dinesha	`do begin`
364			`@ (posedge sys_clk);`
365			`end while(wb_ack_o == 1'b0);`
366	43	dinesha	`if(wb_dat_o !== exp_data) begin`
367			`$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,exp_data);`
368	8	dinesha	`ErrCnt = ErrCnt+1;`
369			`end else begin`
370	30	dinesha	`$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);`
371	8	dinesha	`end`
372			`@ (negedge sdram_clk);`
373			`end`
374	30	dinesha	`wb_stb_i = 0;`
375			`wb_cyc_i = 0;`
376	8	dinesha	`end`
377			`endtask`
378
379
380			`endmodule`

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