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`include "inc.h"
 
//
//  SDRAMCNT.v
//
//  SDRAM controller.
//  This module can control Synchronous DRAMS such as
//  Samsumg's  KM416S1020/KM416S1120   1MB X 16
//  NEC's      uPD451616               1MB X 16
//  Oki's      MSM56V16160
//
//  The SDRAM's internal MODE REGISTER is also programmable.
//
//  
 
 
module sdramcnt(
            // system level stuff
                        sys_rst_l,
                        sys_clk,
 
                        // SDRAM connections
                        sd_clke,
                        sd_wr_l,
            sd_cs_l,
                        sd_ras_l,
                        sd_cas_l,
                        sd_ldqm,
                        sd_udqm,
 
                        // Host Controller connections
                do_mode_set,
                        do_read,
            do_write,
            doing_refresh,
            sd_addx_mux,
            sd_addx10_mux,
            sd_rd_ena,
            sd_data_ena,
            modereg_cas_latency,
            modereg_burst_length,
            mp_data_mux,
 
                        // debug
            next_state,
                        autorefresh_cntr,
                        autorefresh_cntr_l,
                        pwrup,
                        cntr_limit
 
                );
 
 
 
// ****************************************
//
//   I/O  DEFINITION
//
// ****************************************
 
 
// System level stuff
input           sys_rst_l;
input           sys_clk;
 
// SDRAM connections
output          sd_wr_l;
output          sd_cs_l;
output          sd_ras_l;
output          sd_cas_l;
output          sd_ldqm;
output          sd_udqm;
output          sd_clke;
 
// Host Controller connections
input           do_mode_set;
input           do_read;
input           do_write;
output          doing_refresh;
output  [1:0]   sd_addx_mux;
output  [1:0]   sd_addx10_mux;
output          sd_rd_ena;
output          sd_data_ena;
input   [2:0]   modereg_cas_latency;
input   [2:0]   modereg_burst_length;
output          mp_data_mux;
 
// Debug
output  [3:0]  next_state;
output  [12:0]   autorefresh_cntr;
output                  autorefresh_cntr_l;
output                  pwrup;
output  [12:0]   cntr_limit;
 
// ****************************************
//
// Memory Elements 
//
// ****************************************
//
reg     [3:0]    next_state;
reg     [7:0]   refresh_timer;
reg                 sd_wr_l;
reg                         sd_cs_l;
reg                         sd_ras_l;
reg                         sd_cas_l;
reg                 sd_ldqm;
reg                 sd_udqm;
reg     [1:0]       sd_addx_mux;
reg     [1:0]       sd_addx10_mux;
reg                 sd_data_ena;
reg                         pwrup;                      // this variable holds the power up condition
reg     [12:0]      refresh_cntr;   // this is the refresh counter
reg                                     refresh_cntr_l; // this is the refresh counter reset signal
reg     [3:0]       burst_length_cntr;
reg                 burst_cntr_ena;
reg                 sd_rd_ena;      // read latch gate, active high
reg     [12:0]      cntr_limit;
reg     [3:0]       modereg_burst_count;
reg     [2:0]       refresh_state;
reg                 mp_data_mux;
wire                do_refresh;     // this bit indicates autorefresh is due
reg                 doing_refresh;  // this bit indicates that the state machine is 
                                    // doing refresh.
reg     [12:0]   autorefresh_cntr;
reg                 autorefresh_cntr_l;
 
assign sd_clke = `HI;           // clk always enabled
 
// State Machine
always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l) begin
    next_state  <= `state_powerup;
    autorefresh_cntr_l <= `LO;
        refresh_cntr_l  <= `LO;
    pwrup       <= `HI;
    sd_wr_l     <= `HI;
    sd_cs_l     <= `HI;
    sd_ras_l    <= `HI;
    sd_cas_l    <= `HI;
    sd_ldqm     <= `HI;
    sd_udqm     <= `HI;
    sd_data_ena <= `LO;
    sd_addx_mux <= 2'b10;           // select the mode reg default value
    sd_addx10_mux <= 2'b11;         // select 1 as default
    sd_rd_ena   <= `LO;
    mp_data_mux <= `LO;
//    refresh_cntr<= 13'h0000;
    burst_cntr_ena <= `LO;          // do not enable the burst counter
    doing_refresh  <= `LO;
  end
  else case (next_state)
    // Power Up state
    `state_powerup:  begin
        next_state  <= `state_precharge;
        sd_wr_l     <= `HI;
        sd_cs_l     <= `HI;
        sd_ras_l    <= `HI;
        sd_cas_l    <= `HI;
        sd_ldqm     <= `HI;
        sd_udqm     <= `HI;
        sd_data_ena <= `LO;
        sd_addx_mux <= 2'b10;
        sd_rd_ena   <= `LO;
        pwrup       <= `HI;         // this is the power up run
        burst_cntr_ena <= `LO;      // do not enable the burst counter
                refresh_cntr_l <= `HI;          // allow the refresh cycle counter to count
     end
 
    // PRECHARGE both banks             
    `state_precharge:  begin
//        refresh_cntr<= refresh_cntr + 1;         // one less ref cycle to do   
        sd_wr_l     <= `LO;
        sd_cs_l     <= `LO;
        sd_ras_l    <= `LO;
        sd_cas_l    <= `HI;
        sd_ldqm     <= `HI;
        sd_udqm     <= `HI;
        sd_addx10_mux <= 2'b11;      // A10 = 1'b1   
         if ( (refresh_cntr == cntr_limit) & (pwrup == `HI) ) begin
             doing_refresh <= `LO;                // refresh cycle is done
//             refresh_cntr  <= 13'h000;             // ..reset refresh counter
             refresh_cntr_l  <= `LO;             // ..reset refresh counter
             next_state <= `state_modeset;      // if this was power-up, then go and set mode reg
             pwrup      <= `LO;                 // ..no more in power up mode
         end else begin
           doing_refresh <= `HI;        // indicate that we're doing refresh
           next_state    <= `state_auto_refresh;
                 end
    end
 
    // Autorefresh
    `state_auto_refresh: begin
        sd_wr_l     <= `HI;
        sd_cs_l     <= `LO;
        sd_ras_l    <= `LO;
        sd_cas_l    <= `LO;
        sd_ldqm     <= `HI;
        sd_udqm     <= `HI;
        sd_addx10_mux <= 2'b01;      // A10 = 0   
        next_state  <= `state_auto_refresh_dly;
        autorefresh_cntr_l  <= `HI;  //allow delay cntr to tick
     end
 
    // Autor Refresh Delay -- extends the AutoRefresh CMD by   
    // AUTO_REFRESH_WIDTH counts
    `state_auto_refresh_dly:  begin
        if (autorefresh_cntr == `AUTO_REFRESH_WIDTH) begin
          autorefresh_cntr_l <= `LO;
          sd_wr_l     <= `HI;
          sd_cs_l     <= `HI;
          sd_ras_l    <= `HI;
          sd_cas_l    <= `HI;
          sd_ldqm     <= `HI;
          sd_udqm     <= `HI;
          // If all refresh is done
          if ((refresh_cntr == cntr_limit) & (pwrup == `LO))   begin
             doing_refresh <= `LO;                // refresh cycle is done
//             refresh_cntr  <= 13'h000;            // ..reset refresh counter
             refresh_cntr_l  <= `LO;            // ..reset refresh counter
             if (do_write | do_read)
                 next_state <= `state_set_ras;    // go service a pending read or write if any
             else
                 next_state <= `state_idle;       // if there are no peding RD or WR, then go to idle state
           end
          // IF refresh cycles not done yet..
          else
             next_state <= `state_precharge;
       end
   end
 
    // MODE SET state
    `state_modeset:  begin
        next_state  <= `state_idle;
        sd_wr_l     <= `LO;
        sd_cs_l     <= `LO;
        sd_ras_l    <= `LO;
        sd_cas_l    <= `LO;
        if (~pwrup) begin       // select a10-a0 to be the data from mode set reg
          sd_addx_mux <= 2'b10;
          sd_addx10_mux <= 2'b10;
        end
    end
 
    // IDLE state
    `state_idle:  begin
        sd_wr_l     <= `HI;
        sd_cs_l     <= `HI;
        sd_ras_l        <= `HI;
        sd_cas_l        <= `HI;
        sd_ldqm     <= `HI;
        sd_udqm     <= `HI;
        sd_data_ena <= `LO;         // turn off the data bus drivers
        sd_addx10_mux <= 2'b01;     // select low
        mp_data_mux <= `LO;         // drive the SD data bus with normal data
        if (do_write | do_read )
            next_state <= `state_set_ras;
        else if (do_mode_set)
            next_state <= `state_modeset;
        else if (do_refresh) begin
            next_state <= `state_precharge;
                        refresh_cntr_l <= `HI;          // allow refresh cycle counter to count up
                end
    end
 
    // SET RAS state
    `state_set_ras:  begin
        sd_cs_l     <= `LO;     // enable SDRAM 
        sd_ras_l    <= `LO;     // enable the RAS
        sd_addx_mux <= 2'b00;   // send the low 10 bits of mp_addx to SDRAM
        next_state  <= `state_ras_dly;   // wait for a bit
    end
 
    // RAS delay state.  This state may not be necessary for most
    // cases.  Fow now, it is here to kill 1-cycle time
    `state_ras_dly:  begin
        sd_cs_l     <= `HI;     // disable SDRAM 
        sd_ras_l    <= `HI;     // disble the RAS
        if (do_write)
            next_state <= `state_write;      // if write, do the write      
        else
            next_state <= `state_set_cas;    // if read, do the read
    end
 
    // WRITE state
    `state_write:  begin
        sd_cs_l     <= `LO;     // enable SDRAM 
        sd_cas_l    <= `LO;     // enable the CAS
        sd_addx_mux <= 2'b01;   // send the lower 8 bits of mp_addx to SDRAM (CAS addx)
                                // remember that the mp_addr[19] is the sd_ba
        sd_addx10_mux <= 2'b00; // set A10/AP = mp_addx[18] 
        sd_data_ena <= `HI;     // turn on  the data bus drivers
        sd_wr_l     <= `LO;     // enable the write
        sd_ldqm     <= `LO;     // do not mask
        sd_udqm     <= `LO;     // do not mask
        next_state  <= `state_cool_off;
    end
 
    // SET CAS state
    `state_set_cas:  begin
        sd_cs_l     <= `LO;
        sd_cas_l    <= `LO;
        sd_addx_mux <= 2'b01;
        sd_addx10_mux <= 2'b00;
        sd_ldqm     <= `LO;     // do not mask
        sd_udqm     <= `LO;     // do not mask
        next_state  <= `state_cas_latency1;
    end
 
    `state_cas_latency1: begin
        sd_cs_l     <= `HI;     // disable CS
        sd_cas_l    <= `HI;     // disable CAS
        if (modereg_cas_latency==3'b010)  begin
           next_state <= `state_read;            // 2 cycles of lantency done.
           burst_cntr_ena <= `HI;                // enable he burst lenght counter
        end else
           next_state <= `state_cas_latency2;    // 3 cycles of latency      
    end
 
    `state_cas_latency2:  begin
        next_state <= `state_read;
        burst_cntr_ena <= `HI;      // enable the burst lenght counter
    end
 
    `state_read:  begin
        if (burst_length_cntr == modereg_burst_count) begin
            burst_cntr_ena <= `LO;  // done counting;
            sd_rd_ena      <= `LO;     // done with the reading
            next_state     <= `state_cool_off;
        end else
           sd_rd_ena  <= `HI;          // enable the read latch on the next state               
    end
 
    `state_cool_off:  begin
        sd_wr_l     <= `HI;
        sd_cs_l     <= `HI;
        sd_ras_l        <= `HI;
        sd_cas_l        <= `HI;
        sd_ldqm     <= `HI;
        sd_udqm     <= `HI;
        sd_addx10_mux <= 2'b01;     // select the mp_addx[10]
        mp_data_mux <= `HI;         // drive the SD data bus with all zeros
        next_state  <= `state_idle;
    end
 
  endcase
 
 
// This counter is used to extend the width of the Auto Refresh
// command.  It was found that if the AutoRefresh CMD set to be the default of 
// 1 SDRAM_CLK cycle, then an AutoRefresh CMD in the middle of a burst read
// would mess-up the remining burst reads.  By extending the Auto Refresh cycle
// to 2 or more, this burst read problem was solved.  As to why this happens
// I did not investigate further.
always @(posedge sys_clk or negedge autorefresh_cntr_l)
  if (~autorefresh_cntr_l)
    autorefresh_cntr <= 13'h0000;
  else
    autorefresh_cntr <= autorefresh_cntr + 1;
 
 
 
// This mux selects the cycle limit value for the 
// auto refresh counter
always @(pwrup)
  case (pwrup)
/*    `HI:      cntr_limit <= `power_up_ref_cntr_limit;
    default:  cntr_limit <= `auto_ref_cntr_limit;
*/
    1'b1:      cntr_limit <= 13'h000F;
    default:  cntr_limit <= 13'h0001;
  endcase
 
 
//
// BURST LENGHT COUNTER
//
// This is the burst length counter.  
always @(posedge sys_clk or negedge burst_cntr_ena)
  if (~burst_cntr_ena)
     burst_length_cntr <= 3'b000;   // reset whenever 'burst_cntr_ena' is low
  else
     burst_length_cntr <= burst_length_cntr + 1;
 
//
// REFRESH_CNTR
//
always @(posedge sys_clk or negedge refresh_cntr_l)
  if (~refresh_cntr_l)
     refresh_cntr <= 13'h0000;
  else if (next_state  == `state_auto_refresh)
         refresh_cntr <= refresh_cntr + 1;
 
//
// BURST LENGTH SELECTOR
//
always @(modereg_burst_length)
   case (modereg_burst_length)
      3'b000:  modereg_burst_count <= 4'h1;
      3'b001:  modereg_burst_count <= 4'h2;
      3'b010:  modereg_burst_count <= 4'h4;
      default  modereg_burst_count <= 4'h8;
   endcase
 
 
//
// REFRESH Request generator
//
assign do_refresh = (refresh_state == `state_halt);
 
 
always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l) begin
     refresh_state <= `state_count;
     refresh_timer <= 8'h00;
  end
  else case (refresh_state)
     // COUNT
     // count up the refresh interval counter. If the
     // timer reaches the refresh-expire time, then go next state
     `state_count:
        if (refresh_timer != `RC)
           refresh_timer <= refresh_timer + 1;
        else
           refresh_state <= `state_halt;
 
     // HALT
     // wait for the SDRAM to complete any ongoing reads or
     // writes.  If the SDRAM has acknowledged the do_refresh,
     // (i.e. it is now doing the refresh)
     // then go to next state 
     `state_halt:
        if (next_state==`state_auto_refresh     |
            next_state==`state_auto_refresh_dly |
            next_state==`state_precharge )
           refresh_state <= `state_reset;
 
 
     // RESET
     // if the SDRAM refresh is completed, then reset the counter
     // and start counting up again.
     `state_reset:
        if (next_state==`state_idle) begin
           refresh_state <= `state_count;
           refresh_timer <= 8'h00;
        end
  endcase
 
 
endmodule
 

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[/] [sdram/] [branches/] [opencores/] [sdramcnt.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	jlee	`include "inc.h"
2
3			`//`
4			`// SDRAMCNT.v`
5			`//`
6			`// SDRAM controller.`
7			`// This module can control Synchronous DRAMS such as`
8			`// Samsumg's KM416S1020/KM416S1120 1MB X 16`
9			`// NEC's uPD451616 1MB X 16`
10			`// Oki's MSM56V16160`
11			`//`
12			`// The SDRAM's internal MODE REGISTER is also programmable.`
13			`//`
14			`//`
15
16
17			`module sdramcnt(`
18			`// system level stuff`
19			`sys_rst_l,`
20			`sys_clk,`
21
22			`// SDRAM connections`
23			`sd_clke,`
24			`sd_wr_l,`
25			`sd_cs_l,`
26			`sd_ras_l,`
27			`sd_cas_l,`
28			`sd_ldqm,`
29			`sd_udqm,`
30
31			`// Host Controller connections`
32			`do_mode_set,`
33			`do_read,`
34			`do_write,`
35			`doing_refresh,`
36			`sd_addx_mux,`
37			`sd_addx10_mux,`
38			`sd_rd_ena,`
39			`sd_data_ena,`
40			`modereg_cas_latency,`
41			`modereg_burst_length,`
42			`mp_data_mux,`
43
44			`// debug`
45			`next_state,`
46			`autorefresh_cntr,`
47			`autorefresh_cntr_l,`
48			`pwrup,`
49			`cntr_limit`
50
51			`);`
52
53
54
55			`// ****************************************`
56			`//`
57			`// I/O DEFINITION`
58			`//`
59			`// ****************************************`
60
61
62			`// System level stuff`
63			`input sys_rst_l;`
64			`input sys_clk;`
65
66			`// SDRAM connections`
67			`output sd_wr_l;`
68			`output sd_cs_l;`
69			`output sd_ras_l;`
70			`output sd_cas_l;`
71			`output sd_ldqm;`
72			`output sd_udqm;`
73			`output sd_clke;`
74
75			`// Host Controller connections`
76			`input do_mode_set;`
77			`input do_read;`
78			`input do_write;`
79			`output doing_refresh;`
80			`output [1:0] sd_addx_mux;`
81			`output [1:0] sd_addx10_mux;`
82			`output sd_rd_ena;`
83			`output sd_data_ena;`
84			`input [2:0] modereg_cas_latency;`
85			`input [2:0] modereg_burst_length;`
86			`output mp_data_mux;`
87
88			`// Debug`
89			`output [3:0] next_state;`
90			`output [12:0] autorefresh_cntr;`
91			`output autorefresh_cntr_l;`
92			`output pwrup;`
93			`output [12:0] cntr_limit;`
94
95			`// ****************************************`
96			`//`
97			`// Memory Elements`
98			`//`
99			`// ****************************************`
100			`//`
101			`reg [3:0] next_state;`
102			`reg [7:0] refresh_timer;`
103			`reg sd_wr_l;`
104			`reg sd_cs_l;`
105			`reg sd_ras_l;`
106			`reg sd_cas_l;`
107			`reg sd_ldqm;`
108			`reg sd_udqm;`
109			`reg [1:0] sd_addx_mux;`
110			`reg [1:0] sd_addx10_mux;`
111			`reg sd_data_ena;`
112			`reg pwrup; // this variable holds the power up condition`
113			`reg [12:0] refresh_cntr; // this is the refresh counter`
114			`reg refresh_cntr_l; // this is the refresh counter reset signal`
115			`reg [3:0] burst_length_cntr;`
116			`reg burst_cntr_ena;`
117			`reg sd_rd_ena; // read latch gate, active high`
118			`reg [12:0] cntr_limit;`
119			`reg [3:0] modereg_burst_count;`
120			`reg [2:0] refresh_state;`
121			`reg mp_data_mux;`
122			`wire do_refresh; // this bit indicates autorefresh is due`
123			`reg doing_refresh; // this bit indicates that the state machine is`
124			`// doing refresh.`
125			`reg [12:0] autorefresh_cntr;`
126			`reg autorefresh_cntr_l;`
127
128			assign sd_clke = `HI; // clk always enabled
129
130			`// State Machine`
131			`always @(posedge sys_clk or negedge sys_rst_l)`
132			`if (~sys_rst_l) begin`
133			next_state <= `state_powerup;
134			autorefresh_cntr_l <= `LO;
135			refresh_cntr_l <= `LO;
136			pwrup <= `HI;
137			sd_wr_l <= `HI;
138			sd_cs_l <= `HI;
139			sd_ras_l <= `HI;
140			sd_cas_l <= `HI;
141			sd_ldqm <= `HI;
142			sd_udqm <= `HI;
143			sd_data_ena <= `LO;
144			`sd_addx_mux <= 2'b10; // select the mode reg default value`
145			`sd_addx10_mux <= 2'b11; // select 1 as default`
146			sd_rd_ena <= `LO;
147			mp_data_mux <= `LO;
148			`// refresh_cntr<= 13'h0000;`
149			burst_cntr_ena <= `LO; // do not enable the burst counter
150			doing_refresh <= `LO;
151			`end`
152			`else case (next_state)`
153			`// Power Up state`
154			`state_powerup: begin
155			next_state <= `state_precharge;
156			sd_wr_l <= `HI;
157			sd_cs_l <= `HI;
158			sd_ras_l <= `HI;
159			sd_cas_l <= `HI;
160			sd_ldqm <= `HI;
161			sd_udqm <= `HI;
162			sd_data_ena <= `LO;
163			`sd_addx_mux <= 2'b10;`
164			sd_rd_ena <= `LO;
165			pwrup <= `HI; // this is the power up run
166			burst_cntr_ena <= `LO; // do not enable the burst counter
167			refresh_cntr_l <= `HI; // allow the refresh cycle counter to count
168			`end`
169
170			`// PRECHARGE both banks`
171			`state_precharge: begin
172			`// refresh_cntr<= refresh_cntr + 1; // one less ref cycle to do`
173			sd_wr_l <= `LO;
174			sd_cs_l <= `LO;
175			sd_ras_l <= `LO;
176			sd_cas_l <= `HI;
177			sd_ldqm <= `HI;
178			sd_udqm <= `HI;
179			`sd_addx10_mux <= 2'b11; // A10 = 1'b1`
180			if ( (refresh_cntr == cntr_limit) & (pwrup == `HI) ) begin
181			doing_refresh <= `LO; // refresh cycle is done
182			`// refresh_cntr <= 13'h000; // ..reset refresh counter`
183			refresh_cntr_l <= `LO; // ..reset refresh counter
184			next_state <= `state_modeset; // if this was power-up, then go and set mode reg
185			pwrup <= `LO; // ..no more in power up mode
186			`end else begin`
187			doing_refresh <= `HI; // indicate that we're doing refresh
188			next_state <= `state_auto_refresh;
189			`end`
190			`end`
191
192			`// Autorefresh`
193			`state_auto_refresh: begin
194			sd_wr_l <= `HI;
195			sd_cs_l <= `LO;
196			sd_ras_l <= `LO;
197			sd_cas_l <= `LO;
198			sd_ldqm <= `HI;
199			sd_udqm <= `HI;
200			`sd_addx10_mux <= 2'b01; // A10 = 0`
201			next_state <= `state_auto_refresh_dly;
202			autorefresh_cntr_l <= `HI; //allow delay cntr to tick
203			`end`
204
205			`// Autor Refresh Delay -- extends the AutoRefresh CMD by`
206			`// AUTO_REFRESH_WIDTH counts`
207			`state_auto_refresh_dly: begin
208			if (autorefresh_cntr == `AUTO_REFRESH_WIDTH) begin
209			autorefresh_cntr_l <= `LO;
210			sd_wr_l <= `HI;
211			sd_cs_l <= `HI;
212			sd_ras_l <= `HI;
213			sd_cas_l <= `HI;
214			sd_ldqm <= `HI;
215			sd_udqm <= `HI;
216			`// If all refresh is done`
217			if ((refresh_cntr == cntr_limit) & (pwrup == `LO)) begin
218			doing_refresh <= `LO; // refresh cycle is done
219			`// refresh_cntr <= 13'h000; // ..reset refresh counter`
220			refresh_cntr_l <= `LO; // ..reset refresh counter
221			`if (do_write \| do_read)`
222			next_state <= `state_set_ras; // go service a pending read or write if any
223			`else`
224			next_state <= `state_idle; // if there are no peding RD or WR, then go to idle state
225			`end`
226			`// IF refresh cycles not done yet..`
227			`else`
228			next_state <= `state_precharge;
229			`end`
230			`end`
231
232			`// MODE SET state`
233			`state_modeset: begin
234			next_state <= `state_idle;
235			sd_wr_l <= `LO;
236			sd_cs_l <= `LO;
237			sd_ras_l <= `LO;
238			sd_cas_l <= `LO;
239			`if (~pwrup) begin // select a10-a0 to be the data from mode set reg`
240			`sd_addx_mux <= 2'b10;`
241			`sd_addx10_mux <= 2'b10;`
242			`end`
243			`end`
244
245			`// IDLE state`
246			`state_idle: begin
247			sd_wr_l <= `HI;
248			sd_cs_l <= `HI;
249			sd_ras_l <= `HI;
250			sd_cas_l <= `HI;
251			sd_ldqm <= `HI;
252			sd_udqm <= `HI;
253			sd_data_ena <= `LO; // turn off the data bus drivers
254			`sd_addx10_mux <= 2'b01; // select low`
255			mp_data_mux <= `LO; // drive the SD data bus with normal data
256			`if (do_write \| do_read )`
257			next_state <= `state_set_ras;
258			`else if (do_mode_set)`
259			next_state <= `state_modeset;
260			`else if (do_refresh) begin`
261			next_state <= `state_precharge;
262			refresh_cntr_l <= `HI; // allow refresh cycle counter to count up
263			`end`
264			`end`
265
266			`// SET RAS state`
267			`state_set_ras: begin
268			sd_cs_l <= `LO; // enable SDRAM
269			sd_ras_l <= `LO; // enable the RAS
270			`sd_addx_mux <= 2'b00; // send the low 10 bits of mp_addx to SDRAM`
271			next_state <= `state_ras_dly; // wait for a bit
272			`end`
273
274			`// RAS delay state. This state may not be necessary for most`
275			`// cases. Fow now, it is here to kill 1-cycle time`
276			`state_ras_dly: begin
277			sd_cs_l <= `HI; // disable SDRAM
278			sd_ras_l <= `HI; // disble the RAS
279			`if (do_write)`
280			next_state <= `state_write; // if write, do the write
281			`else`
282			next_state <= `state_set_cas; // if read, do the read
283			`end`
284
285			`// WRITE state`
286			`state_write: begin
287			sd_cs_l <= `LO; // enable SDRAM
288			sd_cas_l <= `LO; // enable the CAS
289			`sd_addx_mux <= 2'b01; // send the lower 8 bits of mp_addx to SDRAM (CAS addx)`
290			`// remember that the mp_addr[19] is the sd_ba`
291			`sd_addx10_mux <= 2'b00; // set A10/AP = mp_addx[18]`
292			sd_data_ena <= `HI; // turn on the data bus drivers
293			sd_wr_l <= `LO; // enable the write
294			sd_ldqm <= `LO; // do not mask
295			sd_udqm <= `LO; // do not mask
296			next_state <= `state_cool_off;
297			`end`
298
299			`// SET CAS state`
300			`state_set_cas: begin
301			sd_cs_l <= `LO;
302			sd_cas_l <= `LO;
303			`sd_addx_mux <= 2'b01;`
304			`sd_addx10_mux <= 2'b00;`
305			sd_ldqm <= `LO; // do not mask
306			sd_udqm <= `LO; // do not mask
307			next_state <= `state_cas_latency1;
308			`end`
309
310			`state_cas_latency1: begin
311			sd_cs_l <= `HI; // disable CS
312			sd_cas_l <= `HI; // disable CAS
313			`if (modereg_cas_latency==3'b010) begin`
314			next_state <= `state_read; // 2 cycles of lantency done.
315			burst_cntr_ena <= `HI; // enable he burst lenght counter
316			`end else`
317			next_state <= `state_cas_latency2; // 3 cycles of latency
318			`end`
319
320			`state_cas_latency2: begin
321			next_state <= `state_read;
322			burst_cntr_ena <= `HI; // enable the burst lenght counter
323			`end`
324
325			`state_read: begin
326			`if (burst_length_cntr == modereg_burst_count) begin`
327			burst_cntr_ena <= `LO; // done counting;
328			sd_rd_ena <= `LO; // done with the reading
329			next_state <= `state_cool_off;
330			`end else`
331			sd_rd_ena <= `HI; // enable the read latch on the next state
332			`end`
333
334			`state_cool_off: begin
335			sd_wr_l <= `HI;
336			sd_cs_l <= `HI;
337			sd_ras_l <= `HI;
338			sd_cas_l <= `HI;
339			sd_ldqm <= `HI;
340			sd_udqm <= `HI;
341			`sd_addx10_mux <= 2'b01; // select the mp_addx[10]`
342			mp_data_mux <= `HI; // drive the SD data bus with all zeros
343			next_state <= `state_idle;
344			`end`
345
346			`endcase`
347
348
349			`// This counter is used to extend the width of the Auto Refresh`
350			`// command. It was found that if the AutoRefresh CMD set to be the default of`
351			`// 1 SDRAM_CLK cycle, then an AutoRefresh CMD in the middle of a burst read`
352			`// would mess-up the remining burst reads. By extending the Auto Refresh cycle`
353			`// to 2 or more, this burst read problem was solved. As to why this happens`
354			`// I did not investigate further.`
355			`always @(posedge sys_clk or negedge autorefresh_cntr_l)`
356			`if (~autorefresh_cntr_l)`
357			`autorefresh_cntr <= 13'h0000;`
358			`else`
359			`autorefresh_cntr <= autorefresh_cntr + 1;`
360
361
362
363			`// This mux selects the cycle limit value for the`
364			`// auto refresh counter`
365			`always @(pwrup)`
366			`case (pwrup)`
367			/* `HI: cntr_limit <= `power_up_ref_cntr_limit;
368			default: cntr_limit <= `auto_ref_cntr_limit;
369			`*/`
370			`1'b1: cntr_limit <= 13'h000F;`
371			`default: cntr_limit <= 13'h0001;`
372			`endcase`
373
374
375			`//`
376			`// BURST LENGHT COUNTER`
377			`//`
378			`// This is the burst length counter.`
379			`always @(posedge sys_clk or negedge burst_cntr_ena)`
380			`if (~burst_cntr_ena)`
381			`burst_length_cntr <= 3'b000; // reset whenever 'burst_cntr_ena' is low`
382			`else`
383			`burst_length_cntr <= burst_length_cntr + 1;`
384
385			`//`
386			`// REFRESH_CNTR`
387			`//`
388			`always @(posedge sys_clk or negedge refresh_cntr_l)`
389			`if (~refresh_cntr_l)`
390			`refresh_cntr <= 13'h0000;`
391			else if (next_state == `state_auto_refresh)
392			`refresh_cntr <= refresh_cntr + 1;`
393
394			`//`
395			`// BURST LENGTH SELECTOR`
396			`//`
397			`always @(modereg_burst_length)`
398			`case (modereg_burst_length)`
399			`3'b000: modereg_burst_count <= 4'h1;`
400			`3'b001: modereg_burst_count <= 4'h2;`
401			`3'b010: modereg_burst_count <= 4'h4;`
402			`default modereg_burst_count <= 4'h8;`
403			`endcase`
404
405
406			`//`
407			`// REFRESH Request generator`
408			`//`
409			assign do_refresh = (refresh_state == `state_halt);
410
411
412			`always @(posedge sys_clk or negedge sys_rst_l)`
413			`if (~sys_rst_l) begin`
414			refresh_state <= `state_count;
415			`refresh_timer <= 8'h00;`
416			`end`
417			`else case (refresh_state)`
418			`// COUNT`
419			`// count up the refresh interval counter. If the`
420			`// timer reaches the refresh-expire time, then go next state`
421			`state_count:
422			if (refresh_timer != `RC)
423			`refresh_timer <= refresh_timer + 1;`
424			`else`
425			refresh_state <= `state_halt;
426
427			`// HALT`
428			`// wait for the SDRAM to complete any ongoing reads or`
429			`// writes. If the SDRAM has acknowledged the do_refresh,`
430			`// (i.e. it is now doing the refresh)`
431			`// then go to next state`
432			`state_halt:
433			if (next_state==`state_auto_refresh \|
434			next_state==`state_auto_refresh_dly \|
435			next_state==`state_precharge )
436			refresh_state <= `state_reset;
437
438
439			`// RESET`
440			`// if the SDRAM refresh is completed, then reset the counter`
441			`// and start counting up again.`
442			`state_reset:
443			if (next_state==`state_idle) begin
444			refresh_state <= `state_count;
445			`refresh_timer <= 8'h00;`
446			`end`
447			`endcase`
448
449
450			`endmodule`
451