OpenCores
URL https://opencores.org/ocsvn/sdram_16bit/sdram_16bit/trunk

Subversion Repositories sdram_16bit

[/] [sdram_16bit/] [trunk/] [testbench/] [makefile] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ultra_embe
TRACE                   ?= 1
2
MAX_ADDRESS     ?= 8192
3
PART                    ?= IS42VM16400K
4
 
5
all: compile run view
6
 
7
# Testbench
8
SRC+= ./top_tb.sv wb_master.sv IS42VM16400K.v MT48LC8M16A2.v
9
 
10
# DUT
11
SRC+= ../rtl/sdram.v
12
 
13
SRC_FLAGS = +define+MAX_ADDRESS=$(MAX_ADDRESS)
14
 
15
ifeq ($(TRACE),1)
16
    SRC_FLAGS += +define+TRACE=$(TRACE)
17
endif
18
 
19
SRC_FLAGS += +define+PART=$(PART)
20
 
21
INC_DIRS = -I.
22
 
23
compile :
24
        vlib work
25
        vlog $(SRC) $(SRC_FLAGS)
26
 
27
run : compile
28
        vsim -c -do "run -all" top_tb
29
 
30
view : compile
31
ifeq ($(TRACE),1)
32
        gtkwave waveform.vcd gtksettings.sav
33
endif
34
 
35
clean :
36
        -rm -rf work waveform.vcd transcript

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.