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[/] [sdram_16bit/] [trunk/] [testbench/] [wb_master.sv] - Blame information for rev 2

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1 2 ultra_embe 
//-----------------------------------------------------------------
2 
// Module
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//-----------------------------------------------------------------
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module wb_master
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(
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    input                               clk_i,
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    input                               rst_i,
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    // Wishbone I/F
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    output reg [31:0]                   addr_o,
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    output reg [31:0]                   data_o,
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    input [31:0]                        data_i,
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    output reg [3:0]                    sel_o,
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    output reg [2:0]                    cti_o,
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    output reg                          cyc_o,
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    output reg                          stb_o,
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    output reg                          we_o,
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    input                               ack_i,
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    input                               stall_i
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);
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter MIN_ADDRESS       = 0;
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parameter MAX_ADDRESS       = 8192;
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parameter BURST_ENABLED     = 1;
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parameter READ_ONLY         = 0;
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parameter WRITE_ONLY        = 0;
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parameter SEQUENTIAL_ONLY   = 0;
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parameter RANDOM_DELAY      = 1;
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parameter DELAY_RATE        = 3;
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`include "simulation.svh"
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//-----------------------------------------------------------------
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// Request Queue
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//-----------------------------------------------------------------
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typedef struct
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{
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    reg [31:0] address;
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    reg [31:0] data;
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    reg [3:0]  sel;
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    reg        we;
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} request_t;
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request_t requests[$];
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//-----------------------------------------------------------------
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// Memory
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//-----------------------------------------------------------------
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reg [31:0] mem[*];
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//-----------------------------------------------------------------
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// write
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//-----------------------------------------------------------------
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task automatic write(input [31:0] addr, input [31:0] data);
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begin
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    mem[addr[31:2]] = data;
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end
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endtask
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//-----------------------------------------------------------------
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// read
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//-----------------------------------------------------------------
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task automatic read(input [31:0] addr, output [31:0] data);
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begin
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    if (mem.exists(addr[31:2]))
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        data = mem[addr[31:2]];
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    else
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        data = 32'bx;
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end
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endtask
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//-----------------------------------------------------------------
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// write_bytes
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//-----------------------------------------------------------------
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task automatic write_bytes(input [31:0] addr, input [31:0] data, input [31:0] sel);
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begin
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    reg [31:0] new_data;
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    read(addr, new_data);
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    if (sel[3])
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        new_data[31:24] = data[31:24];
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    if (sel[2])
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        new_data[23:16] = data[23:16];
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    if (sel[1])
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        new_data[15:8]  = data[15:8];
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    if (sel[0])
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        new_data[7:0]   = data[7:0];
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    write(addr, new_data);
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end
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endtask
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//-----------------------------------------------------------------
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// compare
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//-----------------------------------------------------------------
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task automatic compare(input [31:0] addr, input [31:0] data, input [31:0] sel, output match);
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begin
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    reg [31:0] new_data;
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    read(addr, new_data);
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    match = 1;
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    if (sel[3])
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        if (new_data[31:24] !== data[31:24])
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            match = 0;
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    if (sel[2])
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        if (new_data[23:16] !== data[23:16])
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            match = 0;
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    if (sel[1])
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        if (new_data[15:8] !== data[15:8])
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            match = 0;
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    if (sel[0])
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        if (new_data[7:0] !== data[7:0])
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            match = 0;
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    if (!match)
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    begin
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        $display("ERROR: Expected %x Got %x Mask %x", new_data, data, sel);
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    end
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end
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endtask
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//-----------------------------------------------------------------
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// request
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//-----------------------------------------------------------------
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initial
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begin
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    request_t  req;
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    reg        burst;
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    reg [2:0]  burst_cnt;
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    addr_o = 32'bz;
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    data_o = 32'bz;
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    sel_o  = 4'bz;
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    we_o   = 1'bz;
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    stb_o  = 1'b0;
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    cti_o  = 3'bz;
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    burst  = 1'b0;
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    burst_cnt = 0;
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    req.address = 0;
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    forever
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    begin
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        @(posedge clk_i);
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        // Command presented and accepted
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        if (stb_o && !stall_i)
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        begin
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            requests.push_back(req);
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            addr_o = 32'bz;
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            data_o = 32'bz;
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            sel_o  = 4'bz;
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            we_o   = 1'bz;
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            cti_o  = 3'bz;
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            stb_o  = 1'b0;
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        end
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        // Continuation of a burst
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        if (!stb_o && burst)
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        begin
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            req.address = req.address + 4;
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            req.data    = req.we ? $urandom : 32'bz;
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            addr_o = req.address;
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            addr_o[1:0] = 2'b0;
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            data_o = req.data;
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            cti_o  = (burst_cnt == 1) ? 3'b111 : 3'b010;
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            sel_o  = req.sel;
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            we_o   = req.we;
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            stb_o  = 1'b1;
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            burst_cnt   = burst_cnt - 1;
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            if (burst_cnt == 0)
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                burst   = 0;
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        end
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        // Ready to issue a new command?
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        if (!stb_o)
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        begin
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            if (RANDOM_DELAY)
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            begin
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                repeat ($urandom_range(DELAY_RATE,0)) @(posedge clk_i);
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            end
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            if (SEQUENTIAL_ONLY)
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                req.address = req.address + 4;
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            else
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                req.address = $urandom_range(MAX_ADDRESS,MIN_ADDRESS);
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            if (READ_ONLY)
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                req.we  = 1'b0;
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            else if (WRITE_ONLY)
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                req.we  = 1'b1;
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            else
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                req.we  = $urandom;
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            req.data    = req.we ? $urandom : 32'bz;
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            if (BURST_ENABLED)
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            begin
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                burst       = $urandom;
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                burst_cnt   = 7;
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            end
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            else
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                burst       = 0;
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            req.sel     = (!burst && req.we) ? $urandom : 4'b1111;
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            addr_o = req.address;
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            addr_o[1:0] = 2'b0;
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            data_o = req.data;
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            sel_o  = req.sel;
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            we_o   = req.we;
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            cti_o  = (!burst) ? 3'b111 : 3'b010;
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            stb_o  = 1'b1;
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        end
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    end
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end
229 
 
230 
//-----------------------------------------------------------------
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// response
232 
//-----------------------------------------------------------------
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always @(posedge clk_i)
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begin
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    request_t  req;
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    if (ack_i)
237 
    begin
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        `ASSERT(requests.size() > 0);
239 
 
240 
        req = requests.pop_front();
241 
 
242 
        // Write
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        if (req.we)
244 
        begin
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            write_bytes(req.address, req.data, req.sel);
246 
        end
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        // Read
248 
        else
249 
        begin
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            reg match;
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            compare(req.address, data_i, req.sel, match);
252 
            `ASSERT(match);
253 
        end
254 
    end
255 
end
256 
 
257 
always @ *
258 
begin
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    cyc_o  = stb_o || (requests.size() > 0);
260 
end
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endmodule

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