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[/] [sdram_controller/] [trunk/] [ddr_parameters.vh] - Blame information for rev 5

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/****************************************************************************************
*
*   Disclaimer   This software code and all associated documentation, comments or other
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
*                limitation of liability for consequential or incidental damages, the
*                above limitation may not apply to you.
*
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
 
    // Timing parameters based on Speed Grade 04/07
 
                                          // SYMBOL UNITS DESCRIPTION
                                          // ------ ----- -----------
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`else `ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`else `ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
`endif `endif `endif `endif `endif
 
    // Size Parameters based on Part Width
 
`ifdef x4
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used
`else `ifdef x8
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
`else `define x16
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
`endif `endif
 
    parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits are used
    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
 
    parameter no_halt          =       1; // If set to 1, the model won't halt on command sequence/major errors
    parameter DEBUG            =       1; // Turn on DEBUG message

Line No.	Rev	Author	Line
1	5	lynn0p	`/****************************************************************************************`
2			`*`
3			`* Disclaimer This software code and all associated documentation, comments or other`
4			`* of Warranty: information (collectively "Software") is provided "AS IS" without`
5			`* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY`
6			`* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED`
7			`* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES`
8			`* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT`
9			`* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE`
10			`* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.`
11			`* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR`
12			`* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,`
13			`* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE`
14			`* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,`
15			`* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,`
16			`* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,`
17			`* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,`
18			`* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE`
19			`* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH`
20			`* DAMAGES. Because some jurisdictions prohibit the exclusion or`
21			`* limitation of liability for consequential or incidental damages, the`
22			`* above limitation may not apply to you.`
23			`*`
24			`* Copyright 2003 Micron Technology, Inc. All rights reserved.`
25			`*`
26			`****************************************************************************************/`
27
28			`// Timing parameters based on Speed Grade 04/07`
29
30			`// SYMBOL UNITS DESCRIPTION`
31			`// ------ ----- -----------`
32			`ifdef sg5B // Timing Parameters for -5B (CL = 3)
33			`parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time`
34			`parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
35			`parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time`
36			`parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command`
37			`parameter tRAS = 40.0; // tRAS ns Active to Precharge command time`
38			`parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time`
39			`parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time`
40			`parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time`
41			`parameter tRP = 15.0; // tRP ns Precharge command period`
42			`parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time`
43			`parameter tWR = 15.0; // tWR ns Write recovery time`
44			`else `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
45			`parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time`
46			`parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
47			`parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time`
48			`parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command`
49			`parameter tRAS = 42.0; // tRAS ns Active to Precharge command time`
50			`parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time`
51			`parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time`
52			`parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time`
53			`parameter tRP = 15.0; // tRP ns Precharge command period`
54			`parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time`
55			`parameter tWR = 15.0; // tWR ns Write recovery time`
56			`else `ifdef sg6 // Timing Parameters for -6 (CL = 2.5)
57			`parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time`
58			`parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
59			`parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time`
60			`parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command`
61			`parameter tRAS = 42.0; // tRAS ns Active to Precharge command time`
62			`parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time`
63			`parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time`
64			`parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time`
65			`parameter tRP = 15.0; // tRP ns Precharge command period`
66			`parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time`
67			`parameter tWR = 15.0; // tWR ns Write recovery time`
68			`else `ifdef sg75E // Timing Parameters for -75E (CL = 2)
69			`parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time`
70			`parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
71			`parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time`
72			`parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command`
73			`parameter tRAS = 40.0; // tRAS ns Active to Precharge command time`
74			`parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time`
75			`parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time`
76			`parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time`
77			`parameter tRP = 15.0; // tRP ns Precharge command period`
78			`parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time`
79			`parameter tWR = 15.0; // tWR ns Write recovery time`
80			`else `ifdef sg75Z // Timing Parameters for -75Z (CL = 2)
81			`parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time`
82			`parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
83			`parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time`
84			`parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command`
85			`parameter tRAS = 40.0; // tRAS ns Active to Precharge command time`
86			`parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time`
87			`parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time`
88			`parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time`
89			`parameter tRP = 20.0; // tRP ns Precharge command period`
90			`parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time`
91			`parameter tWR = 15.0; // tWR ns Write recovery time`
92			`else `define sg75 // Timing Parameters for -75 (CL = 2.5)
93			`parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time`
94			`parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access`
95			`parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time`
96			`parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command`
97			`parameter tRAS = 40.0; // tRAS ns Active to Precharge command time`
98			`parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time`
99			`parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time`
100			`parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time`
101			`parameter tRP = 20.0; // tRP ns Precharge command period`
102			`parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time`
103			`parameter tWR = 15.0; // tWR ns Write recovery time`
104			`endif `endif `endif `endif `endif
105
106			`// Size Parameters based on Part Width`
107
108			`ifdef x4
109			`parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used`
110			`parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used`
111			`parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used`
112			`parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used`
113			`parameter COL_BITS = 12; // Set this parameter to control how many Column bits are used`
114			`else `ifdef x8
115			`parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used`
116			`parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used`
117			`parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used`
118			`parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used`
119			`parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used`
120			`else `define x16
121			`parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used`
122			`parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used`
123			`parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used`
124			`parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used`
125			`parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used`
126			`endif `endif
127
128			`parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used`
129			`parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used`
130			`parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used`
131
132			`parameter no_halt = 1; // If set to 1, the model won't halt on command sequence/major errors`
133			`parameter DEBUG = 1; // Turn on DEBUG message`

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[/] [sdram_controller/] [trunk/] [ddr_parameters.vh] - Blame information for rev 5