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----------------------------------------------------------------------------------
-- Company: OPL Aerospatiale AG
-- Engineer: Owen Lynn <lynn0p@hotmail.com>
-- 
-- Create Date:    14:25:41 08/20/2009 
-- Design Name:    DDR SDRAM Controller
-- Module Name:    sdram_controller - impl 
-- Project Name: 
-- Target Devices: Spartan3e Starter Board
-- Tool versions:  ISE 11.2
-- Description: This is the main controller module. This is where the signals to/from the DDR SDRAM chip happen.
--  
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--  Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
--  Released under the GNU Lesser General Public License, Version 3
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- This is not meant to be a high performance controller. No fancy command scheduling, does the bare minimum to work without screwing up timing.
-- Do NOT put this controller in something mission critical! This is the creation of a guy in his bedroom, learning digital circuits.
-- Intended to be used exclusively with the Spartan3e Starter Board and targets the mt46v32m16 chip. Dunno if it will work anywhere else.
-- Uses the ODDR2 and DCM Xilinx primitives, for other FPGAs, you'll need to patch in equivalents. See sdram_support for the details.
-- I'd strongly recommend running it through a post-PAR simulation if you're porting to any other FPGA, as the timings will change on you.
-- Consumes two DCMs, runs off of the main 50mhz board clock. Could possibly consume one DCM if you want to feed it the 100mhz clock directly.
-- Has an 8bit wide datapath, moderate changes could support 16bits, 32 bits you'll have to work some. You want more than that, you'll
--  be doing brain surgery on the FSMs - good luck.
 
-- This design has been tested with the testbench only. There may be glitches hidden in here somewhere still. Consider this to be an alpha release.
-- Did I mention that you shouldn't put this in anything mission critical? 
 
-- Be careful with the synthesizer settings too. Do not let the FSM extractor choose something other than one-hot. Be careful with register
--  removal.
 
-- TODO: implement reset signal
entity sdram_controller is
        port(      -- user facing signals 
                 clk50mhz : in  std_logic;
                en : in  std_logic;
                    reset : in  std_logic;
                       op : in  std_logic_vector(1 downto 0);        -- 00/11: NOP, 01: READ, 10: write
                     addr : in  std_logic_vector(25 downto 0);       -- address to read/write 
                   op_ack : out std_logic;                           -- op, addr and data_i should be captured when this goes high
                   busy_n : out std_logic;                           -- busy when LOW, ops will be ignored until busy goes high again
                   data_o : out std_logic_vector(7 downto 0);        -- data from read shows up here
                   data_i : in  std_logic_vector(7 downto 0);        -- data to write needs to be here
 
                -- SDRAM facing signals 
                          dram_clkp : out   std_logic;                         -- 0 deg phase 100mhz clock going out to SDRAM chip
                          dram_clkn : out   std_logic;                         -- 180 deg phase version of dram_clkp
                dram_clke : out   std_logic;                         -- clock enable, owned by the init module
                            dram_cs : out   std_logic;                         -- tied low upon powerup
                 dram_cmd : out   std_logic_vector(2 downto 0);      -- this is the command vector <we_n,cas_n,ras_n>
           dram_bank : out   std_logic_vector(1 downto 0);      -- bank address
                          dram_addr : out   std_logic_vector(12 downto 0);     -- row/col/mode register
                            dram_dm : out   std_logic_vector(1 downto 0);      -- masks used for writing
                           dram_dqs : inout std_logic_vector(1 downto 0);      -- strobes used for writing
                            dram_dq : inout std_logic_vector(15 downto 0);     -- data lines
 
                          -- debug signals (possibly could be repurposed later for wider data)
                          debug_reg : out   std_logic_vector(7 downto 0)
                                 );
end sdram_controller;
 
architecture impl of sdram_controller is
 
        -- component decls begin here
        component sdram_dcm is
                port(
                        reset      : in  std_logic;
                        clk50mhz   : in  std_logic;
                        locked     : out std_logic;
                        dram_clkp  : out std_logic;
                        dram_clkn  : out std_logic;
                        clk_000    : out std_logic;
                        clk_090    : out std_logic;
                        clk_180    : out std_logic;
                        clk_270    : out std_logic
                );
        end component;
 
        component oddr2_2 is
                port(
                        Q  : out std_logic_vector(1 downto 0);
                        C0 : in  std_logic;
                        C1 : in  std_logic;
                        CE : in  std_logic;
                        D0 : in  std_logic_vector(1 downto 0);
                        D1 : in  std_logic_vector(1 downto 0);
                        R  : in  std_logic;
                        S  : in  std_logic );
        end component;
 
        component oddr2_3 is
                port(
                        Q  : out std_logic_vector(2 downto 0);
                        C0 : in  std_logic;
                        C1 : in  std_logic;
                        CE : in  std_logic;
                        D0 : in  std_logic_vector(2 downto 0);
                        D1 : in  std_logic_vector(2 downto 0);
                        R  : in  std_logic;
                        S  : in  std_logic );
        end component;
 
        component oddr2_13 is
                port(
                        Q  : out std_logic_vector(12 downto 0);
                        C0 : in  std_logic;
                        C1 : in  std_logic;
                        CE : in  std_logic;
                        D0 : in  std_logic_vector(12 downto 0);
                        D1 : in  std_logic_vector(12 downto 0);
                        R  : in  std_logic;
                        S  : in  std_logic );
        end component;
 
        component inout_switch_2 is
                port (
                        ioport : inout std_logic_vector(1 downto 0);
                                dir : in    std_logic;
                        data_o : out   std_logic_vector(1 downto 0);
                        data_i : in    std_logic_vector(1 downto 0)
                );
        end component;
 
        component inout_switch_16 is
                port (
                        ioport : inout std_logic_vector(15 downto 0);
                                dir : in    std_logic;
                        data_o : out   std_logic_vector(15 downto 0);
                        data_i : in    std_logic_vector(15 downto 0)
                );
        end component;
 
        component sdram_reader is
                port(
                        clk000 : in  std_logic;
                        clk270 : in  std_logic;
                        rst    : in  std_logic;
                        dq     : in  std_logic_vector(15 downto 0);
                        data0  : out std_logic_vector(7 downto 0);
                        data1  : out std_logic_vector(7 downto 0)
                );
        end component;
 
        component sdram_writer is
                port(
                        clk    : in  std_logic;
                        clk090 : in  std_logic;
                        clk180 : in  std_logic;
                        clk270 : in  std_logic;
                        rst    : in  std_logic;
                        addr   : in  std_logic;
                        data_o : in  std_logic_vector(7 downto 0);
                        dqs    : out std_logic_vector(1 downto 0);
                        dm     : out std_logic_vector(1 downto 0);
                        dq     : out std_logic_vector(15 downto 0);
                        done   : out std_logic
                );
        end component;
 
        component wait_counter is
                generic(
                        BITS : integer;
                        CLKS : integer
                );
                port(
                         clk : in std_logic;
                         rst : in std_logic;
                        done : out std_logic
                );
        end component;
 
        component sdram_init
                port(
                        clk_000 : in std_logic;
                        reset   : in std_logic;
 
                        clke  : out std_logic;
                        cmd   : out std_logic_vector(2 downto 0);
                        bank  : out std_logic_vector(1 downto 0);
                        addr  : out std_logic_vector(12 downto 0);
                        done  : out std_logic
                );
        end component;
 
        component cmd_bank_addr_switch is
                port(
                        sel      : in std_logic;
                        cmd0_in  : in std_logic_vector(2 downto 0);
                        bank0_in : in std_logic_vector(1 downto 0);
                        addr0_in : in std_logic_vector(12 downto 0);
                        cmd1_in  : in std_logic_vector(2 downto 0);
                        bank1_in : in std_logic_vector(1 downto 0);
                        addr1_in : in std_logic_vector(12 downto 0);
                        cmd_out  : out std_logic_vector(2 downto 0);
                        bank_out : out std_logic_vector(1 downto 0);
                        addr_out : out std_logic_vector(12 downto 0)
                );
        end component;
        -- component decls end here
 
        -- DRAM commands - <we,cas,ras>
        constant CMD_NOP        : std_logic_vector(2 downto 0)  := "111";
        constant CMD_ACTIVE     : std_logic_vector(2 downto 0)  := "110"; -- opens a row within a bank
        constant CMD_READ       : std_logic_vector(2 downto 0)  := "101";
        constant CMD_WRITE      : std_logic_vector(2 downto 0)  := "001";
        constant CMD_BURST_TERM : std_logic_vector(2 downto 0)  := "011";
        constant CMD_PRECHARGE  : std_logic_vector(2 downto 0)  := "010"; -- closes a row within a bank
        constant CMD_AUTO_REFR  : std_logic_vector(2 downto 0)  := "100";
        constant CMD_LOAD_MR    : std_logic_vector(2 downto 0)  := "000";
 
        -- various wait counter values
        constant AUTO_REFRESH_CLKS  : integer := 700; -- spec says 7.8us, which is 780 clocks @ 100Mhz, I'm setting it to 700
        constant WRITE_RECOVER_CLKS : integer := 5;   -- these are fudged a bit, you *might* be able to shave a clock or two off
        constant READ_DONE_CLKS     : integer := 5;
 
        type CMD_STATES is ( STATE_START, STATE_INIT, STATE_WAIT_INIT, STATE_IDLE, STATE_IDLE_AUTO_REFRESH, STATE_IDLE_WAIT_AR_CTR,
                                                                STATE_IDLE_WAIT_AUTO_REFRESH, STATE_WRITE_ROW_OPEN, STATE_WRITE_WAIT_ROW_OPEN, STATE_WRITE_ISSUE_CMD,
                                                                STATE_WRITE_WAIT_RECOVER, STATE_READ_ROW_OPEN, STATE_READ_WAIT_ROW_OPEN, STATE_READ_ISSUE_CMD,
                                                                STATE_READ_WAIT_CAPTURE );
 
        signal cmd_state : CMD_STATES := STATE_START;
 
        signal cmd_oddr2_rising   : std_logic_vector(2 downto 0) := CMD_NOP;
        signal bank_oddr2_rising  : std_logic_vector(1 downto 0) := "00";
        signal addr_oddr2_rising  : std_logic_vector(12 downto 0) := "0000000000000";
 
        signal dqs_in : std_logic_vector(1 downto 0);
        signal dqs_out : std_logic_vector(1 downto 0);
        signal dqs_dir : std_logic;
 
        signal dq_in : std_logic_vector(15 downto 0);
        signal dq_out : std_logic_vector(15 downto 0);
        signal dq_dir : std_logic;
 
        signal reader_rst : std_logic := '1';
 
        signal writer_rst : std_logic := '1';
        signal writer_done : std_logic := '0';
 
        signal dcm_locked   : std_logic;
        signal clk_000      : std_logic;
        signal clk_090      : std_logic;
        signal clk_180      : std_logic;
        signal clk_270      : std_logic;
 
        -- init module stuff
        signal init_reset : std_logic;
        signal init_cmd   : std_logic_vector(2 downto 0);
        signal init_bank  : std_logic_vector(1 downto 0);
        signal init_addr  : std_logic_vector(12 downto 0);
        signal init_done  : std_logic;
 
        -- main module stuff
        signal main_sel  : std_logic;
        signal main_cmd  : std_logic_vector(2 downto 0);
        signal main_bank : std_logic_vector(1 downto 0);
        signal main_addr : std_logic_vector(12 downto 0);
 
        -- wait counter stuff
        signal need_ar_rst : std_logic;
        signal need_ar     : std_logic;
 
        signal wait_ar_rst  : std_logic;
        signal wait_ar_done : std_logic;
 
        signal write_reco_rst  : std_logic;
        signal write_reco_done : std_logic;
 
        signal read_wait_rst : std_logic;
        signal read_wait_done : std_logic;
 
        signal data0_o : std_logic_vector(7 downto 0);
        signal data1_o : std_logic_vector(7 downto 0);
 
begin
 
        -- component instantiations begin here
        DRAM_DCM: sdram_dcm
        port map(
                reset           => reset,
                clk50mhz        => clk50mhz,
                locked          => dcm_locked,
                dram_clkp       => dram_clkp,
                dram_clkn       => dram_clkn,
                clk_000         => clk_000,
                clk_090         => clk_090,
                clk_180         => clk_180,
                clk_270         => clk_270
        );
 
        DRAM_INIT: sdram_init
        port map(
                clk_000 => clk_000,
                reset   => init_reset,
                clke    => dram_clke,
                cmd     => init_cmd,
                bank    => init_bank,
                addr    => init_addr,
                done    => init_done
        );
 
        CMD_BANK_ADDR_SEL: cmd_bank_addr_switch
        port map(
                sel      => main_sel,
                cmd0_in  => init_cmd,
                bank0_in => init_bank,
                addr0_in => init_addr,
                cmd1_in  => main_cmd,
                bank1_in => main_bank,
                addr1_in => main_addr,
                cmd_out  => cmd_oddr2_rising,
                bank_out => bank_oddr2_rising,
                addr_out => addr_oddr2_rising
        );
 
        DRAM_BANK_ODDR2: oddr2_2
        port map(
                Q  => dram_bank,
                C0 => clk_270,
                C1 => clk_090,
                CE => '1',
                D0 => bank_oddr2_rising,
                D1 => "00",
                R  => '0',
                S  => '0' );
 
        DRAM_CMD_ODDR2: oddr2_3
        port map(
                Q  => dram_cmd,
                C0 => clk_270,
                C1 => clk_090,
                CE => '1',
                D0 => cmd_oddr2_rising,
                D1 => CMD_NOP,
                R  => '0',
                S  => '0' );
 
        DRAM_ADDR_ODDR2: oddr2_13
        port map(
                Q  => dram_addr,
                C0 => clk_270,
                C1 => clk_090,
                CE => '1',
                D0 => addr_oddr2_rising,
                D1 => "0000000000000",
                R  => '0',
                S  => '0' );
 
        DQS_SWITCH: inout_switch_2
        port map(
                ioport => dram_dqs,
                dir    => dqs_dir,
                data_o => dqs_in,
                data_i => dqs_out
        );
 
        DQ_SWITCH: inout_switch_16
        port map(
                ioport => dram_dq,
                dir    => dq_dir,
                data_o => dq_in,
                data_i => dq_out
        );
 
        AR_NEEDED_CTR: wait_counter
        generic map(
                BITS => 10,
                CLKS => AUTO_REFRESH_CLKS
        )
        port map (
          clk => clk_000,
          rst => need_ar_rst,
         done => need_ar
        );
 
        WAIT_AR_CTR: wait_counter
        generic map(
                BITS => 4,
                CLKS => 11
        )
        port map(
                clk => clk_000,
                rst => wait_ar_rst,
                done => wait_ar_done
        );
 
        WRITE_RECOVER_CTR: wait_counter
        generic map(
                BITS => 2,
                CLKS => WRITE_RECOVER_CLKS
        )
        port map(
          clk => clk_000,
          rst => write_reco_rst,
         done => write_reco_done
        );
 
        READ_DONE_CTR: wait_counter
        generic map(
                BITS => 2,
                CLKS => READ_DONE_CLKS
        )
        port map(
          clk => clk_000,
          rst => read_wait_rst,
         done => read_wait_done
        );
 
        READER: sdram_reader
        port map(
      clk000 => clk_000,
      clk270 => clk_270,
      rst    => reader_rst,
      dq     => dq_in,
                data0  => data0_o,
                data1  => data1_o
        );
 
        WRITER: sdram_writer
        port map(
                clk    => clk_000,
                clk090 => clk_090,
                clk180 => clk_180,
                clk270 => clk_270,
                rst    => writer_rst,
                addr   => addr(0),
                data_o => data_i,
                dqs    => dqs_out,
                dm     => dram_dm,
                dq     => dq_out,
                done   => writer_done
        );
        -- end component allocs
 
        dram_cs <= '0';
        data_o <= data1_o when addr(0) = '1' else data0_o;
 
        -- command state machine
        process (clk_000)
        begin
                if (rising_edge(clk_000)) then
                        if (dcm_locked = '1') then
                                case cmd_state is
                                        when STATE_START =>
                                                busy_n <= '0';
                                                op_ack <= '0';
                                                init_reset <= '1';
                                                main_sel <= '0';
                                                main_cmd <= CMD_NOP;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                cmd_state <= STATE_INIT;
 
                                        when STATE_INIT =>
                                                init_reset <= '0';
                                                cmd_state <= STATE_WAIT_INIT;
 
                                        when STATE_WAIT_INIT =>
                                                need_ar_rst <= '1';
                                                if (init_done = '1') then
                                                        cmd_state <= STATE_IDLE;
                                                else
                                                        cmd_state <= cmd_state;
                                                end if;
 
                                        when STATE_IDLE =>
                                                -- this is the main hub state
                                                -- this is where reads and writes return to after being completed
                                                busy_n <= '1';
                                                op_ack <= '0';
                                                need_ar_rst <= '0';
                                                main_sel <= '1';
                                                writer_rst <= '1';
                                                reader_rst <= '1';
                                                if (need_ar = '1') then
                                                        cmd_state <= STATE_IDLE_AUTO_REFRESH;
                                                elsif (op = "01") then
                                                        cmd_state <= STATE_READ_ROW_OPEN;
                                                elsif (op = "10") then
                                                        cmd_state <= STATE_WRITE_ROW_OPEN;
                                                else
                                                        cmd_state <= cmd_state;
                                                end if;
 
                                        when STATE_IDLE_AUTO_REFRESH =>
                                                need_ar_rst <= '1';
                                                wait_ar_rst <= '1';
                                                main_cmd <= CMD_AUTO_REFR;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                cmd_state <= STATE_IDLE_WAIT_AR_CTR;
 
                                        when STATE_IDLE_WAIT_AR_CTR =>
                                                wait_ar_rst <= '0';
                                                main_cmd <= CMD_NOP;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                cmd_state <= STATE_IDLE_WAIT_AUTO_REFRESH;
 
                                        when STATE_IDLE_WAIT_AUTO_REFRESH =>
                                                main_cmd <= CMD_NOP;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                if (wait_ar_done = '1') then
                                                        cmd_state <= STATE_IDLE;
                                                else
                                                        cmd_state <= cmd_state;
                                                end if;
 
                                        when STATE_WRITE_ROW_OPEN =>
                                                busy_n <= '0';
                                                dqs_dir <= '1';
                                                dq_dir <= '1';
                                                main_cmd <= CMD_ACTIVE;
                                                main_bank <= addr(25 downto 24);
                                                main_addr <= addr(23 downto 11);
                                                cmd_state <= STATE_WRITE_WAIT_ROW_OPEN;
 
                                        when STATE_WRITE_WAIT_ROW_OPEN =>
                                                main_cmd <= CMD_NOP;
                                                main_bank <= addr(25 downto 24); -- timing kludge
                                                main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
                                                cmd_state <= STATE_WRITE_ISSUE_CMD;
 
                                        when STATE_WRITE_ISSUE_CMD =>
                                                writer_rst <= '0';
                                                write_reco_rst <= '1';
                                                main_cmd <= CMD_WRITE;
                                                main_bank <= addr(25 downto 24);
                                                main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
                                                cmd_state <= STATE_WRITE_WAIT_RECOVER;
 
                                        when STATE_WRITE_WAIT_RECOVER =>
                                                op_ack <= '1';
                                                write_reco_rst <= '0';
                                                main_cmd <= CMD_NOP;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                if (write_reco_done = '1') then
                                                        cmd_state <= STATE_IDLE;
                                                else
                                                        cmd_state <= cmd_state;
                                                end if;
 
                                        when STATE_READ_ROW_OPEN =>
                                                busy_n <= '0';
                                                dqs_dir <= '0';
                                                dq_dir <= '0';
                                                main_cmd <= CMD_ACTIVE;
                                                main_bank <= addr(25 downto 24);
                                                main_addr <= addr(23 downto 11);
                                                cmd_state <= STATE_READ_WAIT_ROW_OPEN;
 
                                        when STATE_READ_WAIT_ROW_OPEN =>
                                                main_cmd <= CMD_NOP;
                                                main_bank <= addr(25 downto 24); -- timing kludge
                                                main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
                                                cmd_state <= STATE_READ_ISSUE_CMD;
 
                                        when STATE_READ_ISSUE_CMD =>
                                                read_wait_rst <= '1';
                                                main_cmd <= CMD_READ;
                                                main_bank <= addr(25 downto 24);
                                                main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
                                                cmd_state <= STATE_READ_WAIT_CAPTURE;
 
                                        when STATE_READ_WAIT_CAPTURE =>
                                                op_ack <= '1';
                                                read_wait_rst <= '0';
                                                reader_rst <= '0';
                                                main_cmd <= CMD_NOP;
                                                main_bank <= "00";
                                                main_addr <= "0000000000000";
                                                if (read_wait_done = '1') then
                                                        cmd_state <= STATE_IDLE;
                                                else
                                                        cmd_state <= cmd_state;
                                                end if;
                                end case;
                        end if;
                end if;
        end process;
 
end impl;
 
 

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[/] [sdram_controller/] [trunk/] [sdram.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	lynn0p	`----------------------------------------------------------------------------------`
2			`-- Company: OPL Aerospatiale AG`
3			`-- Engineer: Owen Lynn <lynn0p@hotmail.com>`
4			`--`
5			`-- Create Date: 14:25:41 08/20/2009`
6			`-- Design Name: DDR SDRAM Controller`
7			`-- Module Name: sdram_controller - impl`
8			`-- Project Name:`
9			`-- Target Devices: Spartan3e Starter Board`
10			`-- Tool versions: ISE 11.2`
11			`-- Description: This is the main controller module. This is where the signals to/from the DDR SDRAM chip happen.`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>`
19			`-- Released under the GNU Lesser General Public License, Version 3`
20			`--`
21			`----------------------------------------------------------------------------------`
22			`library IEEE;`
23			`use IEEE.STD_LOGIC_1164.ALL;`
24			`use IEEE.STD_LOGIC_ARITH.ALL;`
25			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
26
27			`---- Uncomment the following library declaration if instantiating`
28			`---- any Xilinx primitives in this code.`
29			`library UNISIM;`
30			`use UNISIM.VComponents.all;`
31
32			`-- This is not meant to be a high performance controller. No fancy command scheduling, does the bare minimum to work without screwing up timing.`
33			`-- Do NOT put this controller in something mission critical! This is the creation of a guy in his bedroom, learning digital circuits.`
34			`-- Intended to be used exclusively with the Spartan3e Starter Board and targets the mt46v32m16 chip. Dunno if it will work anywhere else.`
35			`-- Uses the ODDR2 and DCM Xilinx primitives, for other FPGAs, you'll need to patch in equivalents. See sdram_support for the details.`
36			`-- I'd strongly recommend running it through a post-PAR simulation if you're porting to any other FPGA, as the timings will change on you.`
37			`-- Consumes two DCMs, runs off of the main 50mhz board clock. Could possibly consume one DCM if you want to feed it the 100mhz clock directly.`
38			`-- Has an 8bit wide datapath, moderate changes could support 16bits, 32 bits you'll have to work some. You want more than that, you'll`
39			`-- be doing brain surgery on the FSMs - good luck.`
40
41			`-- This design has been tested with the testbench only. There may be glitches hidden in here somewhere still. Consider this to be an alpha release.`
42			`-- Did I mention that you shouldn't put this in anything mission critical?`
43
44			`-- Be careful with the synthesizer settings too. Do not let the FSM extractor choose something other than one-hot. Be careful with register`
45			`-- removal.`
46
47			`-- TODO: implement reset signal`
48			`entity sdram_controller is`
49			`port( -- user facing signals`
50			`clk50mhz : in std_logic;`
51			`en : in std_logic;`
52			`reset : in std_logic;`
53			`op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write`
54			`addr : in std_logic_vector(25 downto 0); -- address to read/write`
55			`op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high`
56			`busy_n : out std_logic; -- busy when LOW, ops will be ignored until busy goes high again`
57			`data_o : out std_logic_vector(7 downto 0); -- data from read shows up here`
58			`data_i : in std_logic_vector(7 downto 0); -- data to write needs to be here`
59
60			`-- SDRAM facing signals`
61			`dram_clkp : out std_logic; -- 0 deg phase 100mhz clock going out to SDRAM chip`
62			`dram_clkn : out std_logic; -- 180 deg phase version of dram_clkp`
63			`dram_clke : out std_logic; -- clock enable, owned by the init module`
64			`dram_cs : out std_logic; -- tied low upon powerup`
65			`dram_cmd : out std_logic_vector(2 downto 0); -- this is the command vector <we_n,cas_n,ras_n>`
66			`dram_bank : out std_logic_vector(1 downto 0); -- bank address`
67			`dram_addr : out std_logic_vector(12 downto 0); -- row/col/mode register`
68			`dram_dm : out std_logic_vector(1 downto 0); -- masks used for writing`
69			`dram_dqs : inout std_logic_vector(1 downto 0); -- strobes used for writing`
70			`dram_dq : inout std_logic_vector(15 downto 0); -- data lines`
71
72			`-- debug signals (possibly could be repurposed later for wider data)`
73			`debug_reg : out std_logic_vector(7 downto 0)`
74			`);`
75			`end sdram_controller;`
76
77			`architecture impl of sdram_controller is`
78
79			`-- component decls begin here`
80			`component sdram_dcm is`
81			`port(`
82			`reset : in std_logic;`
83			`clk50mhz : in std_logic;`
84			`locked : out std_logic;`
85			`dram_clkp : out std_logic;`
86			`dram_clkn : out std_logic;`
87			`clk_000 : out std_logic;`
88			`clk_090 : out std_logic;`
89			`clk_180 : out std_logic;`
90			`clk_270 : out std_logic`
91			`);`
92			`end component;`
93
94			`component oddr2_2 is`
95			`port(`
96			`Q : out std_logic_vector(1 downto 0);`
97			`C0 : in std_logic;`
98			`C1 : in std_logic;`
99			`CE : in std_logic;`
100			`D0 : in std_logic_vector(1 downto 0);`
101			`D1 : in std_logic_vector(1 downto 0);`
102			`R : in std_logic;`
103			`S : in std_logic );`
104			`end component;`
105
106			`component oddr2_3 is`
107			`port(`
108			`Q : out std_logic_vector(2 downto 0);`
109			`C0 : in std_logic;`
110			`C1 : in std_logic;`
111			`CE : in std_logic;`
112			`D0 : in std_logic_vector(2 downto 0);`
113			`D1 : in std_logic_vector(2 downto 0);`
114			`R : in std_logic;`
115			`S : in std_logic );`
116			`end component;`
117
118			`component oddr2_13 is`
119			`port(`
120			`Q : out std_logic_vector(12 downto 0);`
121			`C0 : in std_logic;`
122			`C1 : in std_logic;`
123			`CE : in std_logic;`
124			`D0 : in std_logic_vector(12 downto 0);`
125			`D1 : in std_logic_vector(12 downto 0);`
126			`R : in std_logic;`
127			`S : in std_logic );`
128			`end component;`
129
130			`component inout_switch_2 is`
131			`port (`
132			`ioport : inout std_logic_vector(1 downto 0);`
133			`dir : in std_logic;`
134			`data_o : out std_logic_vector(1 downto 0);`
135			`data_i : in std_logic_vector(1 downto 0)`
136			`);`
137			`end component;`
138
139			`component inout_switch_16 is`
140			`port (`
141			`ioport : inout std_logic_vector(15 downto 0);`
142			`dir : in std_logic;`
143			`data_o : out std_logic_vector(15 downto 0);`
144			`data_i : in std_logic_vector(15 downto 0)`
145			`);`
146			`end component;`
147
148			`component sdram_reader is`
149			`port(`
150			`clk000 : in std_logic;`
151			`clk270 : in std_logic;`
152			`rst : in std_logic;`
153			`dq : in std_logic_vector(15 downto 0);`
154			`data0 : out std_logic_vector(7 downto 0);`
155			`data1 : out std_logic_vector(7 downto 0)`
156			`);`
157			`end component;`
158
159			`component sdram_writer is`
160			`port(`
161			`clk : in std_logic;`
162			`clk090 : in std_logic;`
163			`clk180 : in std_logic;`
164			`clk270 : in std_logic;`
165			`rst : in std_logic;`
166			`addr : in std_logic;`
167			`data_o : in std_logic_vector(7 downto 0);`
168			`dqs : out std_logic_vector(1 downto 0);`
169			`dm : out std_logic_vector(1 downto 0);`
170			`dq : out std_logic_vector(15 downto 0);`
171			`done : out std_logic`
172			`);`
173			`end component;`
174
175			`component wait_counter is`
176			`generic(`
177			`BITS : integer;`
178			`CLKS : integer`
179			`);`
180			`port(`
181			`clk : in std_logic;`
182			`rst : in std_logic;`
183			`done : out std_logic`
184			`);`
185			`end component;`
186
187			`component sdram_init`
188			`port(`
189			`clk_000 : in std_logic;`
190			`reset : in std_logic;`
191
192			`clke : out std_logic;`
193			`cmd : out std_logic_vector(2 downto 0);`
194			`bank : out std_logic_vector(1 downto 0);`
195			`addr : out std_logic_vector(12 downto 0);`
196			`done : out std_logic`
197			`);`
198			`end component;`
199
200			`component cmd_bank_addr_switch is`
201			`port(`
202			`sel : in std_logic;`
203			`cmd0_in : in std_logic_vector(2 downto 0);`
204			`bank0_in : in std_logic_vector(1 downto 0);`
205			`addr0_in : in std_logic_vector(12 downto 0);`
206			`cmd1_in : in std_logic_vector(2 downto 0);`
207			`bank1_in : in std_logic_vector(1 downto 0);`
208			`addr1_in : in std_logic_vector(12 downto 0);`
209			`cmd_out : out std_logic_vector(2 downto 0);`
210			`bank_out : out std_logic_vector(1 downto 0);`
211			`addr_out : out std_logic_vector(12 downto 0)`
212			`);`
213			`end component;`
214			`-- component decls end here`
215
216			`-- DRAM commands - <we,cas,ras>`
217			`constant CMD_NOP : std_logic_vector(2 downto 0) := "111";`
218			`constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "110"; -- opens a row within a bank`
219			`constant CMD_READ : std_logic_vector(2 downto 0) := "101";`
220			`constant CMD_WRITE : std_logic_vector(2 downto 0) := "001";`
221			`constant CMD_BURST_TERM : std_logic_vector(2 downto 0) := "011";`
222			`constant CMD_PRECHARGE : std_logic_vector(2 downto 0) := "010"; -- closes a row within a bank`
223			`constant CMD_AUTO_REFR : std_logic_vector(2 downto 0) := "100";`
224			`constant CMD_LOAD_MR : std_logic_vector(2 downto 0) := "000";`
225
226			`-- various wait counter values`
227			`constant AUTO_REFRESH_CLKS : integer := 700; -- spec says 7.8us, which is 780 clocks @ 100Mhz, I'm setting it to 700`
228			`constant WRITE_RECOVER_CLKS : integer := 5; -- these are fudged a bit, you might be able to shave a clock or two off`
229			`constant READ_DONE_CLKS : integer := 5;`
230
231			`type CMD_STATES is ( STATE_START, STATE_INIT, STATE_WAIT_INIT, STATE_IDLE, STATE_IDLE_AUTO_REFRESH, STATE_IDLE_WAIT_AR_CTR,`
232			`STATE_IDLE_WAIT_AUTO_REFRESH, STATE_WRITE_ROW_OPEN, STATE_WRITE_WAIT_ROW_OPEN, STATE_WRITE_ISSUE_CMD,`
233			`STATE_WRITE_WAIT_RECOVER, STATE_READ_ROW_OPEN, STATE_READ_WAIT_ROW_OPEN, STATE_READ_ISSUE_CMD,`
234			`STATE_READ_WAIT_CAPTURE );`
235
236			`signal cmd_state : CMD_STATES := STATE_START;`
237
238			`signal cmd_oddr2_rising : std_logic_vector(2 downto 0) := CMD_NOP;`
239			`signal bank_oddr2_rising : std_logic_vector(1 downto 0) := "00";`
240			`signal addr_oddr2_rising : std_logic_vector(12 downto 0) := "0000000000000";`
241
242			`signal dqs_in : std_logic_vector(1 downto 0);`
243			`signal dqs_out : std_logic_vector(1 downto 0);`
244			`signal dqs_dir : std_logic;`
245
246			`signal dq_in : std_logic_vector(15 downto 0);`
247			`signal dq_out : std_logic_vector(15 downto 0);`
248			`signal dq_dir : std_logic;`
249
250			`signal reader_rst : std_logic := '1';`
251
252			`signal writer_rst : std_logic := '1';`
253			`signal writer_done : std_logic := '0';`
254
255			`signal dcm_locked : std_logic;`
256			`signal clk_000 : std_logic;`
257			`signal clk_090 : std_logic;`
258			`signal clk_180 : std_logic;`
259			`signal clk_270 : std_logic;`
260
261			`-- init module stuff`
262			`signal init_reset : std_logic;`
263			`signal init_cmd : std_logic_vector(2 downto 0);`
264			`signal init_bank : std_logic_vector(1 downto 0);`
265			`signal init_addr : std_logic_vector(12 downto 0);`
266			`signal init_done : std_logic;`
267
268			`-- main module stuff`
269			`signal main_sel : std_logic;`
270			`signal main_cmd : std_logic_vector(2 downto 0);`
271			`signal main_bank : std_logic_vector(1 downto 0);`
272			`signal main_addr : std_logic_vector(12 downto 0);`
273
274			`-- wait counter stuff`
275			`signal need_ar_rst : std_logic;`
276			`signal need_ar : std_logic;`
277
278			`signal wait_ar_rst : std_logic;`
279			`signal wait_ar_done : std_logic;`
280
281			`signal write_reco_rst : std_logic;`
282			`signal write_reco_done : std_logic;`
283
284			`signal read_wait_rst : std_logic;`
285			`signal read_wait_done : std_logic;`
286
287			`signal data0_o : std_logic_vector(7 downto 0);`
288			`signal data1_o : std_logic_vector(7 downto 0);`
289
290			`begin`
291
292			`-- component instantiations begin here`
293			`DRAM_DCM: sdram_dcm`
294			`port map(`
295			`reset => reset,`
296			`clk50mhz => clk50mhz,`
297			`locked => dcm_locked,`
298			`dram_clkp => dram_clkp,`
299			`dram_clkn => dram_clkn,`
300			`clk_000 => clk_000,`
301			`clk_090 => clk_090,`
302			`clk_180 => clk_180,`
303			`clk_270 => clk_270`
304			`);`
305
306			`DRAM_INIT: sdram_init`
307			`port map(`
308			`clk_000 => clk_000,`
309			`reset => init_reset,`
310			`clke => dram_clke,`
311			`cmd => init_cmd,`
312			`bank => init_bank,`
313			`addr => init_addr,`
314			`done => init_done`
315			`);`
316
317			`CMD_BANK_ADDR_SEL: cmd_bank_addr_switch`
318			`port map(`
319			`sel => main_sel,`
320			`cmd0_in => init_cmd,`
321			`bank0_in => init_bank,`
322			`addr0_in => init_addr,`
323			`cmd1_in => main_cmd,`
324			`bank1_in => main_bank,`
325			`addr1_in => main_addr,`
326			`cmd_out => cmd_oddr2_rising,`
327			`bank_out => bank_oddr2_rising,`
328			`addr_out => addr_oddr2_rising`
329			`);`
330
331			`DRAM_BANK_ODDR2: oddr2_2`
332			`port map(`
333			`Q => dram_bank,`
334			`C0 => clk_270,`
335			`C1 => clk_090,`
336			`CE => '1',`
337			`D0 => bank_oddr2_rising,`
338			`D1 => "00",`
339			`R => '0',`
340			`S => '0' );`
341
342			`DRAM_CMD_ODDR2: oddr2_3`
343			`port map(`
344			`Q => dram_cmd,`
345			`C0 => clk_270,`
346			`C1 => clk_090,`
347			`CE => '1',`
348			`D0 => cmd_oddr2_rising,`
349			`D1 => CMD_NOP,`
350			`R => '0',`
351			`S => '0' );`
352
353			`DRAM_ADDR_ODDR2: oddr2_13`
354			`port map(`
355			`Q => dram_addr,`
356			`C0 => clk_270,`
357			`C1 => clk_090,`
358			`CE => '1',`
359			`D0 => addr_oddr2_rising,`
360			`D1 => "0000000000000",`
361			`R => '0',`
362			`S => '0' );`
363
364			`DQS_SWITCH: inout_switch_2`
365			`port map(`
366			`ioport => dram_dqs,`
367			`dir => dqs_dir,`
368			`data_o => dqs_in,`
369			`data_i => dqs_out`
370			`);`
371
372			`DQ_SWITCH: inout_switch_16`
373			`port map(`
374			`ioport => dram_dq,`
375			`dir => dq_dir,`
376			`data_o => dq_in,`
377			`data_i => dq_out`
378			`);`
379
380			`AR_NEEDED_CTR: wait_counter`
381			`generic map(`
382			`BITS => 10,`
383			`CLKS => AUTO_REFRESH_CLKS`
384			`)`
385			`port map (`
386			`clk => clk_000,`
387			`rst => need_ar_rst,`
388			`done => need_ar`
389			`);`
390
391			`WAIT_AR_CTR: wait_counter`
392			`generic map(`
393			`BITS => 4,`
394			`CLKS => 11`
395			`)`
396			`port map(`
397			`clk => clk_000,`
398			`rst => wait_ar_rst,`
399			`done => wait_ar_done`
400			`);`
401
402			`WRITE_RECOVER_CTR: wait_counter`
403			`generic map(`
404			`BITS => 2,`
405			`CLKS => WRITE_RECOVER_CLKS`
406			`)`
407			`port map(`
408			`clk => clk_000,`
409			`rst => write_reco_rst,`
410			`done => write_reco_done`
411			`);`
412
413			`READ_DONE_CTR: wait_counter`
414			`generic map(`
415			`BITS => 2,`
416			`CLKS => READ_DONE_CLKS`
417			`)`
418			`port map(`
419			`clk => clk_000,`
420			`rst => read_wait_rst,`
421			`done => read_wait_done`
422			`);`
423
424			`READER: sdram_reader`
425			`port map(`
426			`clk000 => clk_000,`
427			`clk270 => clk_270,`
428			`rst => reader_rst,`
429			`dq => dq_in,`
430			`data0 => data0_o,`
431			`data1 => data1_o`
432			`);`
433
434			`WRITER: sdram_writer`
435			`port map(`
436			`clk => clk_000,`
437			`clk090 => clk_090,`
438			`clk180 => clk_180,`
439			`clk270 => clk_270,`
440			`rst => writer_rst,`
441			`addr => addr(0),`
442			`data_o => data_i,`
443			`dqs => dqs_out,`
444			`dm => dram_dm,`
445			`dq => dq_out,`
446			`done => writer_done`
447			`);`
448			`-- end component allocs`
449
450			`dram_cs <= '0';`
451			`data_o <= data1_o when addr(0) = '1' else data0_o;`
452
453			`-- command state machine`
454			`process (clk_000)`
455			`begin`
456			`if (rising_edge(clk_000)) then`
457			`if (dcm_locked = '1') then`
458			`case cmd_state is`
459			`when STATE_START =>`
460			`busy_n <= '0';`
461			`op_ack <= '0';`
462			`init_reset <= '1';`
463			`main_sel <= '0';`
464			`main_cmd <= CMD_NOP;`
465			`main_bank <= "00";`
466			`main_addr <= "0000000000000";`
467			`cmd_state <= STATE_INIT;`
468
469			`when STATE_INIT =>`
470			`init_reset <= '0';`
471			`cmd_state <= STATE_WAIT_INIT;`
472
473			`when STATE_WAIT_INIT =>`
474			`need_ar_rst <= '1';`
475			`if (init_done = '1') then`
476			`cmd_state <= STATE_IDLE;`
477			`else`
478			`cmd_state <= cmd_state;`
479			`end if;`
480
481			`when STATE_IDLE =>`
482			`-- this is the main hub state`
483			`-- this is where reads and writes return to after being completed`
484			`busy_n <= '1';`
485			`op_ack <= '0';`
486			`need_ar_rst <= '0';`
487			`main_sel <= '1';`
488			`writer_rst <= '1';`
489			`reader_rst <= '1';`
490			`if (need_ar = '1') then`
491			`cmd_state <= STATE_IDLE_AUTO_REFRESH;`
492			`elsif (op = "01") then`
493			`cmd_state <= STATE_READ_ROW_OPEN;`
494			`elsif (op = "10") then`
495			`cmd_state <= STATE_WRITE_ROW_OPEN;`
496			`else`
497			`cmd_state <= cmd_state;`
498			`end if;`
499
500			`when STATE_IDLE_AUTO_REFRESH =>`
501			`need_ar_rst <= '1';`
502			`wait_ar_rst <= '1';`
503			`main_cmd <= CMD_AUTO_REFR;`
504			`main_bank <= "00";`
505			`main_addr <= "0000000000000";`
506			`cmd_state <= STATE_IDLE_WAIT_AR_CTR;`
507
508			`when STATE_IDLE_WAIT_AR_CTR =>`
509			`wait_ar_rst <= '0';`
510			`main_cmd <= CMD_NOP;`
511			`main_bank <= "00";`
512			`main_addr <= "0000000000000";`
513			`cmd_state <= STATE_IDLE_WAIT_AUTO_REFRESH;`
514
515			`when STATE_IDLE_WAIT_AUTO_REFRESH =>`
516			`main_cmd <= CMD_NOP;`
517			`main_bank <= "00";`
518			`main_addr <= "0000000000000";`
519			`if (wait_ar_done = '1') then`
520			`cmd_state <= STATE_IDLE;`
521			`else`
522			`cmd_state <= cmd_state;`
523			`end if;`
524
525			`when STATE_WRITE_ROW_OPEN =>`
526			`busy_n <= '0';`
527			`dqs_dir <= '1';`
528			`dq_dir <= '1';`
529			`main_cmd <= CMD_ACTIVE;`
530			`main_bank <= addr(25 downto 24);`
531			`main_addr <= addr(23 downto 11);`
532			`cmd_state <= STATE_WRITE_WAIT_ROW_OPEN;`
533
534			`when STATE_WRITE_WAIT_ROW_OPEN =>`
535			`main_cmd <= CMD_NOP;`
536			`main_bank <= addr(25 downto 24); -- timing kludge`
537			`main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word`
538			`cmd_state <= STATE_WRITE_ISSUE_CMD;`
539
540			`when STATE_WRITE_ISSUE_CMD =>`
541			`writer_rst <= '0';`
542			`write_reco_rst <= '1';`
543			`main_cmd <= CMD_WRITE;`
544			`main_bank <= addr(25 downto 24);`
545			`main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word`
546			`cmd_state <= STATE_WRITE_WAIT_RECOVER;`
547
548			`when STATE_WRITE_WAIT_RECOVER =>`
549			`op_ack <= '1';`
550			`write_reco_rst <= '0';`
551			`main_cmd <= CMD_NOP;`
552			`main_bank <= "00";`
553			`main_addr <= "0000000000000";`
554			`if (write_reco_done = '1') then`
555			`cmd_state <= STATE_IDLE;`
556			`else`
557			`cmd_state <= cmd_state;`
558			`end if;`
559
560			`when STATE_READ_ROW_OPEN =>`
561			`busy_n <= '0';`
562			`dqs_dir <= '0';`
563			`dq_dir <= '0';`
564			`main_cmd <= CMD_ACTIVE;`
565			`main_bank <= addr(25 downto 24);`
566			`main_addr <= addr(23 downto 11);`
567			`cmd_state <= STATE_READ_WAIT_ROW_OPEN;`
568
569			`when STATE_READ_WAIT_ROW_OPEN =>`
570			`main_cmd <= CMD_NOP;`
571			`main_bank <= addr(25 downto 24); -- timing kludge`
572			`main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte`
573			`cmd_state <= STATE_READ_ISSUE_CMD;`
574
575			`when STATE_READ_ISSUE_CMD =>`
576			`read_wait_rst <= '1';`
577			`main_cmd <= CMD_READ;`
578			`main_bank <= addr(25 downto 24);`
579			`main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte`
580			`cmd_state <= STATE_READ_WAIT_CAPTURE;`
581
582			`when STATE_READ_WAIT_CAPTURE =>`
583			`op_ack <= '1';`
584			`read_wait_rst <= '0';`
585			`reader_rst <= '0';`
586			`main_cmd <= CMD_NOP;`
587			`main_bank <= "00";`
588			`main_addr <= "0000000000000";`
589			`if (read_wait_done = '1') then`
590			`cmd_state <= STATE_IDLE;`
591			`else`
592			`cmd_state <= cmd_state;`
593			`end if;`
594			`end case;`
595			`end if;`
596			`end if;`
597			`end process;`
598
599			`end impl;`
600
601