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lynn0p |
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-- Company: OPL Aerospatiale AG
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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--
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-- Create Date: 14:25:41 08/20/2009
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-- Design Name: DDR SDRAM Controller
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-- Module Name: sdram_controller - impl
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-- Project Name:
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-- Target Devices: Spartan3e Starter Board
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-- Tool versions: ISE 11.2
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-- Description: This is the main controller module. This is where the signals to/from the DDR SDRAM chip happen.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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-- Released under the GNU Lesser General Public License, Version 3
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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-- This is not meant to be a high performance controller. No fancy command scheduling, does the bare minimum to work without screwing up timing.
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-- Do NOT put this controller in something mission critical! This is the creation of a guy in his bedroom, learning digital circuits.
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-- Intended to be used exclusively with the Spartan3e Starter Board and targets the mt46v32m16 chip. Dunno if it will work anywhere else.
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-- Uses the ODDR2 and DCM Xilinx primitives, for other FPGAs, you'll need to patch in equivalents. See sdram_support for the details.
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-- I'd strongly recommend running it through a post-PAR simulation if you're porting to any other FPGA, as the timings will change on you.
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-- Consumes two DCMs, runs off of the main 50mhz board clock. Could possibly consume one DCM if you want to feed it the 100mhz clock directly.
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-- Has an 8bit wide datapath, moderate changes could support 16bits, 32 bits you'll have to work some. You want more than that, you'll
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-- be doing brain surgery on the FSMs - good luck.
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-- This design has been tested with the testbench only. There may be glitches hidden in here somewhere still. Consider this to be an alpha release.
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-- Did I mention that you shouldn't put this in anything mission critical?
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-- Be careful with the synthesizer settings too. Do not let the FSM extractor choose something other than one-hot. Be careful with register
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-- removal.
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-- TODO: implement reset signal
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entity sdram_controller is
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port( -- user facing signals
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clk50mhz : in std_logic;
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en : in std_logic;
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reset : in std_logic;
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op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write
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addr : in std_logic_vector(25 downto 0); -- address to read/write
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op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high
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busy_n : out std_logic; -- busy when LOW, ops will be ignored until busy goes high again
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data_o : out std_logic_vector(7 downto 0); -- data from read shows up here
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data_i : in std_logic_vector(7 downto 0); -- data to write needs to be here
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-- SDRAM facing signals
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dram_clkp : out std_logic; -- 0 deg phase 100mhz clock going out to SDRAM chip
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dram_clkn : out std_logic; -- 180 deg phase version of dram_clkp
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dram_clke : out std_logic; -- clock enable, owned by the init module
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dram_cs : out std_logic; -- tied low upon powerup
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dram_cmd : out std_logic_vector(2 downto 0); -- this is the command vector <we_n,cas_n,ras_n>
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dram_bank : out std_logic_vector(1 downto 0); -- bank address
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dram_addr : out std_logic_vector(12 downto 0); -- row/col/mode register
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dram_dm : out std_logic_vector(1 downto 0); -- masks used for writing
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dram_dqs : inout std_logic_vector(1 downto 0); -- strobes used for writing
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dram_dq : inout std_logic_vector(15 downto 0); -- data lines
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-- debug signals (possibly could be repurposed later for wider data)
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debug_reg : out std_logic_vector(7 downto 0)
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);
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end sdram_controller;
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architecture impl of sdram_controller is
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-- component decls begin here
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component sdram_dcm is
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port(
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reset : in std_logic;
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clk50mhz : in std_logic;
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locked : out std_logic;
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dram_clkp : out std_logic;
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dram_clkn : out std_logic;
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clk_000 : out std_logic;
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clk_090 : out std_logic;
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clk_180 : out std_logic;
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clk_270 : out std_logic
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);
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end component;
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component oddr2_2 is
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port(
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Q : out std_logic_vector(1 downto 0);
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C0 : in std_logic;
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C1 : in std_logic;
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CE : in std_logic;
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D0 : in std_logic_vector(1 downto 0);
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D1 : in std_logic_vector(1 downto 0);
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R : in std_logic;
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S : in std_logic );
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end component;
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component oddr2_3 is
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port(
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Q : out std_logic_vector(2 downto 0);
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C0 : in std_logic;
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C1 : in std_logic;
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CE : in std_logic;
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D0 : in std_logic_vector(2 downto 0);
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D1 : in std_logic_vector(2 downto 0);
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R : in std_logic;
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S : in std_logic );
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end component;
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component oddr2_13 is
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port(
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Q : out std_logic_vector(12 downto 0);
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C0 : in std_logic;
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C1 : in std_logic;
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CE : in std_logic;
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D0 : in std_logic_vector(12 downto 0);
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D1 : in std_logic_vector(12 downto 0);
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R : in std_logic;
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S : in std_logic );
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end component;
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component inout_switch_2 is
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port (
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ioport : inout std_logic_vector(1 downto 0);
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dir : in std_logic;
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data_i : in std_logic_vector(1 downto 0)
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);
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end component;
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component inout_switch_16 is
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port (
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ioport : inout std_logic_vector(15 downto 0);
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dir : in std_logic;
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data_o : out std_logic_vector(15 downto 0);
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data_i : in std_logic_vector(15 downto 0)
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);
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end component;
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component sdram_reader is
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port(
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clk270 : in std_logic;
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rst : in std_logic;
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dq : in std_logic_vector(15 downto 0);
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data0 : out std_logic_vector(7 downto 0);
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data1 : out std_logic_vector(7 downto 0)
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);
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end component;
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component sdram_writer is
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port(
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clk : in std_logic;
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clk090 : in std_logic;
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clk180 : in std_logic;
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clk270 : in std_logic;
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rst : in std_logic;
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addr : in std_logic;
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data_o : in std_logic_vector(7 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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6 |
lynn0p |
dq : out std_logic_vector(15 downto 0)
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2 |
lynn0p |
);
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end component;
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component wait_counter is
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generic(
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BITS : integer;
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CLKS : integer
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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done : out std_logic
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);
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end component;
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component sdram_init
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port(
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clk_000 : in std_logic;
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reset : in std_logic;
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clke : out std_logic;
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cmd : out std_logic_vector(2 downto 0);
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bank : out std_logic_vector(1 downto 0);
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addr : out std_logic_vector(12 downto 0);
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done : out std_logic
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);
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end component;
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component cmd_bank_addr_switch is
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port(
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sel : in std_logic;
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cmd0_in : in std_logic_vector(2 downto 0);
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bank0_in : in std_logic_vector(1 downto 0);
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addr0_in : in std_logic_vector(12 downto 0);
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cmd1_in : in std_logic_vector(2 downto 0);
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bank1_in : in std_logic_vector(1 downto 0);
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addr1_in : in std_logic_vector(12 downto 0);
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cmd_out : out std_logic_vector(2 downto 0);
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bank_out : out std_logic_vector(1 downto 0);
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addr_out : out std_logic_vector(12 downto 0)
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);
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end component;
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-- component decls end here
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-- DRAM commands - <we,cas,ras>
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constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
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constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "110"; -- opens a row within a bank
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constant CMD_READ : std_logic_vector(2 downto 0) := "101";
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constant CMD_WRITE : std_logic_vector(2 downto 0) := "001";
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constant CMD_BURST_TERM : std_logic_vector(2 downto 0) := "011";
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constant CMD_PRECHARGE : std_logic_vector(2 downto 0) := "010"; -- closes a row within a bank
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constant CMD_AUTO_REFR : std_logic_vector(2 downto 0) := "100";
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constant CMD_LOAD_MR : std_logic_vector(2 downto 0) := "000";
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-- various wait counter values
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constant AUTO_REFRESH_CLKS : integer := 700; -- spec says 7.8us, which is 780 clocks @ 100Mhz, I'm setting it to 700
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constant WRITE_RECOVER_CLKS : integer := 5; -- these are fudged a bit, you *might* be able to shave a clock or two off
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constant READ_DONE_CLKS : integer := 5;
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type CMD_STATES is ( STATE_START, STATE_INIT, STATE_WAIT_INIT, STATE_IDLE, STATE_IDLE_AUTO_REFRESH, STATE_IDLE_WAIT_AR_CTR,
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STATE_IDLE_WAIT_AUTO_REFRESH, STATE_WRITE_ROW_OPEN, STATE_WRITE_WAIT_ROW_OPEN, STATE_WRITE_ISSUE_CMD,
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STATE_WRITE_WAIT_RECOVER, STATE_READ_ROW_OPEN, STATE_READ_WAIT_ROW_OPEN, STATE_READ_ISSUE_CMD,
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STATE_READ_WAIT_CAPTURE );
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signal cmd_state : CMD_STATES := STATE_START;
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signal cmd_oddr2_rising : std_logic_vector(2 downto 0) := CMD_NOP;
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signal bank_oddr2_rising : std_logic_vector(1 downto 0) := "00";
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signal addr_oddr2_rising : std_logic_vector(12 downto 0) := "0000000000000";
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signal dqs_out : std_logic_vector(1 downto 0);
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signal dqs_dir : std_logic;
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signal dq_in : std_logic_vector(15 downto 0);
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signal dq_out : std_logic_vector(15 downto 0);
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signal dq_dir : std_logic;
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signal reader_rst : std_logic := '1';
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signal writer_rst : std_logic := '1';
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signal dcm_locked : std_logic;
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signal clk_000 : std_logic;
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signal clk_090 : std_logic;
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signal clk_180 : std_logic;
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signal clk_270 : std_logic;
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-- init module stuff
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signal init_reset : std_logic;
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signal init_cmd : std_logic_vector(2 downto 0);
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signal init_bank : std_logic_vector(1 downto 0);
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signal init_addr : std_logic_vector(12 downto 0);
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signal init_done : std_logic;
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-- main module stuff
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signal main_sel : std_logic;
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signal main_cmd : std_logic_vector(2 downto 0);
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signal main_bank : std_logic_vector(1 downto 0);
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signal main_addr : std_logic_vector(12 downto 0);
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-- wait counter stuff
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signal need_ar_rst : std_logic;
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signal need_ar : std_logic;
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signal wait_ar_rst : std_logic;
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signal wait_ar_done : std_logic;
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signal write_reco_rst : std_logic;
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signal write_reco_done : std_logic;
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signal read_wait_rst : std_logic;
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signal read_wait_done : std_logic;
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signal data0_o : std_logic_vector(7 downto 0);
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signal data1_o : std_logic_vector(7 downto 0);
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begin
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-- component instantiations begin here
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DRAM_DCM: sdram_dcm
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port map(
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reset => reset,
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clk50mhz => clk50mhz,
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locked => dcm_locked,
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dram_clkp => dram_clkp,
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dram_clkn => dram_clkn,
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clk_000 => clk_000,
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clk_090 => clk_090,
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clk_180 => clk_180,
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clk_270 => clk_270
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);
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DRAM_INIT: sdram_init
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port map(
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clk_000 => clk_000,
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reset => init_reset,
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clke => dram_clke,
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cmd => init_cmd,
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bank => init_bank,
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addr => init_addr,
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done => init_done
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);
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CMD_BANK_ADDR_SEL: cmd_bank_addr_switch
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port map(
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sel => main_sel,
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cmd0_in => init_cmd,
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bank0_in => init_bank,
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addr0_in => init_addr,
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cmd1_in => main_cmd,
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|
|
bank1_in => main_bank,
|
| 319 |
|
|
addr1_in => main_addr,
|
| 320 |
|
|
cmd_out => cmd_oddr2_rising,
|
| 321 |
|
|
bank_out => bank_oddr2_rising,
|
| 322 |
|
|
addr_out => addr_oddr2_rising
|
| 323 |
|
|
);
|
| 324 |
|
|
|
| 325 |
|
|
DRAM_BANK_ODDR2: oddr2_2
|
| 326 |
|
|
port map(
|
| 327 |
|
|
Q => dram_bank,
|
| 328 |
|
|
C0 => clk_270,
|
| 329 |
|
|
C1 => clk_090,
|
| 330 |
|
|
CE => '1',
|
| 331 |
|
|
D0 => bank_oddr2_rising,
|
| 332 |
|
|
D1 => "00",
|
| 333 |
|
|
R => '0',
|
| 334 |
|
|
S => '0' );
|
| 335 |
|
|
|
| 336 |
|
|
DRAM_CMD_ODDR2: oddr2_3
|
| 337 |
|
|
port map(
|
| 338 |
|
|
Q => dram_cmd,
|
| 339 |
|
|
C0 => clk_270,
|
| 340 |
|
|
C1 => clk_090,
|
| 341 |
|
|
CE => '1',
|
| 342 |
|
|
D0 => cmd_oddr2_rising,
|
| 343 |
|
|
D1 => CMD_NOP,
|
| 344 |
|
|
R => '0',
|
| 345 |
|
|
S => '0' );
|
| 346 |
|
|
|
| 347 |
|
|
DRAM_ADDR_ODDR2: oddr2_13
|
| 348 |
|
|
port map(
|
| 349 |
|
|
Q => dram_addr,
|
| 350 |
|
|
C0 => clk_270,
|
| 351 |
|
|
C1 => clk_090,
|
| 352 |
|
|
CE => '1',
|
| 353 |
|
|
D0 => addr_oddr2_rising,
|
| 354 |
|
|
D1 => "0000000000000",
|
| 355 |
|
|
R => '0',
|
| 356 |
|
|
S => '0' );
|
| 357 |
|
|
|
| 358 |
|
|
DQS_SWITCH: inout_switch_2
|
| 359 |
|
|
port map(
|
| 360 |
|
|
ioport => dram_dqs,
|
| 361 |
|
|
dir => dqs_dir,
|
| 362 |
|
|
data_i => dqs_out
|
| 363 |
|
|
);
|
| 364 |
|
|
|
| 365 |
|
|
DQ_SWITCH: inout_switch_16
|
| 366 |
|
|
port map(
|
| 367 |
|
|
ioport => dram_dq,
|
| 368 |
|
|
dir => dq_dir,
|
| 369 |
|
|
data_o => dq_in,
|
| 370 |
|
|
data_i => dq_out
|
| 371 |
|
|
);
|
| 372 |
|
|
|
| 373 |
|
|
AR_NEEDED_CTR: wait_counter
|
| 374 |
|
|
generic map(
|
| 375 |
|
|
BITS => 10,
|
| 376 |
|
|
CLKS => AUTO_REFRESH_CLKS
|
| 377 |
|
|
)
|
| 378 |
|
|
port map (
|
| 379 |
|
|
clk => clk_000,
|
| 380 |
|
|
rst => need_ar_rst,
|
| 381 |
|
|
done => need_ar
|
| 382 |
|
|
);
|
| 383 |
|
|
|
| 384 |
|
|
WAIT_AR_CTR: wait_counter
|
| 385 |
|
|
generic map(
|
| 386 |
|
|
BITS => 4,
|
| 387 |
|
|
CLKS => 11
|
| 388 |
|
|
)
|
| 389 |
|
|
port map(
|
| 390 |
|
|
clk => clk_000,
|
| 391 |
|
|
rst => wait_ar_rst,
|
| 392 |
|
|
done => wait_ar_done
|
| 393 |
|
|
);
|
| 394 |
|
|
|
| 395 |
|
|
WRITE_RECOVER_CTR: wait_counter
|
| 396 |
|
|
generic map(
|
| 397 |
|
|
BITS => 2,
|
| 398 |
|
|
CLKS => WRITE_RECOVER_CLKS
|
| 399 |
|
|
)
|
| 400 |
|
|
port map(
|
| 401 |
|
|
clk => clk_000,
|
| 402 |
|
|
rst => write_reco_rst,
|
| 403 |
|
|
done => write_reco_done
|
| 404 |
|
|
);
|
| 405 |
|
|
|
| 406 |
|
|
READ_DONE_CTR: wait_counter
|
| 407 |
|
|
generic map(
|
| 408 |
|
|
BITS => 2,
|
| 409 |
|
|
CLKS => READ_DONE_CLKS
|
| 410 |
|
|
)
|
| 411 |
|
|
port map(
|
| 412 |
|
|
clk => clk_000,
|
| 413 |
|
|
rst => read_wait_rst,
|
| 414 |
|
|
done => read_wait_done
|
| 415 |
|
|
);
|
| 416 |
|
|
|
| 417 |
|
|
READER: sdram_reader
|
| 418 |
|
|
port map(
|
| 419 |
|
|
clk270 => clk_270,
|
| 420 |
|
|
rst => reader_rst,
|
| 421 |
|
|
dq => dq_in,
|
| 422 |
|
|
data0 => data0_o,
|
| 423 |
|
|
data1 => data1_o
|
| 424 |
|
|
);
|
| 425 |
|
|
|
| 426 |
|
|
WRITER: sdram_writer
|
| 427 |
|
|
port map(
|
| 428 |
|
|
clk => clk_000,
|
| 429 |
|
|
clk090 => clk_090,
|
| 430 |
|
|
clk180 => clk_180,
|
| 431 |
|
|
clk270 => clk_270,
|
| 432 |
|
|
rst => writer_rst,
|
| 433 |
|
|
addr => addr(0),
|
| 434 |
|
|
data_o => data_i,
|
| 435 |
|
|
dqs => dqs_out,
|
| 436 |
|
|
dm => dram_dm,
|
| 437 |
6 |
lynn0p |
dq => dq_out
|
| 438 |
2 |
lynn0p |
);
|
| 439 |
|
|
-- end component allocs
|
| 440 |
6 |
lynn0p |
|
| 441 |
|
|
debug_reg <= x"00";
|
| 442 |
2 |
lynn0p |
dram_cs <= '0';
|
| 443 |
|
|
data_o <= data1_o when addr(0) = '1' else data0_o;
|
| 444 |
|
|
|
| 445 |
|
|
-- command state machine
|
| 446 |
|
|
process (clk_000)
|
| 447 |
|
|
begin
|
| 448 |
|
|
if (rising_edge(clk_000)) then
|
| 449 |
|
|
if (dcm_locked = '1') then
|
| 450 |
|
|
case cmd_state is
|
| 451 |
|
|
when STATE_START =>
|
| 452 |
|
|
busy_n <= '0';
|
| 453 |
|
|
op_ack <= '0';
|
| 454 |
|
|
init_reset <= '1';
|
| 455 |
|
|
main_sel <= '0';
|
| 456 |
|
|
main_cmd <= CMD_NOP;
|
| 457 |
|
|
main_bank <= "00";
|
| 458 |
|
|
main_addr <= "0000000000000";
|
| 459 |
|
|
cmd_state <= STATE_INIT;
|
| 460 |
|
|
|
| 461 |
|
|
when STATE_INIT =>
|
| 462 |
|
|
init_reset <= '0';
|
| 463 |
|
|
cmd_state <= STATE_WAIT_INIT;
|
| 464 |
|
|
|
| 465 |
|
|
when STATE_WAIT_INIT =>
|
| 466 |
|
|
need_ar_rst <= '1';
|
| 467 |
|
|
if (init_done = '1') then
|
| 468 |
|
|
cmd_state <= STATE_IDLE;
|
| 469 |
|
|
else
|
| 470 |
|
|
cmd_state <= cmd_state;
|
| 471 |
|
|
end if;
|
| 472 |
|
|
|
| 473 |
|
|
when STATE_IDLE =>
|
| 474 |
|
|
-- this is the main hub state
|
| 475 |
|
|
-- this is where reads and writes return to after being completed
|
| 476 |
|
|
busy_n <= '1';
|
| 477 |
|
|
op_ack <= '0';
|
| 478 |
|
|
need_ar_rst <= '0';
|
| 479 |
|
|
main_sel <= '1';
|
| 480 |
|
|
writer_rst <= '1';
|
| 481 |
|
|
reader_rst <= '1';
|
| 482 |
|
|
if (need_ar = '1') then
|
| 483 |
|
|
cmd_state <= STATE_IDLE_AUTO_REFRESH;
|
| 484 |
6 |
lynn0p |
elsif (op = "01" and en = '1') then
|
| 485 |
2 |
lynn0p |
cmd_state <= STATE_READ_ROW_OPEN;
|
| 486 |
6 |
lynn0p |
elsif (op = "10" and en = '1') then
|
| 487 |
2 |
lynn0p |
cmd_state <= STATE_WRITE_ROW_OPEN;
|
| 488 |
|
|
else
|
| 489 |
|
|
cmd_state <= cmd_state;
|
| 490 |
|
|
end if;
|
| 491 |
|
|
|
| 492 |
|
|
when STATE_IDLE_AUTO_REFRESH =>
|
| 493 |
|
|
need_ar_rst <= '1';
|
| 494 |
|
|
wait_ar_rst <= '1';
|
| 495 |
|
|
main_cmd <= CMD_AUTO_REFR;
|
| 496 |
|
|
main_bank <= "00";
|
| 497 |
|
|
main_addr <= "0000000000000";
|
| 498 |
|
|
cmd_state <= STATE_IDLE_WAIT_AR_CTR;
|
| 499 |
|
|
|
| 500 |
|
|
when STATE_IDLE_WAIT_AR_CTR =>
|
| 501 |
|
|
wait_ar_rst <= '0';
|
| 502 |
|
|
main_cmd <= CMD_NOP;
|
| 503 |
|
|
main_bank <= "00";
|
| 504 |
|
|
main_addr <= "0000000000000";
|
| 505 |
|
|
cmd_state <= STATE_IDLE_WAIT_AUTO_REFRESH;
|
| 506 |
|
|
|
| 507 |
|
|
when STATE_IDLE_WAIT_AUTO_REFRESH =>
|
| 508 |
|
|
main_cmd <= CMD_NOP;
|
| 509 |
|
|
main_bank <= "00";
|
| 510 |
|
|
main_addr <= "0000000000000";
|
| 511 |
|
|
if (wait_ar_done = '1') then
|
| 512 |
|
|
cmd_state <= STATE_IDLE;
|
| 513 |
|
|
else
|
| 514 |
|
|
cmd_state <= cmd_state;
|
| 515 |
|
|
end if;
|
| 516 |
|
|
|
| 517 |
|
|
when STATE_WRITE_ROW_OPEN =>
|
| 518 |
|
|
busy_n <= '0';
|
| 519 |
|
|
dqs_dir <= '1';
|
| 520 |
|
|
dq_dir <= '1';
|
| 521 |
|
|
main_cmd <= CMD_ACTIVE;
|
| 522 |
|
|
main_bank <= addr(25 downto 24);
|
| 523 |
|
|
main_addr <= addr(23 downto 11);
|
| 524 |
|
|
cmd_state <= STATE_WRITE_WAIT_ROW_OPEN;
|
| 525 |
|
|
|
| 526 |
|
|
when STATE_WRITE_WAIT_ROW_OPEN =>
|
| 527 |
|
|
main_cmd <= CMD_NOP;
|
| 528 |
|
|
main_bank <= addr(25 downto 24); -- timing kludge
|
| 529 |
|
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
|
| 530 |
|
|
cmd_state <= STATE_WRITE_ISSUE_CMD;
|
| 531 |
|
|
|
| 532 |
|
|
when STATE_WRITE_ISSUE_CMD =>
|
| 533 |
|
|
writer_rst <= '0';
|
| 534 |
|
|
write_reco_rst <= '1';
|
| 535 |
|
|
main_cmd <= CMD_WRITE;
|
| 536 |
|
|
main_bank <= addr(25 downto 24);
|
| 537 |
|
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
|
| 538 |
|
|
cmd_state <= STATE_WRITE_WAIT_RECOVER;
|
| 539 |
|
|
|
| 540 |
|
|
when STATE_WRITE_WAIT_RECOVER =>
|
| 541 |
|
|
op_ack <= '1';
|
| 542 |
|
|
write_reco_rst <= '0';
|
| 543 |
|
|
main_cmd <= CMD_NOP;
|
| 544 |
|
|
main_bank <= "00";
|
| 545 |
|
|
main_addr <= "0000000000000";
|
| 546 |
|
|
if (write_reco_done = '1') then
|
| 547 |
|
|
cmd_state <= STATE_IDLE;
|
| 548 |
|
|
else
|
| 549 |
|
|
cmd_state <= cmd_state;
|
| 550 |
|
|
end if;
|
| 551 |
|
|
|
| 552 |
|
|
when STATE_READ_ROW_OPEN =>
|
| 553 |
|
|
busy_n <= '0';
|
| 554 |
|
|
dqs_dir <= '0';
|
| 555 |
|
|
dq_dir <= '0';
|
| 556 |
|
|
main_cmd <= CMD_ACTIVE;
|
| 557 |
|
|
main_bank <= addr(25 downto 24);
|
| 558 |
|
|
main_addr <= addr(23 downto 11);
|
| 559 |
|
|
cmd_state <= STATE_READ_WAIT_ROW_OPEN;
|
| 560 |
|
|
|
| 561 |
|
|
when STATE_READ_WAIT_ROW_OPEN =>
|
| 562 |
|
|
main_cmd <= CMD_NOP;
|
| 563 |
|
|
main_bank <= addr(25 downto 24); -- timing kludge
|
| 564 |
|
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
|
| 565 |
|
|
cmd_state <= STATE_READ_ISSUE_CMD;
|
| 566 |
|
|
|
| 567 |
|
|
when STATE_READ_ISSUE_CMD =>
|
| 568 |
|
|
read_wait_rst <= '1';
|
| 569 |
|
|
main_cmd <= CMD_READ;
|
| 570 |
|
|
main_bank <= addr(25 downto 24);
|
| 571 |
|
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
|
| 572 |
|
|
cmd_state <= STATE_READ_WAIT_CAPTURE;
|
| 573 |
|
|
|
| 574 |
|
|
when STATE_READ_WAIT_CAPTURE =>
|
| 575 |
|
|
op_ack <= '1';
|
| 576 |
|
|
read_wait_rst <= '0';
|
| 577 |
|
|
reader_rst <= '0';
|
| 578 |
|
|
main_cmd <= CMD_NOP;
|
| 579 |
|
|
main_bank <= "00";
|
| 580 |
|
|
main_addr <= "0000000000000";
|
| 581 |
|
|
if (read_wait_done = '1') then
|
| 582 |
|
|
cmd_state <= STATE_IDLE;
|
| 583 |
|
|
else
|
| 584 |
|
|
cmd_state <= cmd_state;
|
| 585 |
|
|
end if;
|
| 586 |
|
|
end case;
|
| 587 |
|
|
end if;
|
| 588 |
|
|
end if;
|
| 589 |
|
|
end process;
|
| 590 |
|
|
|
| 591 |
|
|
end impl;
|
| 592 |
|
|
|
| 593 |
|
|
|
