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[/] [sdram_controller/] [trunk/] [sdram_init.vhd] - Blame information for rev 2

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1 2 lynn0p
----------------------------------------------------------------------------------
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-- Company: OPL Aerospatiale AG
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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-- 
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-- Create Date:    17:29:55 08/29/2009 
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-- Design Name: 
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-- Module Name:    sdram_init - impl 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: This is the FSM that gets the DDR SDRAM chip past init. Otherwise
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--  the main FSM would grow pretty unwieldy and unstable.
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--  Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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--  Released under the GNU Lesser General Public License, Version 3
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity sdram_init is
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        port(
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                clk_000 : in std_logic;
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                reset   : in std_logic;
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                clke  : out std_logic;
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                cmd   : out std_logic_vector(2 downto 0);
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                bank  : out std_logic_vector(1 downto 0);
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                addr  : out std_logic_vector(12 downto 0);
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                done  : out std_logic
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        );
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end sdram_init;
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architecture impl of sdram_init is
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        component wait_counter is
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                generic(
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                        BITS : integer;
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                        CLKS : integer
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                );
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                port(
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                         clk : in std_logic;
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                         rst : in std_logic;
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                        done : out std_logic
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                );
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        end component;
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        constant CMD_NOP        : std_logic_vector(2 downto 0)  := "111";
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        constant CMD_PRECHARGE  : std_logic_vector(2 downto 0)  := "010";
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        constant CMD_AUTO_REFR  : std_logic_vector(2 downto 0)  := "100";
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        constant CMD_LOAD_MR    : std_logic_vector(2 downto 0)  := "000";
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        constant CLKS_200US         : integer := 21000; -- well, it's supposed to be 20000, but i'm fudging with 21000
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        type INIT_STATES is ( STATE_START, STATE_WAIT200US, STATE_CLKE, STATE_PRECHARGE_ALL0, STATE_WAIT_PRECHARGE_ALL0, STATE_LOAD_MRE,
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                              STATE_WAIT_MRE, STATE_LOAD_MRN, STATE_WAIT_MRN, STATE_PRECHARGE_ALL1, STATE_WAIT_PRECHARGE_ALL1, STATE_AUTO_REFRESH0,
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                                                                 STATE_WAIT_AR_CTR0, STATE_WAIT_AUTO_REFRESH0, STATE_AUTO_REFRESH1, STATE_WAIT_AR_CTR1, STATE_WAIT_AUTO_REFRESH1,
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                                                                 STATE_WAIT_200_CLOCKS, STATE_DONE );
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        signal init_state : INIT_STATES;
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        signal wait200us_rst : std_logic;
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        signal wait200us_done : std_logic;
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        signal wait_ar_rst : std_logic;
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        signal wait_ar_done : std_logic;
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        signal wait_200clks_rst : std_logic;
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        signal wait_200clks_done : std_logic;
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        signal a058 : std_logic;
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        signal a10 : std_logic;
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        signal bk0 : std_logic;
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begin
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        WAIT200US_CTR: wait_counter
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        generic map(
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                BITS => 16,
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                CLKS => CLKS_200US
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        )
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        port map(
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                clk => clk_000,
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                rst => wait200us_rst,
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                done => wait200us_done
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        );
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        WAIT_AR_CTR: wait_counter
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        generic map(
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                BITS => 4,
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                CLKS => 11
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        )
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        port map(
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                clk => clk_000,
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                rst => wait_ar_rst,
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                done => wait_ar_done
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        );
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        WAIT_200CLKS_CTR: wait_counter
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        generic map(
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                BITS => 8,
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                CLKS => 200
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        )
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        port map(
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                clk => clk_000,
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                rst => wait_200clks_rst,
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                done => wait_200clks_done
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        );
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        -- really optimized output of FSM
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        addr(12) <= '0';
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        addr(11) <= '0';
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        addr(10) <= a10;
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        addr(9)  <= '0';
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        addr(8)  <= a058;
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        addr(7)  <= '0';
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        addr(6)  <= '0';
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        addr(5)  <= a058;
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        addr(4)  <= '0';
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        addr(3)  <= '0';
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        addr(2)  <= '0';
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        addr(1)  <= '0';
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        addr(0)  <= a058;
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        bank(1) <= '0';
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        bank(0) <= bk0;
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        process (clk_000, reset)
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        begin
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                if (reset = '1') then
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                        init_state <= STATE_START;
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                        wait200us_rst <= '1';
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                        wait_ar_rst <= '1';
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                        wait_200clks_rst <= '1';
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                        clke <= '0';
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                        cmd <= CMD_NOP;
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                        bk0 <= '0';
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                        a10 <= '0'; a058 <= '0';
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                        done <= '0';
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                elsif (rising_edge(clk_000)) then
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                        case init_state is
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                                when STATE_START =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT200US;
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                                when STATE_WAIT200US =>
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                                        wait200us_rst <= '0';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        if( wait200us_done = '1' ) then
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                                                init_state <= STATE_CLKE;
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                                        else
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                                                init_state <= init_state;
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                                        end if;
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                                when STATE_CLKE =>
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                                        clke <= '1';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '1'; a058 <= '0'; -- timing kludge
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                                        init_state <= STATE_PRECHARGE_ALL0;
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                                when STATE_PRECHARGE_ALL0 =>
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                                        cmd <= CMD_PRECHARGE;
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                                        bk0 <= '0';
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                                        a10 <= '1'; a058 <= '0';
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                                        init_state <= STATE_WAIT_PRECHARGE_ALL0;
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                                when STATE_WAIT_PRECHARGE_ALL0 =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_LOAD_MRE;
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                                when STATE_LOAD_MRE =>
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                                        cmd <= CMD_LOAD_MR;
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                                        bk0 <= '1';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT_MRE;
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                                when STATE_WAIT_MRE =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '1'; -- timing kludge
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                                        init_state <= STATE_LOAD_MRN;
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                                when STATE_LOAD_MRN =>
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                                        cmd <= CMD_LOAD_MR;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '1';
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                                        init_state <= STATE_WAIT_MRN;
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                                when STATE_WAIT_MRN =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '1'; -- timing kludge
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                                        init_state <= STATE_PRECHARGE_ALL1;
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                                when STATE_PRECHARGE_ALL1 =>
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                                        cmd <= CMD_PRECHARGE;
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                                        bk0 <= '0';
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                                        a10 <= '1'; a058 <= '0';
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                                        init_state <= STATE_WAIT_PRECHARGE_ALL1;
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                                when STATE_WAIT_PRECHARGE_ALL1 =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_AUTO_REFRESH0;
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                                when STATE_AUTO_REFRESH0 =>
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                                        wait_ar_rst <= '1';
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                                        cmd <= CMD_AUTO_REFR;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT_AR_CTR0;
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                                when STATE_WAIT_AR_CTR0 =>
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                                        wait_ar_rst <= '0';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT_AUTO_REFRESH0;
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                                when STATE_WAIT_AUTO_REFRESH0 =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        if (wait_ar_done = '1') then
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                                                init_state <= STATE_AUTO_REFRESH1;
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                                        else
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                                                init_state <= init_state;
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                                        end if;
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                                when STATE_AUTO_REFRESH1 =>
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                                        wait_ar_rst <= '1';
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                                        cmd <= CMD_AUTO_REFR;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT_AR_CTR1;
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                                when STATE_WAIT_AR_CTR1 =>
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                                        wait_ar_rst <= '0';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
259
                                        a10 <= '0'; a058 <= '0';
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                                        init_state <= STATE_WAIT_AUTO_REFRESH1;
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262
                                when STATE_WAIT_AUTO_REFRESH1 =>
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                                        wait_200clks_rst <= '1';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        if (wait_ar_done = '1') then
268
                                                init_state <= STATE_WAIT_200_CLOCKS;
269
                                        else
270
                                                init_state <= init_state;
271
                                        end if;
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273
                                when STATE_WAIT_200_CLOCKS =>
274
                                        wait_200clks_rst <= '0';
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                                        if (wait_200clks_done = '1') then
279
                                                init_state <= STATE_DONE;
280
                                        else
281
                                                init_state <= init_state;
282
                                        end if;
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284
                                 when STATE_DONE =>
285
                                        done <= '1';
286
                                        cmd <= CMD_NOP;
287
                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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290
                                when others =>
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                                        cmd <= CMD_NOP;
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                                        bk0 <= '0';
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                                        a10 <= '0'; a058 <= '0';
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                        end case;
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                end if;
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        end process;
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end impl;
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