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[/] [sdram_controller/] [trunk/] [sdram_support.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------
-- Company: OPL Aerospatiale AG
-- Engineer: Owen Lynn <lynn0p@hotmail.com>
-- 
-- Create Date:    15:35:09 08/18/2009 
-- Design Name: 
-- Module Name:    sdram_support - impl 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: This contains all the dirty primitives used by all the other modules.
--  Anything that's small and would be considered plumbing goes in here.
--
-- Dependencies: Xilinx primitives
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--  Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
--  Released under the GNU Lesser General Public License, Version 3
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity cmd_bank_addr_switch is
        port(
                sel      : in std_logic;
                cmd0_in  : in std_logic_vector(2 downto 0);
                bank0_in : in std_logic_vector(1 downto 0);
                addr0_in : in std_logic_vector(12 downto 0);
                cmd1_in  : in std_logic_vector(2 downto 0);
                bank1_in : in std_logic_vector(1 downto 0);
                addr1_in : in std_logic_vector(12 downto 0);
                cmd_out  : out std_logic_vector(2 downto 0);
                bank_out : out std_logic_vector(1 downto 0);
                addr_out : out std_logic_vector(12 downto 0)
        );
end cmd_bank_addr_switch;
 
architecture impl of cmd_bank_addr_switch is
begin
 
        cmd_out  <= cmd0_in  when sel = '0' else cmd1_in;
        bank_out <= bank0_in when sel = '0' else bank1_in;
        addr_out <= addr0_in when sel = '0' else addr1_in;
 
end impl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity wait_counter is
        generic(
                BITS : integer;
                CLKS : integer
        );
        port(
            clk : in std_logic;
                 rst : in std_logic;
                done : out std_logic
        );
end wait_counter;
 
architecture impl of wait_counter is
 
        signal reg : std_logic_vector(BITS-1 downto 0);
 
begin
 
        process(clk,rst)
        begin
                if (rst = '1') then
                        done <= '0';
                        reg <= CONV_STD_LOGIC_VECTOR(CLKS, BITS);
                elsif (rising_edge(clk)) then
                        if (reg > x"00") then
                                done <= '0';
                                reg <= reg - 1;
                        else
                                done <= '1';
                        end if;
                end if;
        end process;
 
end architecture;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity sdram_dcm is
        port(
           reset           : in  std_logic;
                clk100mhz       : in  std_logic;
                locked          : out std_logic;
                dram_clkp       : out std_logic;
                dram_clkn       : out std_logic;
                clk_000         : out std_logic;
                clk_090         : out std_logic;
                clk_180         : out std_logic;
                clk_270         : out std_logic
        );
end sdram_dcm;
 
architecture impl of sdram_dcm is
 
        signal dcm1_reset       : std_logic;
        signal dcm1_locked      : std_logic;
        signal dcm1_clk_raw_000 : std_logic;
        signal dcm1_clk_raw_090 : std_logic;
        signal dcm1_clk_000     : std_logic;
        signal dcm1_clk_090     : std_logic;
        signal dcm1_clk_180     : std_logic;
        signal dcm1_clk_270     : std_logic;
 
begin
 
        SDRAM_DCM : DCM_SP
   generic map (
      CLKDV_DIVIDE => 2.0,                   --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                             --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 2,                     --  Can be any integer from 1 to 32 
      CLKFX_MULTIPLY => 2,                   --  Can be any integer from 1 to 32
      CLKIN_DIVIDE_BY_2 => FALSE,            --  TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 10.0,                  --  Specify period of input clock
      CLKOUT_PHASE_SHIFT => "NONE",          --  Specify phase shift of "NONE", "FIXED" or "VARIABLE" 
      CLK_FEEDBACK => "1X",                  --  Specify clock feedback of "NONE", "1X" or "2X" 
      DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
                                             --     an integer from 0 to 15
      DLL_FREQUENCY_MODE => "LOW",           -- "HIGH" or "LOW" frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE,         --  Duty cycle correction, TRUE or FALSE
      PHASE_SHIFT => 0,                      --  Amount of fixed phase shift from -255 to 255
      STARTUP_WAIT => FALSE)                 --  Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
   port map (
      CLK0     => dcm1_clk_raw_000,      -- 0 degree DCM CLK ouptput
      CLK90    => dcm1_clk_raw_090,      -- 90 degree DCM CLK output
      CLK180   => open,                  -- 180 degree DCM CLK output
      CLK270   => open,                  -- 270 degree DCM CLK output
      CLK2X    => open,                  -- 2X DCM CLK output
      CLK2X180 => open,                  -- 2X, 180 degree DCM CLK out
      CLKDV    => open,                  -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => open,                  -- DCM CLK synthesis out (M/D) 
      CLKFX180 => open,                  -- 180 degree CLK synthesis out
      LOCKED   => dcm1_locked,           -- DCM LOCK status output (means feedback is in phase with main clock)
      PSDONE   => open,                  -- Dynamic phase adjust done output
      STATUS   => open,                  -- 8-bit DCM status bits output
      CLKFB    => dcm1_clk_000,          -- DCM clock feedback
      CLKIN    => clk100mhz,             -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK    => '0',                   -- Dynamic phase adjust clock input
      PSEN     => '0',                   -- Dynamic phase adjust enable input
      PSINCDEC => '0',                   -- Dynamic phase adjust increment/decrement
      RST      => dcm1_reset             -- DCM asynchronous reset input
   );
        dcm1_reset <= reset;
 
        BUFG_DCM1_000 : BUFG
   port map (
      O => dcm1_clk_000,      -- Clock buffer output
      I => dcm1_clk_raw_000   -- Clock buffer input
   );
 
        BUFG_DCM1_090 : BUFG
   port map (
      O => dcm1_clk_090,      -- Clock buffer output
      I => dcm1_clk_raw_090   -- Clock buffer input
   );
 
        dcm1_clk_180 <= not(dcm1_clk_000);
        dcm1_clk_270 <= not(dcm1_clk_090);
 
        ODDR2_DRAM_CLKP : ODDR2
        generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => dram_clkp,            -- 1-bit output data
      C0 => dcm1_clk_000,        -- 1-bit clock input
      C1 => dcm1_clk_180,        -- 1-bit clock input
      CE => '1',                 -- 1-bit clock enable input
      D0 => '1',                 -- 1-bit data input (associated with C0)
      D1 => '0',                 -- 1-bit data input (associated with C1)
      R => reset,                -- 1-bit reset input
      S => '0'                   -- 1-bit set input
   );
 
        ODDR2_DRAM_CLKN : ODDR2
        generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => dram_clkn,            -- 1-bit output data
      C0 => dcm1_clk_000,        -- 1-bit clock input
      C1 => dcm1_clk_180,        -- 1-bit clock input
      CE => '1',                 -- 1-bit clock enable input
      D0 => '0',                 -- 1-bit data input (associated with C0)
      D1 => '1',                 -- 1-bit data input (associated with C1)
      R => reset,                -- 1-bit reset input
      S => '0'                   -- 1-bit set input
   );
 
        locked <= dcm1_locked;
 
        clk_000 <= dcm1_clk_000;
        clk_090 <= dcm1_clk_090;
        clk_180 <= dcm1_clk_180;
        clk_270 <= dcm1_clk_270;
 
end impl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- just a 2 bit wide ODDR2
entity oddr2_2 is
        port(
                Q  : out std_logic_vector(1 downto 0);
                C0 : in std_logic;
                C1 : in std_logic;
                CE : in std_logic;
                D0 : in std_logic_vector(1 downto 0);
                D1 : in std_logic_vector(1 downto 0);
                R  : in std_logic;
                S  : in std_logic );
end oddr2_2;
 
architecture impl of oddr2_2 is
begin
        ODDR2_0 : ODDR2
        generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(0),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(0),     -- 1-bit data input (associated with C0)
      D1 => D1(0),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
 
  ODDR2_1 : ODDR2
  generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(1),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(1),     -- 1-bit data input (associated with C0)
      D1 => D1(1),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
end impl;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- just a 3 bit wide ODDR2
entity oddr2_3 is
        port(
                Q  : out std_logic_vector(2 downto 0);
                C0 : in std_logic;
                C1 : in std_logic;
                CE : in std_logic;
                D0 : in std_logic_vector(2 downto 0);
                D1 : in std_logic_vector(2 downto 0);
                R  : in std_logic;
                S  : in std_logic );
end oddr2_3;
 
architecture impl of oddr2_3 is
begin
        ODDR2_0 : ODDR2
        generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(0),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(0),     -- 1-bit data input (associated with C0)
      D1 => D1(0),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
 
  ODDR2_1 : ODDR2
  generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(1),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(1),     -- 1-bit data input (associated with C0)
      D1 => D1(1),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
 
  ODDR2_2 : ODDR2
  generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(2),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(2),     -- 1-bit data input (associated with C0)
      D1 => D1(2),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
end impl;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- 2 oddr2_2's
entity oddr2_4 is
   port( Q  : out std_logic_vector(3 downto 0);
         C0 : in std_logic;
         C1 : in std_logic;
         CE : in std_logic;
         D0 : in std_logic_vector(3 downto 0);
         D1 : in std_logic_vector(3 downto 0);
         R  : in std_logic;
         S  : in std_logic );
end oddr2_4;
 
architecture impl of oddr2_4 is
 
        component oddr2_2 is
    port(
                Q  : out std_logic_vector(1 downto 0);
                C0 : in std_logic;
                C1 : in std_logic;
                CE : in std_logic;
                D0 : in std_logic_vector(1 downto 0);
                D1 : in std_logic_vector(1 downto 0);
                R  : in std_logic;
                S  : in std_logic );
        end component;
 
begin
  ODDR2_0 : oddr2_2
  port map (
      Q => Q(1 downto 0),       -- 1-bit output data
      C0 => C0,                 -- 1-bit clock input
      C1 => C1,                 -- 1-bit clock input
      CE => CE,                 -- 1-bit clock enable input
      D0 => D0(1 downto 0),     -- 1-bit data input (associated with C0)
      D1 => D1(1 downto 0),     -- 1-bit data input (associated with C1)
      R => R,                   -- 1-bit reset input
      S => S                    -- 1-bit set input
   );
 
  ODDR2_1 : oddr2_2
   port map (
      Q => Q(3 downto 2),       -- 1-bit output data
      C0 => C0,                 -- 1-bit clock input
      C1 => C1,                 -- 1-bit clock input
      CE => CE,                 -- 1-bit clock enable input
      D0 => D0(3 downto 2),     -- 1-bit data input (associated with C0)
      D1 => D1(3 downto 2),     -- 1-bit data input (associated with C1)
      R => R,                   -- 1-bit reset input
      S => S                    -- 1-bit set input
   );
end impl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- one ODDR2 and 3 4-bit oddr2_4's
entity oddr2_13 is
   port( Q  : out std_logic_vector(12 downto 0);
         C0 : in std_logic;
         C1 : in std_logic;
         CE : in std_logic;
         D0 : in std_logic_vector(12 downto 0);
         D1 : in std_logic_vector(12 downto 0);
         R  : in std_logic;
         S  : in std_logic );
end oddr2_13;
 
architecture impl of oddr2_13 is
 
        component oddr2_4 is
                port(
                        Q  : out std_logic_vector(3 downto 0);
                        C0 : in std_logic;
                        C1 : in std_logic;
                        CE : in std_logic;
                        D0 : in std_logic_vector(3 downto 0);
                        D1 : in std_logic_vector(3 downto 0);
                        R  : in std_logic;
                        S  : in std_logic );
  end component;
 
begin
 
  ODDR2_0 : ODDR2
  generic map(
      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => Q(0),       -- 1-bit output data
      C0 => C0,        -- 1-bit clock input
      C1 => C1,        -- 1-bit clock input
      CE => CE,        -- 1-bit clock enable input
      D0 => D0(0),     -- 1-bit data input (associated with C0)
      D1 => D1(0),     -- 1-bit data input (associated with C1)
      R => R,          -- 1-bit reset input
      S => S           -- 1-bit set input
   );
 
   ODDR2_1 : oddr2_4
   port map(
      Q => Q(4 downto 1),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(4 downto 1),
      D1 => D1(4 downto 1),
      R => R,
      S => S
   );
 
   ODDR2_2 : oddr2_4
   port map(
      Q => Q(8 downto 5),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(8 downto 5),
      D1 => D1(8 downto 5),
      R => R,
      S => S
   );
 
   ODDR2_3 : oddr2_4
   port map(
      Q => Q(12 downto 9),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(12 downto 9),
      D1 => D1(12 downto 9),
      R => R,
      S => S
   );
end impl;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
-- 4 4-bit oddr2_4's
entity oddr2_16 is
   port( Q  : out std_logic_vector(15 downto 0);
         C0 : in std_logic;
         C1 : in std_logic;
         CE : in std_logic;
         D0 : in std_logic_vector(15 downto 0);
         D1 : in std_logic_vector(15 downto 0);
         R  : in std_logic;
         S  : in std_logic );
end oddr2_16;
 
architecture impl of oddr2_16 is
 
        component oddr2_4 is
                port(
                        Q  : out std_logic_vector(3 downto 0);
                        C0 : in std_logic;
                        C1 : in std_logic;
                        CE : in std_logic;
                        D0 : in std_logic_vector(3 downto 0);
                        D1 : in std_logic_vector(3 downto 0);
                        R  : in std_logic;
                        S  : in std_logic );
  end component;
 
begin
        ODDR2_0 : oddr2_4
        port map (
      Q => Q(3 downto 0),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(3 downto 0),
      D1 => D1(3 downto 0),
      R => R,
      S => S
   );
 
        ODDR2_1 : oddr2_4
        port map (
      Q => Q(7 downto 4),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(7 downto 4),
      D1 => D1(7 downto 4),
      R => R,
      S => S
   );
 
        ODDR2_2 : oddr2_4
        port map (
      Q => Q(11 downto 8),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(11 downto 8),
      D1 => D1(11 downto 8),
      R => R,
      S => S
   );
 
        ODDR2_3 : oddr2_4
        port map (
      Q => Q(15 downto 12),
      C0 => C0,
      C1 => C1,
      CE => CE,
      D0 => D0(15 downto 12),
      D1 => D1(15 downto 12),
      R => R,
      S => S
   );
end;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity inout_switch_2 is
        port (
                ioport : inout std_logic_vector(1 downto 0);
                   dir : in std_logic;
                data_i : in std_logic_vector(1 downto 0)
        );
end inout_switch_2;
 
architecture impl of inout_switch_2 is
begin
        ioport <= data_i when dir = '1' else "ZZ";
end impl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity inout_switch_16 is
        port (
                ioport : inout std_logic_vector(15 downto 0);
                   dir : in    std_logic;
                data_o : out   std_logic_vector(15 downto 0);
                data_i : in    std_logic_vector(15 downto 0)
        );
end inout_switch_16;
 
architecture impl of inout_switch_16 is
begin
        data_o <= ioport when dir = '0' else "ZZZZZZZZZZZZZZZZ";
        ioport <= data_i when dir = '1' else "ZZZZZZZZZZZZZZZZ";
end impl;
 
 

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[/] [sdram_controller/] [trunk/] [sdram_support.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	2	lynn0p	`----------------------------------------------------------------------------------`
2			`-- Company: OPL Aerospatiale AG`
3			`-- Engineer: Owen Lynn <lynn0p@hotmail.com>`
4			`--`
5			`-- Create Date: 15:35:09 08/18/2009`
6			`-- Design Name:`
7			`-- Module Name: sdram_support - impl`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description: This contains all the dirty primitives used by all the other modules.`
12			`-- Anything that's small and would be considered plumbing goes in here.`
13			`--`
14			`-- Dependencies: Xilinx primitives`
15			`--`
16			`-- Revision:`
17			`-- Revision 0.01 - File Created`
18			`-- Additional Comments:`
19			`-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>`
20			`-- Released under the GNU Lesser General Public License, Version 3`
21			`--`
22			`----------------------------------------------------------------------------------`
23			`library IEEE;`
24			`use IEEE.STD_LOGIC_1164.ALL;`
25			`use IEEE.STD_LOGIC_ARITH.ALL;`
26			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity cmd_bank_addr_switch is`
34			`port(`
35			`sel : in std_logic;`
36			`cmd0_in : in std_logic_vector(2 downto 0);`
37			`bank0_in : in std_logic_vector(1 downto 0);`
38			`addr0_in : in std_logic_vector(12 downto 0);`
39			`cmd1_in : in std_logic_vector(2 downto 0);`
40			`bank1_in : in std_logic_vector(1 downto 0);`
41			`addr1_in : in std_logic_vector(12 downto 0);`
42			`cmd_out : out std_logic_vector(2 downto 0);`
43			`bank_out : out std_logic_vector(1 downto 0);`
44			`addr_out : out std_logic_vector(12 downto 0)`
45			`);`
46			`end cmd_bank_addr_switch;`
47
48			`architecture impl of cmd_bank_addr_switch is`
49			`begin`
50
51			`cmd_out <= cmd0_in when sel = '0' else cmd1_in;`
52			`bank_out <= bank0_in when sel = '0' else bank1_in;`
53			`addr_out <= addr0_in when sel = '0' else addr1_in;`
54
55			`end impl;`
56
57
58			`library IEEE;`
59			`use IEEE.STD_LOGIC_1164.ALL;`
60			`use IEEE.STD_LOGIC_ARITH.ALL;`
61			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
62
63			`---- Uncomment the following library declaration if instantiating`
64			`---- any Xilinx primitives in this code.`
65			`library UNISIM;`
66			`use UNISIM.VComponents.all;`
67
68			`entity wait_counter is`
69			`generic(`
70			`BITS : integer;`
71			`CLKS : integer`
72			`);`
73			`port(`
74			`clk : in std_logic;`
75			`rst : in std_logic;`
76			`done : out std_logic`
77			`);`
78			`end wait_counter;`
79
80			`architecture impl of wait_counter is`
81
82			`signal reg : std_logic_vector(BITS-1 downto 0);`
83
84			`begin`
85
86			`process(clk,rst)`
87			`begin`
88			`if (rst = '1') then`
89			`done <= '0';`
90			`reg <= CONV_STD_LOGIC_VECTOR(CLKS, BITS);`
91			`elsif (rising_edge(clk)) then`
92			`if (reg > x"00") then`
93			`done <= '0';`
94			`reg <= reg - 1;`
95			`else`
96			`done <= '1';`
97			`end if;`
98			`end if;`
99			`end process;`
100
101			`end architecture;`
102
103
104			`library IEEE;`
105			`use IEEE.STD_LOGIC_1164.ALL;`
106			`use IEEE.STD_LOGIC_ARITH.ALL;`
107			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
108
109			`---- Uncomment the following library declaration if instantiating`
110			`---- any Xilinx primitives in this code.`
111			`library UNISIM;`
112			`use UNISIM.VComponents.all;`
113
114			`entity sdram_dcm is`
115			`port(`
116			`reset : in std_logic;`
117	8	lynn0p	`clk100mhz : in std_logic;`
118	2	lynn0p	`locked : out std_logic;`
119			`dram_clkp : out std_logic;`
120			`dram_clkn : out std_logic;`
121			`clk_000 : out std_logic;`
122			`clk_090 : out std_logic;`
123			`clk_180 : out std_logic;`
124			`clk_270 : out std_logic`
125			`);`
126			`end sdram_dcm;`
127
128			`architecture impl of sdram_dcm is`
129
130			`signal dcm1_reset : std_logic;`
131			`signal dcm1_locked : std_logic;`
132			`signal dcm1_clk_raw_000 : std_logic;`
133			`signal dcm1_clk_raw_090 : std_logic;`
134			`signal dcm1_clk_000 : std_logic;`
135			`signal dcm1_clk_090 : std_logic;`
136			`signal dcm1_clk_180 : std_logic;`
137			`signal dcm1_clk_270 : std_logic;`
138
139			`begin`
140
141	8	lynn0p	`SDRAM_DCM : DCM_SP`
142	2	lynn0p	`generic map (`
143			`CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
144			`-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
145			`CLKFX_DIVIDE => 2, -- Can be any integer from 1 to 32`
146			`CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32`
147			`CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature`
148			`CLKIN_PERIOD => 10.0, -- Specify period of input clock`
149			`CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"`
150			`CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"`
151			`DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or`
152			`-- an integer from 0 to 15`
153			`DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL`
154			`DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE`
155			`PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255`
156			`STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE`
157			`port map (`
158			`CLK0 => dcm1_clk_raw_000, -- 0 degree DCM CLK ouptput`
159			`CLK90 => dcm1_clk_raw_090, -- 90 degree DCM CLK output`
160			`CLK180 => open, -- 180 degree DCM CLK output`
161			`CLK270 => open, -- 270 degree DCM CLK output`
162			`CLK2X => open, -- 2X DCM CLK output`
163			`CLK2X180 => open, -- 2X, 180 degree DCM CLK out`
164			`CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)`
165			`CLKFX => open, -- DCM CLK synthesis out (M/D)`
166			`CLKFX180 => open, -- 180 degree CLK synthesis out`
167			`LOCKED => dcm1_locked, -- DCM LOCK status output (means feedback is in phase with main clock)`
168			`PSDONE => open, -- Dynamic phase adjust done output`
169			`STATUS => open, -- 8-bit DCM status bits output`
170			`CLKFB => dcm1_clk_000, -- DCM clock feedback`
171	8	lynn0p	`CLKIN => clk100mhz, -- Clock input (from IBUFG, BUFG or DCM)`
172	2	lynn0p	`PSCLK => '0', -- Dynamic phase adjust clock input`
173			`PSEN => '0', -- Dynamic phase adjust enable input`
174			`PSINCDEC => '0', -- Dynamic phase adjust increment/decrement`
175			`RST => dcm1_reset -- DCM asynchronous reset input`
176			`);`
177			`dcm1_reset <= reset;`
178
179			`BUFG_DCM1_000 : BUFG`
180			`port map (`
181			`O => dcm1_clk_000, -- Clock buffer output`
182			`I => dcm1_clk_raw_000 -- Clock buffer input`
183			`);`
184
185			`BUFG_DCM1_090 : BUFG`
186			`port map (`
187			`O => dcm1_clk_090, -- Clock buffer output`
188			`I => dcm1_clk_raw_090 -- Clock buffer input`
189			`);`
190
191			`dcm1_clk_180 <= not(dcm1_clk_000);`
192			`dcm1_clk_270 <= not(dcm1_clk_090);`
193
194			`ODDR2_DRAM_CLKP : ODDR2`
195			`generic map(`
196			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
197			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
198			`SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
199			`port map (`
200			`Q => dram_clkp, -- 1-bit output data`
201			`C0 => dcm1_clk_000, -- 1-bit clock input`
202			`C1 => dcm1_clk_180, -- 1-bit clock input`
203			`CE => '1', -- 1-bit clock enable input`
204			`D0 => '1', -- 1-bit data input (associated with C0)`
205			`D1 => '0', -- 1-bit data input (associated with C1)`
206			`R => reset, -- 1-bit reset input`
207			`S => '0' -- 1-bit set input`
208			`);`
209
210			`ODDR2_DRAM_CLKN : ODDR2`
211			`generic map(`
212			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
213			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
214			`SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
215			`port map (`
216			`Q => dram_clkn, -- 1-bit output data`
217			`C0 => dcm1_clk_000, -- 1-bit clock input`
218			`C1 => dcm1_clk_180, -- 1-bit clock input`
219			`CE => '1', -- 1-bit clock enable input`
220			`D0 => '0', -- 1-bit data input (associated with C0)`
221			`D1 => '1', -- 1-bit data input (associated with C1)`
222			`R => reset, -- 1-bit reset input`
223			`S => '0' -- 1-bit set input`
224			`);`
225
226	8	lynn0p	`locked <= dcm1_locked;`
227	2	lynn0p
228			`clk_000 <= dcm1_clk_000;`
229			`clk_090 <= dcm1_clk_090;`
230			`clk_180 <= dcm1_clk_180;`
231			`clk_270 <= dcm1_clk_270;`
232
233			`end impl;`
234
235
236			`library IEEE;`
237			`use IEEE.STD_LOGIC_1164.ALL;`
238			`use IEEE.STD_LOGIC_ARITH.ALL;`
239			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
240
241			`---- Uncomment the following library declaration if instantiating`
242			`---- any Xilinx primitives in this code.`
243			`library UNISIM;`
244			`use UNISIM.VComponents.all;`
245
246			`-- just a 2 bit wide ODDR2`
247			`entity oddr2_2 is`
248			`port(`
249			`Q : out std_logic_vector(1 downto 0);`
250			`C0 : in std_logic;`
251			`C1 : in std_logic;`
252			`CE : in std_logic;`
253			`D0 : in std_logic_vector(1 downto 0);`
254			`D1 : in std_logic_vector(1 downto 0);`
255			`R : in std_logic;`
256			`S : in std_logic );`
257			`end oddr2_2;`
258
259			`architecture impl of oddr2_2 is`
260			`begin`
261			`ODDR2_0 : ODDR2`
262			`generic map(`
263			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
264			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
265			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
266			`port map (`
267			`Q => Q(0), -- 1-bit output data`
268			`C0 => C0, -- 1-bit clock input`
269			`C1 => C1, -- 1-bit clock input`
270			`CE => CE, -- 1-bit clock enable input`
271			`D0 => D0(0), -- 1-bit data input (associated with C0)`
272			`D1 => D1(0), -- 1-bit data input (associated with C1)`
273			`R => R, -- 1-bit reset input`
274			`S => S -- 1-bit set input`
275			`);`
276
277			`ODDR2_1 : ODDR2`
278			`generic map(`
279			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
280			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
281			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
282			`port map (`
283			`Q => Q(1), -- 1-bit output data`
284			`C0 => C0, -- 1-bit clock input`
285			`C1 => C1, -- 1-bit clock input`
286			`CE => CE, -- 1-bit clock enable input`
287			`D0 => D0(1), -- 1-bit data input (associated with C0)`
288			`D1 => D1(1), -- 1-bit data input (associated with C1)`
289			`R => R, -- 1-bit reset input`
290			`S => S -- 1-bit set input`
291			`);`
292			`end impl;`
293
294
295
296			`library IEEE;`
297			`use IEEE.STD_LOGIC_1164.ALL;`
298			`use IEEE.STD_LOGIC_ARITH.ALL;`
299			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
300
301			`---- Uncomment the following library declaration if instantiating`
302			`---- any Xilinx primitives in this code.`
303			`library UNISIM;`
304			`use UNISIM.VComponents.all;`
305
306			`-- just a 3 bit wide ODDR2`
307			`entity oddr2_3 is`
308			`port(`
309			`Q : out std_logic_vector(2 downto 0);`
310			`C0 : in std_logic;`
311			`C1 : in std_logic;`
312			`CE : in std_logic;`
313			`D0 : in std_logic_vector(2 downto 0);`
314			`D1 : in std_logic_vector(2 downto 0);`
315			`R : in std_logic;`
316			`S : in std_logic );`
317			`end oddr2_3;`
318
319			`architecture impl of oddr2_3 is`
320			`begin`
321			`ODDR2_0 : ODDR2`
322			`generic map(`
323			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
324			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
325			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
326			`port map (`
327			`Q => Q(0), -- 1-bit output data`
328			`C0 => C0, -- 1-bit clock input`
329			`C1 => C1, -- 1-bit clock input`
330			`CE => CE, -- 1-bit clock enable input`
331			`D0 => D0(0), -- 1-bit data input (associated with C0)`
332			`D1 => D1(0), -- 1-bit data input (associated with C1)`
333			`R => R, -- 1-bit reset input`
334			`S => S -- 1-bit set input`
335			`);`
336
337			`ODDR2_1 : ODDR2`
338			`generic map(`
339			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
340			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
341			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
342			`port map (`
343			`Q => Q(1), -- 1-bit output data`
344			`C0 => C0, -- 1-bit clock input`
345			`C1 => C1, -- 1-bit clock input`
346			`CE => CE, -- 1-bit clock enable input`
347			`D0 => D0(1), -- 1-bit data input (associated with C0)`
348			`D1 => D1(1), -- 1-bit data input (associated with C1)`
349			`R => R, -- 1-bit reset input`
350			`S => S -- 1-bit set input`
351			`);`
352
353			`ODDR2_2 : ODDR2`
354			`generic map(`
355			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
356			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
357			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
358			`port map (`
359			`Q => Q(2), -- 1-bit output data`
360			`C0 => C0, -- 1-bit clock input`
361			`C1 => C1, -- 1-bit clock input`
362			`CE => CE, -- 1-bit clock enable input`
363			`D0 => D0(2), -- 1-bit data input (associated with C0)`
364			`D1 => D1(2), -- 1-bit data input (associated with C1)`
365			`R => R, -- 1-bit reset input`
366			`S => S -- 1-bit set input`
367			`);`
368			`end impl;`
369
370
371
372			`library IEEE;`
373			`use IEEE.STD_LOGIC_1164.ALL;`
374			`use IEEE.STD_LOGIC_ARITH.ALL;`
375			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
376
377			`---- Uncomment the following library declaration if instantiating`
378			`---- any Xilinx primitives in this code.`
379			`library UNISIM;`
380			`use UNISIM.VComponents.all;`
381
382			`-- 2 oddr2_2's`
383			`entity oddr2_4 is`
384			`port( Q : out std_logic_vector(3 downto 0);`
385			`C0 : in std_logic;`
386			`C1 : in std_logic;`
387			`CE : in std_logic;`
388			`D0 : in std_logic_vector(3 downto 0);`
389			`D1 : in std_logic_vector(3 downto 0);`
390			`R : in std_logic;`
391			`S : in std_logic );`
392			`end oddr2_4;`
393
394			`architecture impl of oddr2_4 is`
395
396			`component oddr2_2 is`
397			`port(`
398			`Q : out std_logic_vector(1 downto 0);`
399			`C0 : in std_logic;`
400			`C1 : in std_logic;`
401			`CE : in std_logic;`
402			`D0 : in std_logic_vector(1 downto 0);`
403			`D1 : in std_logic_vector(1 downto 0);`
404			`R : in std_logic;`
405			`S : in std_logic );`
406			`end component;`
407
408			`begin`
409			`ODDR2_0 : oddr2_2`
410			`port map (`
411			`Q => Q(1 downto 0), -- 1-bit output data`
412			`C0 => C0, -- 1-bit clock input`
413			`C1 => C1, -- 1-bit clock input`
414			`CE => CE, -- 1-bit clock enable input`
415			`D0 => D0(1 downto 0), -- 1-bit data input (associated with C0)`
416			`D1 => D1(1 downto 0), -- 1-bit data input (associated with C1)`
417			`R => R, -- 1-bit reset input`
418			`S => S -- 1-bit set input`
419			`);`
420
421			`ODDR2_1 : oddr2_2`
422			`port map (`
423			`Q => Q(3 downto 2), -- 1-bit output data`
424			`C0 => C0, -- 1-bit clock input`
425			`C1 => C1, -- 1-bit clock input`
426			`CE => CE, -- 1-bit clock enable input`
427			`D0 => D0(3 downto 2), -- 1-bit data input (associated with C0)`
428			`D1 => D1(3 downto 2), -- 1-bit data input (associated with C1)`
429			`R => R, -- 1-bit reset input`
430			`S => S -- 1-bit set input`
431			`);`
432			`end impl;`
433
434
435			`library IEEE;`
436			`use IEEE.STD_LOGIC_1164.ALL;`
437			`use IEEE.STD_LOGIC_ARITH.ALL;`
438			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
439
440			`---- Uncomment the following library declaration if instantiating`
441			`---- any Xilinx primitives in this code.`
442			`library UNISIM;`
443			`use UNISIM.VComponents.all;`
444
445			`-- one ODDR2 and 3 4-bit oddr2_4's`
446			`entity oddr2_13 is`
447			`port( Q : out std_logic_vector(12 downto 0);`
448			`C0 : in std_logic;`
449			`C1 : in std_logic;`
450			`CE : in std_logic;`
451			`D0 : in std_logic_vector(12 downto 0);`
452			`D1 : in std_logic_vector(12 downto 0);`
453			`R : in std_logic;`
454			`S : in std_logic );`
455			`end oddr2_13;`
456
457			`architecture impl of oddr2_13 is`
458
459			`component oddr2_4 is`
460			`port(`
461			`Q : out std_logic_vector(3 downto 0);`
462			`C0 : in std_logic;`
463			`C1 : in std_logic;`
464			`CE : in std_logic;`
465			`D0 : in std_logic_vector(3 downto 0);`
466			`D1 : in std_logic_vector(3 downto 0);`
467			`R : in std_logic;`
468			`S : in std_logic );`
469			`end component;`
470
471			`begin`
472
473			`ODDR2_0 : ODDR2`
474			`generic map(`
475			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
476			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
477			`SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset`
478			`port map (`
479			`Q => Q(0), -- 1-bit output data`
480			`C0 => C0, -- 1-bit clock input`
481			`C1 => C1, -- 1-bit clock input`
482			`CE => CE, -- 1-bit clock enable input`
483			`D0 => D0(0), -- 1-bit data input (associated with C0)`
484			`D1 => D1(0), -- 1-bit data input (associated with C1)`
485			`R => R, -- 1-bit reset input`
486			`S => S -- 1-bit set input`
487			`);`
488
489			`ODDR2_1 : oddr2_4`
490			`port map(`
491			`Q => Q(4 downto 1),`
492			`C0 => C0,`
493			`C1 => C1,`
494			`CE => CE,`
495			`D0 => D0(4 downto 1),`
496			`D1 => D1(4 downto 1),`
497			`R => R,`
498			`S => S`
499			`);`
500
501			`ODDR2_2 : oddr2_4`
502			`port map(`
503			`Q => Q(8 downto 5),`
504			`C0 => C0,`
505			`C1 => C1,`
506			`CE => CE,`
507			`D0 => D0(8 downto 5),`
508			`D1 => D1(8 downto 5),`
509			`R => R,`
510			`S => S`
511			`);`
512
513			`ODDR2_3 : oddr2_4`
514			`port map(`
515			`Q => Q(12 downto 9),`
516			`C0 => C0,`
517			`C1 => C1,`
518			`CE => CE,`
519			`D0 => D0(12 downto 9),`
520			`D1 => D1(12 downto 9),`
521			`R => R,`
522			`S => S`
523			`);`
524			`end impl;`
525
526
527
528			`library IEEE;`
529			`use IEEE.STD_LOGIC_1164.ALL;`
530			`use IEEE.STD_LOGIC_ARITH.ALL;`
531			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
532
533			`---- Uncomment the following library declaration if instantiating`
534			`---- any Xilinx primitives in this code.`
535			`library UNISIM;`
536			`use UNISIM.VComponents.all;`
537
538			`-- 4 4-bit oddr2_4's`
539			`entity oddr2_16 is`
540			`port( Q : out std_logic_vector(15 downto 0);`
541			`C0 : in std_logic;`
542			`C1 : in std_logic;`
543			`CE : in std_logic;`
544			`D0 : in std_logic_vector(15 downto 0);`
545			`D1 : in std_logic_vector(15 downto 0);`
546			`R : in std_logic;`
547			`S : in std_logic );`
548			`end oddr2_16;`
549
550			`architecture impl of oddr2_16 is`
551
552			`component oddr2_4 is`
553			`port(`
554			`Q : out std_logic_vector(3 downto 0);`
555			`C0 : in std_logic;`
556			`C1 : in std_logic;`
557			`CE : in std_logic;`
558			`D0 : in std_logic_vector(3 downto 0);`
559			`D1 : in std_logic_vector(3 downto 0);`
560			`R : in std_logic;`
561			`S : in std_logic );`
562			`end component;`
563
564			`begin`
565			`ODDR2_0 : oddr2_4`
566			`port map (`
567			`Q => Q(3 downto 0),`
568			`C0 => C0,`
569			`C1 => C1,`
570			`CE => CE,`
571			`D0 => D0(3 downto 0),`
572			`D1 => D1(3 downto 0),`
573			`R => R,`
574			`S => S`
575			`);`
576
577			`ODDR2_1 : oddr2_4`
578			`port map (`
579			`Q => Q(7 downto 4),`
580			`C0 => C0,`
581			`C1 => C1,`
582			`CE => CE,`
583			`D0 => D0(7 downto 4),`
584			`D1 => D1(7 downto 4),`
585			`R => R,`
586			`S => S`
587			`);`
588
589			`ODDR2_2 : oddr2_4`
590			`port map (`
591			`Q => Q(11 downto 8),`
592			`C0 => C0,`
593			`C1 => C1,`
594			`CE => CE,`
595			`D0 => D0(11 downto 8),`
596			`D1 => D1(11 downto 8),`
597			`R => R,`
598			`S => S`
599			`);`
600
601			`ODDR2_3 : oddr2_4`
602			`port map (`
603			`Q => Q(15 downto 12),`
604			`C0 => C0,`
605			`C1 => C1,`
606			`CE => CE,`
607			`D0 => D0(15 downto 12),`
608			`D1 => D1(15 downto 12),`
609			`R => R,`
610			`S => S`
611			`);`
612			`end;`
613
614
615			`library IEEE;`
616			`use IEEE.STD_LOGIC_1164.ALL;`
617			`use IEEE.STD_LOGIC_ARITH.ALL;`
618			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
619
620			`---- Uncomment the following library declaration if instantiating`
621			`---- any Xilinx primitives in this code.`
622			`library UNISIM;`
623			`use UNISIM.VComponents.all;`
624
625			`entity inout_switch_2 is`
626			`port (`
627			`ioport : inout std_logic_vector(1 downto 0);`
628			`dir : in std_logic;`
629			`data_i : in std_logic_vector(1 downto 0)`
630			`);`
631			`end inout_switch_2;`
632
633			`architecture impl of inout_switch_2 is`
634			`begin`
635			`ioport <= data_i when dir = '1' else "ZZ";`
636			`end impl;`
637
638
639			`library IEEE;`
640			`use IEEE.STD_LOGIC_1164.ALL;`
641			`use IEEE.STD_LOGIC_ARITH.ALL;`
642			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
643
644			`---- Uncomment the following library declaration if instantiating`
645			`---- any Xilinx primitives in this code.`
646			`library UNISIM;`
647			`use UNISIM.VComponents.all;`
648
649			`entity inout_switch_16 is`
650			`port (`
651			`ioport : inout std_logic_vector(15 downto 0);`
652			`dir : in std_logic;`
653			`data_o : out std_logic_vector(15 downto 0);`
654			`data_i : in std_logic_vector(15 downto 0)`
655			`);`
656			`end inout_switch_16;`
657
658			`architecture impl of inout_switch_16 is`
659			`begin`
660			`data_o <= ioport when dir = '0' else "ZZZZZZZZZZZZZZZZ";`
661			`ioport <= data_i when dir = '1' else "ZZZZZZZZZZZZZZZZ";`
662			`end impl;`
663
664