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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [GMII_SGMII.v] - Blame information for rev 26

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1 26 jefflieu
 
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/*
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* This core is to adapt from GMII to SGMII interface.
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* This core requires hardIP to perform serdes
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*/
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module GMII_SGMII (
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//GMII interface
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input [7:0] TxD,
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input TxDV,
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input TxER,
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input TxClk,
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output [7:0] RxD,
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output RxDV,
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output RxER,
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output RxClk,
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//SGMII Interface
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output SGMII_Tx,
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input  SGMII_Rx,
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//Supplementary
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input clk_125M,
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input [2:0] Speed,
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input rstn,
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output core_clk,        //This clock will change according to speed, will be either 125,25,2.5
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output core_clkh        //This clock will change according to speed, will be either 125,12.5,1.25
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);
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endmodule

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