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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [GbMAC.v.bak] - Blame information for rev 26

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    18:49:28 06/15/2010
// Design Name:
// Module Name:    GbMAC_verify
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GbMAC(
        input clk_125M,
        input clk_25M,          //10Mbps not supported
        input clk_125M_90,
        input clk_25M_90,
        input MAC_Sysclk,       //FIFO interface of MAC block
        input MAC_Regclk,       //Register interface of MAC block
 
        input cal_blk_clk,      //calibration clock
        input rstn,                     //hardware reset
        input MACrst,           //Software reset of mac
 
 
        //MDIO interface
        inout  mdio,
        output mdc,
 
 
        //GMII interface
 
        output [7:0]    GMII_TXD,
        output                  GMII_TX_EN,
        output                  GMII_TX_ER,
        output                  GMII_TXClk,
        input [7:0]     GMII_RXD,
        input                   GMII_RX_EN,
        input                   GMII_RX_ER,
        input                   GMII_RXClk,
 
        //SGMII interface
 
        output  SGMII_Tx,
        input   SGMII_Rx,
 
        //RGMII interface
        //RX
        input                   RGMII_Rx_DV,
        input [3:0]     RGMII_Rx_D,
        input                   RGMII_Rx_CLK,
        //TX
        output                  RGMII_Tx_CLK,
        output                  RGMII_Tx_EN,
        output [3:0]    RGMII_Tx_D,
 
        //Host interface
        input [7:0]     address         ,
        input                   read            ,
        input                   write           ,
        input [15:0]    writedata       ,
        output [15:0]   readdata        ,
        output                  waitreq         ,
 
        //status
        output led_an                           ,
        output led_link                         ,
        output [2:0] Speed                      ,
        output reg [3:0] link_stat      ,
 
        output                  pktlen_fifo_ra          ,
        output [15:0]   pktlen_fifo_data        ,
        input                   pktlen_fifo_rd          ,
 
        //PACKET Inteface
        output          Rx_mac_ra               ,
        input           Rx_mac_rd               ,
        output  [31:0]  Rx_mac_data             ,
        output  [1:0]   Rx_mac_BE               ,
        output          Rx_mac_pa               ,
        output          Rx_mac_sop              ,
        output          Rx_mac_eop              ,
        //user interface
        output          Tx_mac_wa               ,
        input           Tx_mac_wr               ,
        input   [31:0]  Tx_mac_data             ,
        input   [1:0]   Tx_mac_BE               ,//big endian
        input           Tx_mac_sop              ,
        input           Tx_mac_eop
);
 
        //clocks
        wire CLK_125M_90;
        wire CLK_125M;
        wire CLK_25M;
        wire CLK_25M_90;
 
        //MAC Module signals
        wire [2:0] gEMAC_Speed;
 
        //user interface RX
        wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop;
        reg Tx_wr;
        wire Rx_rd;
        wire [31:0] Rx_data, Tx_data;
        wire [1:0] Rx_BE, Tx_BE;
        wire pkt_length_fifo_rd, pkt_length_fifo_ra;
        wire [15:0] pkt_length_fifo_data;
 
 
        //host interface
        wire RxClk_MAC;//For MAC Receiver block
        wire TxClk_MAC;//For MAC Transmitter block
        wire MAC_RegSelect;
        wire MAC_RdnWr;
        wire [15:0] MAC_RegDin;
        wire [15:0] MAC_RegDout;
        wire [7:0] MAC_RegAddr;
        wire MAC_RegWait;
        wire MAC_rsti;
 
        wire sysrst;
        reg pwr_on_rst;
 
 
        wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout;
        wire LoopbackFIFO_empty;
        wire LoopbackFIFO_full;
        wire LoopbackFIFO_wren;
        reg LoopbackFIFO_rden;
        wire sysclk,regclk;
 
        reg [3:0] pwr_on_cnt;
        reg Sync_Rst, CE;
 
        assign CLK_125M         = clk_125M;
        assign CLK_125M_90      = clk_125M_90;
        assign CLK_25M          = clk_25M;
        assign CLK_25M_90       = clk_25M_90;
        assign sysclk           = MAC_Sysclk;
        assign regclk           = MAC_Regclk;
 
 
 
        //Phy interface
        wire MAC_Tx_Clk_d;
        wire MAC_Tx_Clk;
        wire MAC_Rx_Clk;
 
        wire [31:0] MAC_Monitoring;
        wire            MAC_GMII_TxER;
        wire            MAC_GMII_TxEN;
        wire [7:0]      MAC_GMII_TxD;
        wire            MAC_GMII_RxDV;
        wire            MAC_GMII_RxER;
        wire            GMII_RxDV;
        wire [7:0]      MAC_GMII_RxD;
        wire MAC_Carrier_Sense;
        wire MAC_Colision_Detect;
 
 
        /* Altera GBX signals */
        wire [7:0] gmii_rx_d;
        wire gmii_rx_dv;
        wire gmii_rx_err;
        wire [7:0] gmii_tx_d;
        wire gmii_tx_en;
        wire gmii_tx_err;
        wire GXB_tx_clk;
        wire GXB_rx_clk;
        wire [3:0] mii_rx_d;
        wire [3:0] mii_tx_d;
        wire mii_rx_dv;
        wire mii_tx_en;
        wire mii_rx_err;
        wire mii_tx_err;
        wire set_100;
        wire hd_ena;
        wire GXB_reset;
        wire [4:0] GXB_reg_addr;
        wire [15:0] GXB_readdata;
        wire [15:0] GXB_writedata;
        wire GXB_read;
        wire GXB_write;
        wire GXB_wait;
        wire GXB_regclk;
        wire GXB_refclk;
        wire GXB_reconfig_clk;
        wire [3:0] GXB_reconfig_togxb;
        wire GXB_led_an;
        wire GXB_tx_clkena;
        wire GXB_rx_clkena;
        wire GXB_led_link;
        wire GXB_cs;
 
        wire mdi;
        wire mdo;
        wire mdoe;
 
        /*
        wire Rx_mac_ra,Rx_mac_rd,Rx_mac_pa,  Rx_mac_sop,Rx_mac_eop;
        wire [31:0]  Rx_mac_data  ;
        wire [1:0]   Rx_mac_BE    ;
        wire Tx_mac_wa, Tx_mac_wr,Tx_mac_sop,Tx_mac_eop;
        wire [31:0]  Tx_mac_data;
        wire [1:0]   Tx_mac_BE ;*/
 
        initial
        begin
        pwr_on_rst <= 1;
        pwr_on_cnt <= 0;
        end
 
        //power on reset circuit
        always@(posedge CLK_125M)
        begin
                if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1;
                if (pwr_on_cnt<15 && pwr_on_cnt>9)
                                        pwr_on_rst <= 1;
                                        else
                                        pwr_on_rst <= 0;
        end
 
        always@(posedge(CLK_125M))
        begin
          if(!rstn)
                begin
                        Sync_Rst <= 1;
                        CE <= 0;
                end
                else
                begin
                        Sync_Rst <= 0;
                        CE <= 1;
                end
        end
        assign sysrst = (~rstn)|pwr_on_rst;
        assign MAC_rsti = MACrst | pwr_on_rst | (~rstn);
        assign MAC_Carrier_Sense = 0;
        assign MAC_Colision_Detect = 0;
 
                //MAC Module
                MAC_top  gMAC(                //system signals
                .Reset                  (MAC_rsti),
                .Clk_125M               (CLK_125M),
                .Clk_125M_90    (CLK_125M_90),
                .Clk_25M_90             (CLK_25M_90),
                .Clk_25M                (CLK_25M),
                .Clk_user               (sysclk),
                .Clk_reg                (regclk),
                .Tx_clk                 (clk_25M),      //used only in MII mode
 
 
                .Speed                  (Speed),
 
                //user interface RX
                .Rx_mac_ra              (Rx_ra),
                .Rx_mac_rd              (Rx_rd),
                .Rx_mac_data    (Rx_data),
                .Rx_mac_BE              (Rx_BE),
                .Rx_mac_pa              (Rx_pa),
                .Rx_mac_sop             (Rx_sop),
                .Rx_mac_eop             (Rx_eop),
                //user interface
                .Tx_mac_wa              (Tx_wa),
                .Tx_mac_wr              (Tx_wr),
                .Tx_mac_data    (Tx_data),
                .Tx_mac_BE              (Tx_BE),//big endian
                .Tx_mac_sop             (Tx_sop),
                .Tx_mac_eop             (Tx_eop),
                //pkg_lgth fifo
                .Pkg_lgth_fifo_rd       (pktlen_fifo_rd),
                .Pkg_lgth_fifo_ra       (pktlen_fifo_ra),
                .Pkg_lgth_fifo_data     (pktlen_fifo_data),
                //Phy interface
                //Phy interface
                .Rx_clk                 (MAC_Rx_Clk),
                .Gtx_clk                (MAC_Tx_Clk),                   //used only in GMII mode
                .Gtx_clk_d              (MAC_Tx_Clk_d),
                .Tx_er                  (MAC_GMII_TxER),
                .Tx_en                  (MAC_GMII_TxEN),
                .Txd                    (MAC_GMII_TxD),
                .Rx_er                  (MAC_GMII_RxER),
                .Rx_dv                  (MAC_GMII_RxDV),
                .Rxd                    (MAC_GMII_RxD),
                .Crs                    (MAC_Carrier_Sense),
                .Col                    (MAC_Colision_Detect),
                //host interface
                .CSB                    (MAC_RegSelect),
                .WRB                    (MAC_RdnWr),
                .CD_in                  (MAC_RegDin),
                .CD_out                 (MAC_RegDout),
                .CA                             (MAC_RegAddr),
                .Monitoring             (MAC_Monitoring),
                //mdx
                .Mdo(mdo),                 // MII Management Data Output
                .MdoEn(mdoe),              // MII Management Data Output Enable
                .Mdi(mdi),
                .Mdc(mdc)                  // MII Management Data Clock
                );
 
        assign mdio = mdoe?(mdo):1'bz;
        assign mdi = mdio;
 
        //RGMII adapter
        RGMII2GMII R2G(
    .RGMII_RxD(RGMII_Rx_D),
    .RGMII_RxCtl(RGMII_Rx_DV),
    .RGMII_RxClk(RGMII_Rx_CLK),
    .RxD(MAC_GMII_RxD),
    .RxDV(MAC_GMII_RxDV),
    .RxER(MAC_GMII_RxER),
    .RxClk(MAC_Rx_Clk),
        .ClkEN(1'b1),
        .rst(sysrst)
    );
 
        GMII2RGMII G2R(
    .TxD(MAC_GMII_TxD),
    .TxClk(MAC_Tx_Clk),
    .TxClk90(MAC_Tx_Clk_d),
    .TxEn(MAC_GMII_TxEN),
    .TxErr(MAC_GMII_TxER),
    .RGMII_TxD(RGMII_Tx_D),
    .RGMII_TxCtl(RGMII_Tx_EN),
    .RGMII_TxClk(RGMII_Tx_CLK),
 
        .ClkEN(1'b1),
        .rst(sysrst)
    );
 
        always@(posedge MAC_Rx_Clk)
        begin
                if((~MAC_GMII_RxDV) & (~MAC_GMII_RxER)) link_stat <= MAC_GMII_RxD[3:0];
        end
 
        //GMII to SGMII
        /*
        sgmii_if sgmii (
         .gmii_rx_d(gmii_rx_d),
         .gmii_rx_dv(gmii_rx_dv),
         .gmii_rx_err(gmii_rx_err),
         .gmii_tx_d(gmii_tx_d),
         .gmii_tx_en(gmii_tx_en),
         .gmii_tx_err(gmii_tx_err),
 
         .tx_clk(GXB_tx_clk),
         .rx_clk(GXB_rx_clk),
 
         .mii_rx_d(mii_rx_d),
         .mii_rx_dv(mii_rx_dv),
         .mii_rx_err(mii_rx_err),
         .mii_tx_d(mii_tx_d),
         .mii_tx_en(mii_tx_en),
         .mii_tx_err(mii_tx_err),
         .mii_col(),
         .mii_crs(),
 
         .set_10(),
         .set_100(set_100),
         .set_1000(),
         .hd_ena(hd_ena),
 
         .reset_tx_clk(GXB_reset),
         .reset_rx_clk(GXB_reset),
 
         .address(GXB_reg_addr),
         .readdata(GXB_readdata),
         .read(GXB_read),
         .writedata(GXB_writedata),
         .write(GXB_write),
         .waitrequest(GXB_wait),
         .clk(GXB_regclk),
         .reset(GXB_reset),
 
         .txp(SGMII_Tx),
         .rxp(SGMII_Rx),
         .ref_clk(GXB_refclk),
         .reconfig_clk(GXB_reconfig_clk),
         .reconfig_togxb(GXB_reconfig_togxb),
         .reconfig_fromgxb(),
         .led_col(),
         .led_crs(),
         .led_an(GXB_led_an),
         .tx_clkena(GXB_tx_clkena),
         .rx_clkena(GXB_rx_clkena),
         .led_link(GXB_led_link),
         .led_disp_err(),
         .gxb_cal_blk_clk(GXB_refclk),
         .led_char_err()
        );
 
        //MII is open
        assign GXB_reset = MAC_rsti;
        assign GXB_regclk = regclk;
        assign GXB_reg_addr = address[4:0];
        assign GXB_writedata = writedata;
        assign GXB_read = read & GXB_cs;
        assign GXB_write = write & GXB_cs;
        assign GXB_cs = (address[7]==1'b1)?1'b1:1'b0;
 
        assign led_an = GXB_led_an;
        assign led_link = GXB_led_link;
 
        //Others signal
        assign GXB_reconfig_clk = 1'b0;
        assign reconfig_togxb = 4'b0010;
        assign GXB_refclk = clk_125M;
 
        //Connect MAC and GXB
        //GMII Interafce
        assign MAC_GMII_RxD = gmii_rx_d;
        assign MAC_GMII_RxDV = gmii_rx_dv;
        assign MAC_GMII_RxER = gmii_rx_err;
        assign gmii_tx_d = MAC_GMII_TxD;
        assign gmii_tx_en= MAC_GMII_TxEN;
        assign gmii_tx_err = MAC_GMII_TxER;
 
        assign MAC_Tx_Clk = GXB_tx_clk;
        assign MAC_Rx_Clk = GXB_rx_clk;
 
        */
 
        assign MAC_RegSelect = (address[7]==1'b1)?1'b1:1'b0;
        assign MAC_RdnWr = ~(write & (~read)& (~MAC_RegSelect));
        assign MAC_RegAddr[7:1] = address[6:0];
        assign MAC_RegDin = writedata;
        //Multiplex data out
        assign readdata = ((~MAC_RegSelect) & (~GXB_cs))?MAC_RegDout:GXB_readdata;
        //wait signal
        assign waitreq = (GXB_wait & GXB_cs) | (MAC_RegWait & (~MAC_RegSelect));
 
        reg MAC_RegSelect_rd ;
        assign MAC_RegWait = (~MAC_RegSelect_rd) & (~MAC_RegSelect & read);
        always@(posedge regclk)
        begin
                MAC_RegSelect_rd <= (~MAC_RegSelect & read) ;
        end
 
        assign Tx_mac_wa = Tx_wa;
        assign Tx_wr = Tx_mac_wr;
        assign Tx_sop = Tx_mac_sop;
        assign Tx_eop = Tx_mac_eop;
        assign Tx_BE = Tx_mac_BE;
        assign Tx_data = Tx_mac_data;
        //MAC BLOCK
//      assign Tx_data  = LoopbackFIFO_dout[31:0];
//      assign Tx_BE    = LoopbackFIFO_dout[35:34];
//      assign Tx_sop   = LoopbackFIFO_dout[32];
//      assign Tx_eop   = LoopbackFIFO_dout[33];
//      assign LoopbackFIFO_din = {Rx_BE,Rx_eop,Rx_sop, Rx_data};
 
//      always@(posedge sysclk)
//      begin
//
//              Rx_rd <= Rx_ra & (~LoopbackFIFO_full);
//              LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty);
//              Tx_wr <= LoopbackFIFO_rden;
//
//      end
//      assign LoopbackFIFO_wren = Rx_pa;
 
//      //Loopback FIFO block
//      lpbff   lpbff_inst (
//      .data ( LoopbackFIFO_din ),
//      .rdreq ( LoopbackFIFO_rden ),
//      .clock (sysclk),
//      .wrreq ( LoopbackFIFO_wren ),
//      .q ( LoopbackFIFO_dout ),
//      .almost_empty (LoopbackFIFO_empty ),
//      .almost_full (LoopbackFIFO_full )
//      );
 
        assign Rx_mac_ra = Rx_ra;
        assign Rx_mac_pa = Rx_pa;
        assign Rx_mac_BE = Rx_BE;
        assign Rx_mac_sop = Rx_sop;
        assign Rx_mac_eop = Rx_eop;
        assign Rx_rd = Rx_mac_rd;
        assign Rx_mac_data = Rx_data;
 
endmodule
 
 

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [GbMAC.v.bak] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 18:49:28 06/15/2010`
7			`// Design Name:`
8			`// Module Name: GbMAC_verify`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module GbMAC(`
22			`input clk_125M,`
23			`input clk_25M, //10Mbps not supported`
24			`input clk_125M_90,`
25			`input clk_25M_90,`
26			`input MAC_Sysclk, //FIFO interface of MAC block`
27			`input MAC_Regclk, //Register interface of MAC block`
28
29			`input cal_blk_clk, //calibration clock`
30			`input rstn, //hardware reset`
31			`input MACrst, //Software reset of mac`
32
33
34			`//MDIO interface`
35			`inout mdio,`
36			`output mdc,`
37
38
39			`//GMII interface`
40
41			`output [7:0] GMII_TXD,`
42			`output GMII_TX_EN,`
43			`output GMII_TX_ER,`
44			`output GMII_TXClk,`
45			`input [7:0] GMII_RXD,`
46			`input GMII_RX_EN,`
47			`input GMII_RX_ER,`
48			`input GMII_RXClk,`
49
50			`//SGMII interface`
51
52			`output SGMII_Tx,`
53			`input SGMII_Rx,`
54
55			`//RGMII interface`
56			`//RX`
57			`input RGMII_Rx_DV,`
58			`input [3:0] RGMII_Rx_D,`
59			`input RGMII_Rx_CLK,`
60			`//TX`
61			`output RGMII_Tx_CLK,`
62			`output RGMII_Tx_EN,`
63			`output [3:0] RGMII_Tx_D,`
64
65			`//Host interface`
66			`input [7:0] address ,`
67			`input read ,`
68			`input write ,`
69			`input [15:0] writedata ,`
70			`output [15:0] readdata ,`
71			`output waitreq ,`
72
73			`//status`
74			`output led_an ,`
75			`output led_link ,`
76			`output [2:0] Speed ,`
77			`output reg [3:0] link_stat ,`
78
79			`output pktlen_fifo_ra ,`
80			`output [15:0] pktlen_fifo_data ,`
81			`input pktlen_fifo_rd ,`
82
83			`//PACKET Inteface`
84			`output Rx_mac_ra ,`
85			`input Rx_mac_rd ,`
86			`output [31:0] Rx_mac_data ,`
87			`output [1:0] Rx_mac_BE ,`
88			`output Rx_mac_pa ,`
89			`output Rx_mac_sop ,`
90			`output Rx_mac_eop ,`
91			`//user interface`
92			`output Tx_mac_wa ,`
93			`input Tx_mac_wr ,`
94			`input [31:0] Tx_mac_data ,`
95			`input [1:0] Tx_mac_BE ,//big endian`
96			`input Tx_mac_sop ,`
97			`input Tx_mac_eop`
98			`);`
99
100			`//clocks`
101			`wire CLK_125M_90;`
102			`wire CLK_125M;`
103			`wire CLK_25M;`
104			`wire CLK_25M_90;`
105
106			`//MAC Module signals`
107			`wire [2:0] gEMAC_Speed;`
108
109			`//user interface RX`
110			`wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop;`
111			`reg Tx_wr;`
112			`wire Rx_rd;`
113			`wire [31:0] Rx_data, Tx_data;`
114			`wire [1:0] Rx_BE, Tx_BE;`
115			`wire pkt_length_fifo_rd, pkt_length_fifo_ra;`
116			`wire [15:0] pkt_length_fifo_data;`
117
118
119			`//host interface`
120			`wire RxClk_MAC;//For MAC Receiver block`
121			`wire TxClk_MAC;//For MAC Transmitter block`
122			`wire MAC_RegSelect;`
123			`wire MAC_RdnWr;`
124			`wire [15:0] MAC_RegDin;`
125			`wire [15:0] MAC_RegDout;`
126			`wire [7:0] MAC_RegAddr;`
127			`wire MAC_RegWait;`
128			`wire MAC_rsti;`
129
130			`wire sysrst;`
131			`reg pwr_on_rst;`
132
133
134			`wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout;`
135			`wire LoopbackFIFO_empty;`
136			`wire LoopbackFIFO_full;`
137			`wire LoopbackFIFO_wren;`
138			`reg LoopbackFIFO_rden;`
139			`wire sysclk,regclk;`
140
141			`reg [3:0] pwr_on_cnt;`
142			`reg Sync_Rst, CE;`
143
144			`assign CLK_125M = clk_125M;`
145			`assign CLK_125M_90 = clk_125M_90;`
146			`assign CLK_25M = clk_25M;`
147			`assign CLK_25M_90 = clk_25M_90;`
148			`assign sysclk = MAC_Sysclk;`
149			`assign regclk = MAC_Regclk;`
150
151
152
153			`//Phy interface`
154			`wire MAC_Tx_Clk_d;`
155			`wire MAC_Tx_Clk;`
156			`wire MAC_Rx_Clk;`
157
158			`wire [31:0] MAC_Monitoring;`
159			`wire MAC_GMII_TxER;`
160			`wire MAC_GMII_TxEN;`
161			`wire [7:0] MAC_GMII_TxD;`
162			`wire MAC_GMII_RxDV;`
163			`wire MAC_GMII_RxER;`
164			`wire GMII_RxDV;`
165			`wire [7:0] MAC_GMII_RxD;`
166			`wire MAC_Carrier_Sense;`
167			`wire MAC_Colision_Detect;`
168
169
170			`/* Altera GBX signals */`
171			`wire [7:0] gmii_rx_d;`
172			`wire gmii_rx_dv;`
173			`wire gmii_rx_err;`
174			`wire [7:0] gmii_tx_d;`
175			`wire gmii_tx_en;`
176			`wire gmii_tx_err;`
177			`wire GXB_tx_clk;`
178			`wire GXB_rx_clk;`
179			`wire [3:0] mii_rx_d;`
180			`wire [3:0] mii_tx_d;`
181			`wire mii_rx_dv;`
182			`wire mii_tx_en;`
183			`wire mii_rx_err;`
184			`wire mii_tx_err;`
185			`wire set_100;`
186			`wire hd_ena;`
187			`wire GXB_reset;`
188			`wire [4:0] GXB_reg_addr;`
189			`wire [15:0] GXB_readdata;`
190			`wire [15:0] GXB_writedata;`
191			`wire GXB_read;`
192			`wire GXB_write;`
193			`wire GXB_wait;`
194			`wire GXB_regclk;`
195			`wire GXB_refclk;`
196			`wire GXB_reconfig_clk;`
197			`wire [3:0] GXB_reconfig_togxb;`
198			`wire GXB_led_an;`
199			`wire GXB_tx_clkena;`
200			`wire GXB_rx_clkena;`
201			`wire GXB_led_link;`
202			`wire GXB_cs;`
203
204			`wire mdi;`
205			`wire mdo;`
206			`wire mdoe;`
207
208			`/*`
209			`wire Rx_mac_ra,Rx_mac_rd,Rx_mac_pa, Rx_mac_sop,Rx_mac_eop;`
210			`wire [31:0] Rx_mac_data ;`
211			`wire [1:0] Rx_mac_BE ;`
212			`wire Tx_mac_wa, Tx_mac_wr,Tx_mac_sop,Tx_mac_eop;`
213			`wire [31:0] Tx_mac_data;`
214			`wire [1:0] Tx_mac_BE ;*/`
215
216			`initial`
217			`begin`
218			`pwr_on_rst <= 1;`
219			`pwr_on_cnt <= 0;`
220			`end`
221
222			`//power on reset circuit`
223			`always@(posedge CLK_125M)`
224			`begin`
225			`if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1;`
226			`if (pwr_on_cnt<15 && pwr_on_cnt>9)`
227			`pwr_on_rst <= 1;`
228			`else`
229			`pwr_on_rst <= 0;`
230			`end`
231
232			`always@(posedge(CLK_125M))`
233			`begin`
234			`if(!rstn)`
235			`begin`
236			`Sync_Rst <= 1;`
237			`CE <= 0;`
238			`end`
239			`else`
240			`begin`
241			`Sync_Rst <= 0;`
242			`CE <= 1;`
243			`end`
244			`end`
245			`assign sysrst = (~rstn)\|pwr_on_rst;`
246			`assign MAC_rsti = MACrst \| pwr_on_rst \| (~rstn);`
247			`assign MAC_Carrier_Sense = 0;`
248			`assign MAC_Colision_Detect = 0;`
249
250			`//MAC Module`
251			`MAC_top gMAC( //system signals`
252			`.Reset (MAC_rsti),`
253			`.Clk_125M (CLK_125M),`
254			`.Clk_125M_90 (CLK_125M_90),`
255			`.Clk_25M_90 (CLK_25M_90),`
256			`.Clk_25M (CLK_25M),`
257			`.Clk_user (sysclk),`
258			`.Clk_reg (regclk),`
259			`.Tx_clk (clk_25M), //used only in MII mode`
260
261
262			`.Speed (Speed),`
263
264			`//user interface RX`
265			`.Rx_mac_ra (Rx_ra),`
266			`.Rx_mac_rd (Rx_rd),`
267			`.Rx_mac_data (Rx_data),`
268			`.Rx_mac_BE (Rx_BE),`
269			`.Rx_mac_pa (Rx_pa),`
270			`.Rx_mac_sop (Rx_sop),`
271			`.Rx_mac_eop (Rx_eop),`
272			`//user interface`
273			`.Tx_mac_wa (Tx_wa),`
274			`.Tx_mac_wr (Tx_wr),`
275			`.Tx_mac_data (Tx_data),`
276			`.Tx_mac_BE (Tx_BE),//big endian`
277			`.Tx_mac_sop (Tx_sop),`
278			`.Tx_mac_eop (Tx_eop),`
279			`//pkg_lgth fifo`
280			`.Pkg_lgth_fifo_rd (pktlen_fifo_rd),`
281			`.Pkg_lgth_fifo_ra (pktlen_fifo_ra),`
282			`.Pkg_lgth_fifo_data (pktlen_fifo_data),`
283			`//Phy interface`
284			`//Phy interface`
285			`.Rx_clk (MAC_Rx_Clk),`
286			`.Gtx_clk (MAC_Tx_Clk), //used only in GMII mode`
287			`.Gtx_clk_d (MAC_Tx_Clk_d),`
288			`.Tx_er (MAC_GMII_TxER),`
289			`.Tx_en (MAC_GMII_TxEN),`
290			`.Txd (MAC_GMII_TxD),`
291			`.Rx_er (MAC_GMII_RxER),`
292			`.Rx_dv (MAC_GMII_RxDV),`
293			`.Rxd (MAC_GMII_RxD),`
294			`.Crs (MAC_Carrier_Sense),`
295			`.Col (MAC_Colision_Detect),`
296			`//host interface`
297			`.CSB (MAC_RegSelect),`
298			`.WRB (MAC_RdnWr),`
299			`.CD_in (MAC_RegDin),`
300			`.CD_out (MAC_RegDout),`
301			`.CA (MAC_RegAddr),`
302			`.Monitoring (MAC_Monitoring),`
303			`//mdx`
304			`.Mdo(mdo), // MII Management Data Output`
305			`.MdoEn(mdoe), // MII Management Data Output Enable`
306			`.Mdi(mdi),`
307			`.Mdc(mdc) // MII Management Data Clock`
308			`);`
309
310			`assign mdio = mdoe?(mdo):1'bz;`
311			`assign mdi = mdio;`
312
313			`//RGMII adapter`
314			`RGMII2GMII R2G(`
315			`.RGMII_RxD(RGMII_Rx_D),`
316			`.RGMII_RxCtl(RGMII_Rx_DV),`
317			`.RGMII_RxClk(RGMII_Rx_CLK),`
318			`.RxD(MAC_GMII_RxD),`
319			`.RxDV(MAC_GMII_RxDV),`
320			`.RxER(MAC_GMII_RxER),`
321			`.RxClk(MAC_Rx_Clk),`
322			`.ClkEN(1'b1),`
323			`.rst(sysrst)`
324			`);`
325
326			`GMII2RGMII G2R(`
327			`.TxD(MAC_GMII_TxD),`
328			`.TxClk(MAC_Tx_Clk),`
329			`.TxClk90(MAC_Tx_Clk_d),`
330			`.TxEn(MAC_GMII_TxEN),`
331			`.TxErr(MAC_GMII_TxER),`
332			`.RGMII_TxD(RGMII_Tx_D),`
333			`.RGMII_TxCtl(RGMII_Tx_EN),`
334			`.RGMII_TxClk(RGMII_Tx_CLK),`
335
336			`.ClkEN(1'b1),`
337			`.rst(sysrst)`
338			`);`
339
340			`always@(posedge MAC_Rx_Clk)`
341			`begin`
342			`if((~MAC_GMII_RxDV) & (~MAC_GMII_RxER)) link_stat <= MAC_GMII_RxD[3:0];`
343			`end`
344
345			`//GMII to SGMII`
346			`/*`
347			`sgmii_if sgmii (`
348			`.gmii_rx_d(gmii_rx_d),`
349			`.gmii_rx_dv(gmii_rx_dv),`
350			`.gmii_rx_err(gmii_rx_err),`
351			`.gmii_tx_d(gmii_tx_d),`
352			`.gmii_tx_en(gmii_tx_en),`
353			`.gmii_tx_err(gmii_tx_err),`
354
355			`.tx_clk(GXB_tx_clk),`
356			`.rx_clk(GXB_rx_clk),`
357
358			`.mii_rx_d(mii_rx_d),`
359			`.mii_rx_dv(mii_rx_dv),`
360			`.mii_rx_err(mii_rx_err),`
361			`.mii_tx_d(mii_tx_d),`
362			`.mii_tx_en(mii_tx_en),`
363			`.mii_tx_err(mii_tx_err),`
364			`.mii_col(),`
365			`.mii_crs(),`
366
367			`.set_10(),`
368			`.set_100(set_100),`
369			`.set_1000(),`
370			`.hd_ena(hd_ena),`
371
372			`.reset_tx_clk(GXB_reset),`
373			`.reset_rx_clk(GXB_reset),`
374
375			`.address(GXB_reg_addr),`
376			`.readdata(GXB_readdata),`
377			`.read(GXB_read),`
378			`.writedata(GXB_writedata),`
379			`.write(GXB_write),`
380			`.waitrequest(GXB_wait),`
381			`.clk(GXB_regclk),`
382			`.reset(GXB_reset),`
383
384			`.txp(SGMII_Tx),`
385			`.rxp(SGMII_Rx),`
386			`.ref_clk(GXB_refclk),`
387			`.reconfig_clk(GXB_reconfig_clk),`
388			`.reconfig_togxb(GXB_reconfig_togxb),`
389			`.reconfig_fromgxb(),`
390			`.led_col(),`
391			`.led_crs(),`
392			`.led_an(GXB_led_an),`
393			`.tx_clkena(GXB_tx_clkena),`
394			`.rx_clkena(GXB_rx_clkena),`
395			`.led_link(GXB_led_link),`
396			`.led_disp_err(),`
397			`.gxb_cal_blk_clk(GXB_refclk),`
398			`.led_char_err()`
399			`);`
400
401			`//MII is open`
402			`assign GXB_reset = MAC_rsti;`
403			`assign GXB_regclk = regclk;`
404			`assign GXB_reg_addr = address[4:0];`
405			`assign GXB_writedata = writedata;`
406			`assign GXB_read = read & GXB_cs;`
407			`assign GXB_write = write & GXB_cs;`
408			`assign GXB_cs = (address[7]==1'b1)?1'b1:1'b0;`
409
410			`assign led_an = GXB_led_an;`
411			`assign led_link = GXB_led_link;`
412
413			`//Others signal`
414			`assign GXB_reconfig_clk = 1'b0;`
415			`assign reconfig_togxb = 4'b0010;`
416			`assign GXB_refclk = clk_125M;`
417
418			`//Connect MAC and GXB`
419			`//GMII Interafce`
420			`assign MAC_GMII_RxD = gmii_rx_d;`
421			`assign MAC_GMII_RxDV = gmii_rx_dv;`
422			`assign MAC_GMII_RxER = gmii_rx_err;`
423			`assign gmii_tx_d = MAC_GMII_TxD;`
424			`assign gmii_tx_en= MAC_GMII_TxEN;`
425			`assign gmii_tx_err = MAC_GMII_TxER;`
426
427			`assign MAC_Tx_Clk = GXB_tx_clk;`
428			`assign MAC_Rx_Clk = GXB_rx_clk;`
429
430			`*/`
431
432			`assign MAC_RegSelect = (address[7]==1'b1)?1'b1:1'b0;`
433			`assign MAC_RdnWr = ~(write & (~read)& (~MAC_RegSelect));`
434			`assign MAC_RegAddr[7:1] = address[6:0];`
435			`assign MAC_RegDin = writedata;`
436			`//Multiplex data out`
437			`assign readdata = ((~MAC_RegSelect) & (~GXB_cs))?MAC_RegDout:GXB_readdata;`
438			`//wait signal`
439			`assign waitreq = (GXB_wait & GXB_cs) \| (MAC_RegWait & (~MAC_RegSelect));`
440
441			`reg MAC_RegSelect_rd ;`
442			`assign MAC_RegWait = (~MAC_RegSelect_rd) & (~MAC_RegSelect & read);`
443			`always@(posedge regclk)`
444			`begin`
445			`MAC_RegSelect_rd <= (~MAC_RegSelect & read) ;`
446			`end`
447
448			`assign Tx_mac_wa = Tx_wa;`
449			`assign Tx_wr = Tx_mac_wr;`
450			`assign Tx_sop = Tx_mac_sop;`
451			`assign Tx_eop = Tx_mac_eop;`
452			`assign Tx_BE = Tx_mac_BE;`
453			`assign Tx_data = Tx_mac_data;`
454			`//MAC BLOCK`
455			`// assign Tx_data = LoopbackFIFO_dout[31:0];`
456			`// assign Tx_BE = LoopbackFIFO_dout[35:34];`
457			`// assign Tx_sop = LoopbackFIFO_dout[32];`
458			`// assign Tx_eop = LoopbackFIFO_dout[33];`
459			`// assign LoopbackFIFO_din = {Rx_BE,Rx_eop,Rx_sop, Rx_data};`
460
461			`// always@(posedge sysclk)`
462			`// begin`
463			`//`
464			`// Rx_rd <= Rx_ra & (~LoopbackFIFO_full);`
465			`// LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty);`
466			`// Tx_wr <= LoopbackFIFO_rden;`
467			`//`
468			`// end`
469			`// assign LoopbackFIFO_wren = Rx_pa;`
470
471			`// //Loopback FIFO block`
472			`// lpbff lpbff_inst (`
473			`// .data ( LoopbackFIFO_din ),`
474			`// .rdreq ( LoopbackFIFO_rden ),`
475			`// .clock (sysclk),`
476			`// .wrreq ( LoopbackFIFO_wren ),`
477			`// .q ( LoopbackFIFO_dout ),`
478			`// .almost_empty (LoopbackFIFO_empty ),`
479			`// .almost_full (LoopbackFIFO_full )`
480			`// );`
481
482			`assign Rx_mac_ra = Rx_ra;`
483			`assign Rx_mac_pa = Rx_pa;`
484			`assign Rx_mac_BE = Rx_BE;`
485			`assign Rx_mac_sop = Rx_sop;`
486			`assign Rx_mac_eop = Rx_eop;`
487			`assign Rx_rd = Rx_mac_rd;`
488			`assign Rx_mac_data = Rx_data;`
489
490			`endmodule`
491
492