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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [GbMAC_verify.v] - Blame information for rev 26

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:49:28 06/15/2010 
// Design Name: 
// Module Name:    GbMAC_verify 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module GbMAC_verify(
         input PhyA_RxClk,
         input PhyA_RxCtl,
         input [3:0] PhyA_RxD,
         output PhyA_TxClk,
         output PhyA_TxCtl,
         output [3:0] PhyA_TxD,
 
 
 
         output PhyB_TxClk,
         output PhyB_TxCtl,
         output [3:0] PhyB_TxD,
 
         input PhyC_RxClk,
         input PhyC_RxCtl,
         input [3:0] PhyC_RxD,
 
         output PhyC_TxClk,
         output PhyC_TxCtl,
         output [3:0] PhyC_TxD,
 
 
         input V4_PCIXClk,
 
         output V4_Uart_Tx,
         input V4_Uart_Rx,
 
         input V4_CLK_125M,
    input V4_CLK_Sys,
    input V4_rst_n
);
 
// OPB BUS
wire [0:0] OPB_CS_n;
wire [11:0] OPB_Addr;
wire OPB_ADS;
wire [1:0] OPB_BE;
wire OPB_RnW;
wire OPB_Rd_n;
wire OPB_Wr_n;
wire OPB_Burst;
reg  OPB_Rdy;
wire [15:0] OPB_Din;
wire [15:0] OPB_Dout;
wire [0:31] OPB_outD;
wire [0:31] OPB_inD;
 
        //MAC Module signals
        wire [2:0] gEMAC_Speed;
        //user interface RX 
        wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop;
        reg Tx_wr;
        reg Rx_rd;
        wire [31:0] Rx_data, Tx_data;
        wire [1:0] Rx_BE, Tx_BE;
        wire pkt_length_fifo_rd, pkt_length_fifo_ra;
        wire [15:0] pkt_length_fifo_data;
        wire Carrier_Sense, Colision_Detect;
 
        //host interface
        wire RxClk_MAC;//For MAC Receiver block
        wire MAC_RegSelect;
        wire MAC_RdnWr;
        wire [15:0] MAC_RegDin;
        wire [15:0] MAC_RegDout;
        wire [7:0] MAC_RegAddr;
 
//RGMII-GMII adaptation module
        wire [7:0] GMII_TxD;
        wire GMII_TxEN, GMII_TxER, GTx_Clk;
        wire [7:0] GMII_RxD;
        wire GMII_RxDV, GMII_RxER, GRx_Clk;
        reg  CE, Sync_Rst;
 
        wire [3:0] RGMII_RxD;
        wire [3:0] RGMII_TxD;
        wire RGMII_RxCtl, RGMII_RxClk;
        wire RGMII_TxCtl, RGMII_TxClk;
 
        wire [3:0] RxPhyA_Stat;
 
        wire CLK_125M90;
        wire CLK_125M;
        wire CLK_25M;
        wire V4_rst;
        wire uB_rst;
        reg pwr_on_rst;
        wire MAC_Sysclk;
        wire MAC_Regclk;
 
        reg one_sec_pulse;
        reg [27:0] one_sec;
        reg [31:0] rx_rate;
        reg [31:0] rx_rate_reg;
 
        wire [0:0] ila_trig0, ila_trig1, ila_trig2;
        wire [63:0] ila_data_bus;
        wire [35:0] ila_control;
        wire [23:0] MAC_Monitoring;
 
        wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout;
        wire LoopbackFIFO_empty;
        wire LoopbackFIFO_full;
        wire LoopbackFIFO_wren;
        reg LoopbackFIFO_rden;
 
        assign PhyA_TxD =  0;//RGMII_TxD;
        assign PhyA_TxClk = 0;//RGMII_TxClk;
        assign PhyA_TxCtl = 0;//RGMII_TxCtl;
        assign PhyB_TxD =  0;//RGMII_TxD;
        assign PhyB_TxClk = 0;//RGMII_TxClk;
        assign PhyB_TxCtl = 0;//RGMII_TxCtl;
 
        assign PhyC_TxD = RGMII_TxD;
        assign PhyC_TxClk = RGMII_TxClk;
        assign PhyC_TxCtl = RGMII_TxCtl;
 
        assign RGMII_RxD  = PhyC_RxD;
        assign RGMII_RxCtl= PhyC_RxCtl;
        assign RGMII_RxClk= PhyC_RxClk;
 
        assign CLK_66M = V4_PCIXClk;
 
                always@(posedge(CLK_125M))
        begin
          if(!V4_rst_n)
                begin
                        Sync_Rst <= 1;
                        CE <= 0;
                end
                else
                begin
                        Sync_Rst <= 0;
                        CE <= 1;
                end
        end
 
        assign V4_rst = (~V4_rst_n)|pwr_on_rst;
        assign uB_rst = ~ V4_rst;
 
Clocks Clockings(.V4_Clk_125M(V4_CLK_125M),.V4_Clk_27M(),.V4_Clk_13M5(),
                                                .Clk_125M(CLK_125M),.Clk_27M(),.Clk_13M5(),.Clk_25M(CLK_25M),
                                                .Clk_125M_90(CLK_125M90),
                                                .rst(0));
 
                reg [3:0] pwr_on_cnt;
                initial
                begin
                pwr_on_rst <= 1;
                pwr_on_cnt <= 0;
                end
                always@(posedge CLK_125M)
                begin
                if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1;
                if (pwr_on_cnt<15 && pwr_on_cnt>9)
                                        pwr_on_rst <= 1;
                                        else
                                        pwr_on_rst <= 0;
                end
 
                assign RxClkPhase = 0;
                RGMII_GMII_Adaptation RGMIIAdp(
                                                                         .Speed(gEMAC_Speed),.RxClkPhase(RxClkPhase),
                                                                         .TxD(GMII_TxD), .TxEN(GMII_TxEN), .TxER(GMII_TxER), .TxClk(GTx_Clk),
                                                                         .RxD(GMII_RxD), .RxDV(GMII_RxDV), .RxER(GMII_RxER), .RxClk(GRx_Clk),
                                                                         .RGMII_TxD(RGMII_TxD),
                                                                         .RGMII_TxCtl(RGMII_TxCtl),
                                                                         .RGMII_TxClk(RGMII_TxClk),
                                                                         .RGMII_RxD(RGMII_RxD),
                                                                         .RGMII_RxCtl(RGMII_RxCtl),
                                                                         .RGMII_RxClk(RGMII_RxClk),
                                                                         .Status(RxPhyA_Stat),
                                                                         .RxClk_MAC(RxClk_MAC),
                                                                         .CE(CE),
                                                                         .rst(V4_rst)
                                                                         );
 
                assign MAC_Sysclk = CLK_125M;
assign MAC_Regclk = CLK_66M;
//MAC Module
MAC_top  gMAC(                //system signals
.Reset(V4_rst),
.Clk_125M(CLK_125M),
.Clk_user(MAC_Sysclk),
.Clk_reg(MAC_Regclk),
.Clk_MACRx(RxClk_MAC),
.Speed(gEMAC_Speed),
//user interface RX 
.Rx_mac_ra(Rx_ra),
.Rx_mac_rd(Rx_rd),
.Rx_mac_data(Rx_data),
.Rx_mac_BE(Rx_BE),
.Rx_mac_pa(Rx_pa),
.Rx_mac_sop(Rx_sop),
.Rx_mac_eop(Rx_eop),
//user interface 
.Tx_mac_wa(Tx_wa),
.Tx_mac_wr(Tx_wr),
.Tx_mac_data(Tx_data),
.Tx_mac_BE(Tx_BE),//big endian
.Tx_mac_sop(Tx_sop),
.Tx_mac_eop(Tx_eop),
//pkg_lgth fifo
.Pkg_lgth_fifo_rd(pkt_length_fifo_rd),
.Pkg_lgth_fifo_ra(pkt_length_fifo_ra),
.Pkg_lgth_fifo_data(pkt_length_fifo_data),
//Phy interface          
//Phy interface         
.Gtx_clk(GTx_Clk),//used only in GMII mode
.Rx_clk(GRx_Clk),
.Tx_clk(CLK_25M),//used only in MII mode
.Tx_er(GMII_TxER),
.Tx_en(GMII_TxEN),
.Txd(GMII_TxD),
.Rx_er(GMII_RxER),
.Rx_dv(GMII_RxDV),
.Rxd(GMII_RxD),
.Crs(Carrier_Sense),
.Col(Colision_Detect),
//host interface
.CSB(MAC_RegSelect),
.WRB(MAC_RdnWr),
.CD_in(MAC_RegDin),
.CD_out(MAC_RegDout),
.CA(MAC_RegAddr),
.Monitoring(MAC_Monitoring),
//mdx
.Mdo(),                // MII Management Data Output
.MdoEn(),              // MII Management Data Output Enable
.Mdi(0),
.Mdc()                      // MII Management Data Clock       
);
 
        LoopbackFIFO lpbff(
        .clk(CLK_125M),
        .din(LoopbackFIFO_din),
        .rd_en(LoopbackFIFO_rden),
        .wr_en(LoopbackFIFO_wren),
        .dout(LoopbackFIFO_dout),
        .empty(),
        .full(),
        .almost_empty(LoopbackFIFO_empty),
        .almost_full(LoopbackFIFO_full));
 
        assign LoopbackFIFO_din = {Rx_BE,Rx_sop,Rx_eop,Rx_data};
        assign LoopbackFIFO_wren= Rx_pa;
 
                //Route packet back to transmitter
                assign Tx_data = LoopbackFIFO_dout[31:0];
                assign Tx_sop = LoopbackFIFO_dout[33];
                assign Tx_eop = LoopbackFIFO_dout[32];
                assign Tx_BE =  LoopbackFIFO_dout[35:34];
 
                assign MAC_RegSelect = OPB_CS_n;
                assign MAC_RegDin = OPB_outD[0:15];
                assign OPB_inD = {MAC_RegDout,16'h0000};
                assign MAC_RegAddr = OPB_Addr[7:0];
                assign MAC_RdnWr = OPB_RnW;
 
                //Initializing machine
                always@(posedge MAC_Regclk or posedge V4_rst)
                begin
                if(V4_rst)
                        begin
                        OPB_Rdy <= 0;
                        end
                else
                        begin
                                OPB_Rdy <= ~OPB_CS_n;
                        end
                end
 
                assign Carrier_Sense = 1;
                assign Colision_Detect = 0;
 
                wire one_sec_pulse_long;
 
                assign one_sec_pulse_long = (one_sec>0 && one_sec<256)?1:0;
 
                always@(posedge MAC_Sysclk or posedge V4_rst)
                if(V4_rst)
                begin
                one_sec <=0;
                one_sec_pulse <= 0;
                Rx_rd <= 0;
                Tx_wr <= 0;
                LoopbackFIFO_rden <= 0;
                end
                else
                begin
                        if(one_sec == 125000000) one_sec <= 1; else one_sec <= one_sec+1;
                        if(one_sec == 125000000) one_sec_pulse <= 1; else one_sec_pulse <= 0;
                        if(one_sec_pulse)
                                begin
                                rx_rate <= 0;
                                rx_rate_reg <= rx_rate;
                                end
                        else
                                begin
                                if(Rx_sop) rx_rate <= rx_rate+1;
                                end
                        //start to read whenever data is available;
                        Rx_rd <= Rx_ra & (~LoopbackFIFO_full);
                        LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty);
                        Tx_wr <= LoopbackFIFO_rden;
                end
 
                        //Microblaze 
        uBlaze microBlaze
  ( .uBlaze_Int(one_sec_pulse_long),
         .fpga_0_RS232_req_to_send_pin(),
    .fpga_0_RS232_RX_pin(V4_Uart_Rx),
    .fpga_0_RS232_TX_pin(V4_Uart_Tx),
    .sys_clk_pin(CLK_66M),
    .sys_rst_pin(uB_rst),
    .PRH_Clk_pin(CLK_66M),
    .PRH_Rst_pin(V4_rst),
    .PRH_CS_n_pin(OPB_CS_n),
    .PRH_Addr_pin(OPB_Addr),
    .PRH_ADS_pin(OPB_ADS),
    .PRH_BE_pin(OPB_BE),
    .PRH_RNW_pin(OPB_RnW),
    .PRH_Rd_n_pin(OPB_Rd_n),
    .PRH_Wr_n_pin(OPB_Wr_n),
    .PRH_Burst_pin(OPB_Burst),
    .PRH_Rdy_pin(OPB_Rdy),
    .PRH_Data_I_pin(OPB_inD),
    .PRH_Data_O_pin(OPB_outD),
    .PRH_Data_T_pin());
 
        //Monitoring
        ila i_ila
    (
      .control(ila_control),
      .clk(CLK_125M),
      .data(ila_data_bus),
      .trig0(ila_trig0),
      .trig1(ila_trig1),
      .trig2(ila_trig2)
    );
 
 
 
        assign ila_data_bus[31:0] =  {0,gEMAC_Speed,MAC_Monitoring};
        assign ila_data_bus[47:32] = {GMII_TxEN,GMII_TxER,GMII_TxD};
        assign ila_data_bus[63:48] = {0,LoopbackFIFO_empty,LoopbackFIFO_full,Tx_wr,Tx_wa,Rx_ra,Rx_pa,Rx_rd};
        assign ila_trig0 = Rx_rd;
        assign ila_trig1 = Tx_wr;
        assign ila_trig2 = LoopbackFIFO_full;
 
        icon i_icon
    (
      .control0(ila_control)
    );
 
endmodule
 
module icon
  (
      control0
  );
  output [35:0] control0;
endmodule
 
module ila
  (
    control,
    clk,
    data,
    trig0,
    trig1,
    trig2
  );
  input [35:0] control;
  input clk;
  input [63:0] data;
  input [0:0] trig0;
  input [0:0] trig1;
  input [0:0] trig2;
endmodule

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [GbMAC_verify.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 18:49:28 06/15/2010`
7			`// Design Name:`
8			`// Module Name: GbMAC_verify`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module GbMAC_verify(`
22			`input PhyA_RxClk,`
23			`input PhyA_RxCtl,`
24			`input [3:0] PhyA_RxD,`
25			`output PhyA_TxClk,`
26			`output PhyA_TxCtl,`
27			`output [3:0] PhyA_TxD,`
28
29
30
31			`output PhyB_TxClk,`
32			`output PhyB_TxCtl,`
33			`output [3:0] PhyB_TxD,`
34
35			`input PhyC_RxClk,`
36			`input PhyC_RxCtl,`
37			`input [3:0] PhyC_RxD,`
38
39			`output PhyC_TxClk,`
40			`output PhyC_TxCtl,`
41			`output [3:0] PhyC_TxD,`
42
43
44			`input V4_PCIXClk,`
45
46			`output V4_Uart_Tx,`
47			`input V4_Uart_Rx,`
48
49			`input V4_CLK_125M,`
50			`input V4_CLK_Sys,`
51			`input V4_rst_n`
52			`);`
53
54			`// OPB BUS`
55			`wire [0:0] OPB_CS_n;`
56			`wire [11:0] OPB_Addr;`
57			`wire OPB_ADS;`
58			`wire [1:0] OPB_BE;`
59			`wire OPB_RnW;`
60			`wire OPB_Rd_n;`
61			`wire OPB_Wr_n;`
62			`wire OPB_Burst;`
63			`reg OPB_Rdy;`
64			`wire [15:0] OPB_Din;`
65			`wire [15:0] OPB_Dout;`
66			`wire [0:31] OPB_outD;`
67			`wire [0:31] OPB_inD;`
68
69			`//MAC Module signals`
70			`wire [2:0] gEMAC_Speed;`
71			`//user interface RX`
72			`wire Rx_ra, Rx_pa,Tx_wa, Tx_pa, Rx_sop, Rx_eop, Tx_sop, Tx_eop;`
73			`reg Tx_wr;`
74			`reg Rx_rd;`
75			`wire [31:0] Rx_data, Tx_data;`
76			`wire [1:0] Rx_BE, Tx_BE;`
77			`wire pkt_length_fifo_rd, pkt_length_fifo_ra;`
78			`wire [15:0] pkt_length_fifo_data;`
79			`wire Carrier_Sense, Colision_Detect;`
80
81			`//host interface`
82			`wire RxClk_MAC;//For MAC Receiver block`
83			`wire MAC_RegSelect;`
84			`wire MAC_RdnWr;`
85			`wire [15:0] MAC_RegDin;`
86			`wire [15:0] MAC_RegDout;`
87			`wire [7:0] MAC_RegAddr;`
88
89			`//RGMII-GMII adaptation module`
90			`wire [7:0] GMII_TxD;`
91			`wire GMII_TxEN, GMII_TxER, GTx_Clk;`
92			`wire [7:0] GMII_RxD;`
93			`wire GMII_RxDV, GMII_RxER, GRx_Clk;`
94			`reg CE, Sync_Rst;`
95
96			`wire [3:0] RGMII_RxD;`
97			`wire [3:0] RGMII_TxD;`
98			`wire RGMII_RxCtl, RGMII_RxClk;`
99			`wire RGMII_TxCtl, RGMII_TxClk;`
100
101			`wire [3:0] RxPhyA_Stat;`
102
103			`wire CLK_125M90;`
104			`wire CLK_125M;`
105			`wire CLK_25M;`
106			`wire V4_rst;`
107			`wire uB_rst;`
108			`reg pwr_on_rst;`
109			`wire MAC_Sysclk;`
110			`wire MAC_Regclk;`
111
112			`reg one_sec_pulse;`
113			`reg [27:0] one_sec;`
114			`reg [31:0] rx_rate;`
115			`reg [31:0] rx_rate_reg;`
116
117			`wire [0:0] ila_trig0, ila_trig1, ila_trig2;`
118			`wire [63:0] ila_data_bus;`
119			`wire [35:0] ila_control;`
120			`wire [23:0] MAC_Monitoring;`
121
122			`wire [35:0] LoopbackFIFO_din,LoopbackFIFO_dout;`
123			`wire LoopbackFIFO_empty;`
124			`wire LoopbackFIFO_full;`
125			`wire LoopbackFIFO_wren;`
126			`reg LoopbackFIFO_rden;`
127
128			`assign PhyA_TxD = 0;//RGMII_TxD;`
129			`assign PhyA_TxClk = 0;//RGMII_TxClk;`
130			`assign PhyA_TxCtl = 0;//RGMII_TxCtl;`
131			`assign PhyB_TxD = 0;//RGMII_TxD;`
132			`assign PhyB_TxClk = 0;//RGMII_TxClk;`
133			`assign PhyB_TxCtl = 0;//RGMII_TxCtl;`
134
135			`assign PhyC_TxD = RGMII_TxD;`
136			`assign PhyC_TxClk = RGMII_TxClk;`
137			`assign PhyC_TxCtl = RGMII_TxCtl;`
138
139			`assign RGMII_RxD = PhyC_RxD;`
140			`assign RGMII_RxCtl= PhyC_RxCtl;`
141			`assign RGMII_RxClk= PhyC_RxClk;`
142
143			`assign CLK_66M = V4_PCIXClk;`
144
145			`always@(posedge(CLK_125M))`
146			`begin`
147			`if(!V4_rst_n)`
148			`begin`
149			`Sync_Rst <= 1;`
150			`CE <= 0;`
151			`end`
152			`else`
153			`begin`
154			`Sync_Rst <= 0;`
155			`CE <= 1;`
156			`end`
157			`end`
158
159			`assign V4_rst = (~V4_rst_n)\|pwr_on_rst;`
160			`assign uB_rst = ~ V4_rst;`
161
162			`Clocks Clockings(.V4_Clk_125M(V4_CLK_125M),.V4_Clk_27M(),.V4_Clk_13M5(),`
163			`.Clk_125M(CLK_125M),.Clk_27M(),.Clk_13M5(),.Clk_25M(CLK_25M),`
164			`.Clk_125M_90(CLK_125M90),`
165			`.rst(0));`
166
167			`reg [3:0] pwr_on_cnt;`
168			`initial`
169			`begin`
170			`pwr_on_rst <= 1;`
171			`pwr_on_cnt <= 0;`
172			`end`
173			`always@(posedge CLK_125M)`
174			`begin`
175			`if (pwr_on_cnt!=15) pwr_on_cnt <= pwr_on_cnt+1;`
176			`if (pwr_on_cnt<15 && pwr_on_cnt>9)`
177			`pwr_on_rst <= 1;`
178			`else`
179			`pwr_on_rst <= 0;`
180			`end`
181
182			`assign RxClkPhase = 0;`
183			`RGMII_GMII_Adaptation RGMIIAdp(`
184			`.Speed(gEMAC_Speed),.RxClkPhase(RxClkPhase),`
185			`.TxD(GMII_TxD), .TxEN(GMII_TxEN), .TxER(GMII_TxER), .TxClk(GTx_Clk),`
186			`.RxD(GMII_RxD), .RxDV(GMII_RxDV), .RxER(GMII_RxER), .RxClk(GRx_Clk),`
187			`.RGMII_TxD(RGMII_TxD),`
188			`.RGMII_TxCtl(RGMII_TxCtl),`
189			`.RGMII_TxClk(RGMII_TxClk),`
190			`.RGMII_RxD(RGMII_RxD),`
191			`.RGMII_RxCtl(RGMII_RxCtl),`
192			`.RGMII_RxClk(RGMII_RxClk),`
193			`.Status(RxPhyA_Stat),`
194			`.RxClk_MAC(RxClk_MAC),`
195			`.CE(CE),`
196			`.rst(V4_rst)`
197			`);`
198
199			`assign MAC_Sysclk = CLK_125M;`
200			`assign MAC_Regclk = CLK_66M;`
201			`//MAC Module`
202			`MAC_top gMAC( //system signals`
203			`.Reset(V4_rst),`
204			`.Clk_125M(CLK_125M),`
205			`.Clk_user(MAC_Sysclk),`
206			`.Clk_reg(MAC_Regclk),`
207			`.Clk_MACRx(RxClk_MAC),`
208			`.Speed(gEMAC_Speed),`
209			`//user interface RX`
210			`.Rx_mac_ra(Rx_ra),`
211			`.Rx_mac_rd(Rx_rd),`
212			`.Rx_mac_data(Rx_data),`
213			`.Rx_mac_BE(Rx_BE),`
214			`.Rx_mac_pa(Rx_pa),`
215			`.Rx_mac_sop(Rx_sop),`
216			`.Rx_mac_eop(Rx_eop),`
217			`//user interface`
218			`.Tx_mac_wa(Tx_wa),`
219			`.Tx_mac_wr(Tx_wr),`
220			`.Tx_mac_data(Tx_data),`
221			`.Tx_mac_BE(Tx_BE),//big endian`
222			`.Tx_mac_sop(Tx_sop),`
223			`.Tx_mac_eop(Tx_eop),`
224			`//pkg_lgth fifo`
225			`.Pkg_lgth_fifo_rd(pkt_length_fifo_rd),`
226			`.Pkg_lgth_fifo_ra(pkt_length_fifo_ra),`
227			`.Pkg_lgth_fifo_data(pkt_length_fifo_data),`
228			`//Phy interface`
229			`//Phy interface`
230			`.Gtx_clk(GTx_Clk),//used only in GMII mode`
231			`.Rx_clk(GRx_Clk),`
232			`.Tx_clk(CLK_25M),//used only in MII mode`
233			`.Tx_er(GMII_TxER),`
234			`.Tx_en(GMII_TxEN),`
235			`.Txd(GMII_TxD),`
236			`.Rx_er(GMII_RxER),`
237			`.Rx_dv(GMII_RxDV),`
238			`.Rxd(GMII_RxD),`
239			`.Crs(Carrier_Sense),`
240			`.Col(Colision_Detect),`
241			`//host interface`
242			`.CSB(MAC_RegSelect),`
243			`.WRB(MAC_RdnWr),`
244			`.CD_in(MAC_RegDin),`
245			`.CD_out(MAC_RegDout),`
246			`.CA(MAC_RegAddr),`
247			`.Monitoring(MAC_Monitoring),`
248			`//mdx`
249			`.Mdo(), // MII Management Data Output`
250			`.MdoEn(), // MII Management Data Output Enable`
251			`.Mdi(0),`
252			`.Mdc() // MII Management Data Clock`
253			`);`
254
255			`LoopbackFIFO lpbff(`
256			`.clk(CLK_125M),`
257			`.din(LoopbackFIFO_din),`
258			`.rd_en(LoopbackFIFO_rden),`
259			`.wr_en(LoopbackFIFO_wren),`
260			`.dout(LoopbackFIFO_dout),`
261			`.empty(),`
262			`.full(),`
263			`.almost_empty(LoopbackFIFO_empty),`
264			`.almost_full(LoopbackFIFO_full));`
265
266			`assign LoopbackFIFO_din = {Rx_BE,Rx_sop,Rx_eop,Rx_data};`
267			`assign LoopbackFIFO_wren= Rx_pa;`
268
269			`//Route packet back to transmitter`
270			`assign Tx_data = LoopbackFIFO_dout[31:0];`
271			`assign Tx_sop = LoopbackFIFO_dout[33];`
272			`assign Tx_eop = LoopbackFIFO_dout[32];`
273			`assign Tx_BE = LoopbackFIFO_dout[35:34];`
274
275			`assign MAC_RegSelect = OPB_CS_n;`
276			`assign MAC_RegDin = OPB_outD[0:15];`
277			`assign OPB_inD = {MAC_RegDout,16'h0000};`
278			`assign MAC_RegAddr = OPB_Addr[7:0];`
279			`assign MAC_RdnWr = OPB_RnW;`
280
281			`//Initializing machine`
282			`always@(posedge MAC_Regclk or posedge V4_rst)`
283			`begin`
284			`if(V4_rst)`
285			`begin`
286			`OPB_Rdy <= 0;`
287			`end`
288			`else`
289			`begin`
290			`OPB_Rdy <= ~OPB_CS_n;`
291			`end`
292			`end`
293
294			`assign Carrier_Sense = 1;`
295			`assign Colision_Detect = 0;`
296
297			`wire one_sec_pulse_long;`
298
299			`assign one_sec_pulse_long = (one_sec>0 && one_sec<256)?1:0;`
300
301			`always@(posedge MAC_Sysclk or posedge V4_rst)`
302			`if(V4_rst)`
303			`begin`
304			`one_sec <=0;`
305			`one_sec_pulse <= 0;`
306			`Rx_rd <= 0;`
307			`Tx_wr <= 0;`
308			`LoopbackFIFO_rden <= 0;`
309			`end`
310			`else`
311			`begin`
312			`if(one_sec == 125000000) one_sec <= 1; else one_sec <= one_sec+1;`
313			`if(one_sec == 125000000) one_sec_pulse <= 1; else one_sec_pulse <= 0;`
314			`if(one_sec_pulse)`
315			`begin`
316			`rx_rate <= 0;`
317			`rx_rate_reg <= rx_rate;`
318			`end`
319			`else`
320			`begin`
321			`if(Rx_sop) rx_rate <= rx_rate+1;`
322			`end`
323			`//start to read whenever data is available;`
324			`Rx_rd <= Rx_ra & (~LoopbackFIFO_full);`
325			`LoopbackFIFO_rden <= Tx_wa & (~LoopbackFIFO_empty);`
326			`Tx_wr <= LoopbackFIFO_rden;`
327			`end`
328
329			`//Microblaze`
330			`uBlaze microBlaze`
331			`( .uBlaze_Int(one_sec_pulse_long),`
332			`.fpga_0_RS232_req_to_send_pin(),`
333			`.fpga_0_RS232_RX_pin(V4_Uart_Rx),`
334			`.fpga_0_RS232_TX_pin(V4_Uart_Tx),`
335			`.sys_clk_pin(CLK_66M),`
336			`.sys_rst_pin(uB_rst),`
337			`.PRH_Clk_pin(CLK_66M),`
338			`.PRH_Rst_pin(V4_rst),`
339			`.PRH_CS_n_pin(OPB_CS_n),`
340			`.PRH_Addr_pin(OPB_Addr),`
341			`.PRH_ADS_pin(OPB_ADS),`
342			`.PRH_BE_pin(OPB_BE),`
343			`.PRH_RNW_pin(OPB_RnW),`
344			`.PRH_Rd_n_pin(OPB_Rd_n),`
345			`.PRH_Wr_n_pin(OPB_Wr_n),`
346			`.PRH_Burst_pin(OPB_Burst),`
347			`.PRH_Rdy_pin(OPB_Rdy),`
348			`.PRH_Data_I_pin(OPB_inD),`
349			`.PRH_Data_O_pin(OPB_outD),`
350			`.PRH_Data_T_pin());`
351
352			`//Monitoring`
353			`ila i_ila`
354			`(`
355			`.control(ila_control),`
356			`.clk(CLK_125M),`
357			`.data(ila_data_bus),`
358			`.trig0(ila_trig0),`
359			`.trig1(ila_trig1),`
360			`.trig2(ila_trig2)`
361			`);`
362
363
364
365			`assign ila_data_bus[31:0] = {0,gEMAC_Speed,MAC_Monitoring};`
366			`assign ila_data_bus[47:32] = {GMII_TxEN,GMII_TxER,GMII_TxD};`
367			`assign ila_data_bus[63:48] = {0,LoopbackFIFO_empty,LoopbackFIFO_full,Tx_wr,Tx_wa,Rx_ra,Rx_pa,Rx_rd};`
368			`assign ila_trig0 = Rx_rd;`
369			`assign ila_trig1 = Tx_wr;`
370			`assign ila_trig2 = LoopbackFIFO_full;`
371
372			`icon i_icon`
373			`(`
374			`.control0(ila_control)`
375			`);`
376
377			`endmodule`
378
379			`module icon`
380			`(`
381			`control0`
382			`);`
383			`output [35:0] control0;`
384			`endmodule`
385
386			`module ila`
387			`(`
388			`control,`
389			`clk,`
390			`data,`
391			`trig0,`
392			`trig1,`
393			`trig2`
394			`);`
395			`input [35:0] control;`
396			`input clk;`
397			`input [63:0] data;`
398			`input [0:0] trig0;`
399			`input [0:0] trig1;`
400			`input [0:0] trig2;`
401			`endmodule`