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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
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//I'm afraid that the synchronization chain is not good enough
//add addr_rd_gray_dl2                                         
 
module MAC_rx_FF (
Reset       ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface                                                                                                                                          
Fifo_data       ,
Fifo_data_en    ,
Fifo_full       ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface                                                                                                                                               
Rx_mac_ra   ,
Rx_mac_rd   ,
Rx_mac_data ,
Rx_mac_BE   ,
Rx_mac_sop  ,
Rx_mac_pa,
Rx_mac_eop
);
input           Reset       ;
input           Clk_MAC     ;
input           Clk_SYS     ;
                //MAC_rx_ctrl interface 
input   [7:0]   Fifo_data       ;
input           Fifo_data_en    ;
output          Fifo_full       ;
input           Fifo_data_err   ;
input           Fifo_data_end   ;
                //CPU
input           RX_APPEND_CRC       ;
input   [4:0]   Rx_Hwmark           ;
input   [4:0]   Rx_Lwmark           ;
                //user interface 
output          Rx_mac_ra   ;//
input           Rx_mac_rd   ;
output  [31:0]  Rx_mac_data ;
output  [1:0]   Rx_mac_BE   ;
output          Rx_mac_pa   ;
output          Rx_mac_sop  ;
output          Rx_mac_eop  ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter       State_byte3     =4'd0;
parameter       State_byte2     =4'd1;
parameter       State_byte1     =4'd2;
parameter       State_byte0     =4'd3;
parameter       State_be0       =4'd4;
parameter       State_be3       =4'd5;
parameter       State_be2       =4'd6;
parameter       State_be1       =4'd7;
parameter       State_err_end   =4'd8;
parameter       State_idle      =4'd9;
 
parameter       SYS_read        =3'd0;
parameter       SYS_pause       =3'd1;
parameter       SYS_wait_end    =3'd2;
parameter       SYS_idle        =3'd3;
parameter       FF_emtpy_err    =3'd4;
 
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_ungray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_gray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_gray_dl2;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_reg;
 
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_pl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_gray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_gray_dl2;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_ungray;
reg [35:0]      Din;
reg [35:0]      Din_tmp;
reg [35:0]      Din_tmp_reg;
wire[35:0]      Dout;
reg             Wr_en;
reg             Wr_en_tmp;
reg             Wr_en_ptr;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse4;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse3;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse2;
reg             Full;
reg             Almost_full;
reg             Empty /* synthesis syn_keep=1 */;
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [7:0]       Fifo_data_byte0;
reg [7:0]       Fifo_data_byte1;
reg [7:0]       Fifo_data_byte2;
reg [7:0]       Fifo_data_byte3;
reg             Fifo_data_en_dl1;
reg [7:0]       Fifo_data_dl1;
reg             Rx_mac_sop_tmp  ;
reg             Rx_mac_sop  ;
reg             Rx_mac_ra   ;
reg             Rx_mac_pa   ;
 
 
 
reg [2:0]       Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0]       Next_state_SYS ;
reg [5:0]       Packet_number_inFF /* synthesis syn_keep=1 */;
reg             Packet_number_sub ;
wire            Packet_number_add_edge;
reg             Packet_number_add_dl1;
reg             Packet_number_add_dl2;
reg             Packet_number_add ;
reg             Packet_number_add_tmp    ;
reg             Packet_number_add_tmp_dl1;
reg             Packet_number_add_tmp_dl2;
 
reg             Rx_mac_sop_tmp_dl1;
reg [35:0]      Dout_dl1;
reg [4:0]       Fifo_data_count;
reg             Rx_mac_pa_tmp       ;
reg             Add_wr_jump_tmp     ;
reg             Add_wr_jump_tmp_pl1 ;
reg             Add_wr_jump         ;
reg             Add_wr_jump_rd_pl1  ;
reg [4:0]       Rx_Hwmark_pl        ;
reg [4:0]       Rx_Lwmark_pl        ;
reg             Addr_freshed_ptr    ;
integer         i                   ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************    
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
    case (Current_state)
        State_idle:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else
                    Next_state  =Current_state;
        State_byte3:
                if (Fifo_data_en)
                    Next_state  =State_byte2;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be1;
                else
                    Next_state  =Current_state;
        State_byte2:
                if (Fifo_data_en)
                    Next_state  =State_byte1;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be2;
                else
                    Next_state  =Current_state;
        State_byte1:
                if (Fifo_data_en)
                    Next_state  =State_byte0;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be3;
                else
                    Next_state  =Current_state;
        State_byte0:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be0;
                else
                    Next_state  =Current_state;
        State_be1:
                Next_state      =State_idle;
        State_be2:
                Next_state      =State_idle;
        State_be3:
                Next_state      =State_idle;
        State_be0:
                Next_state      =State_idle;
        State_err_end:
                Next_state      =State_idle;
        default:
                Next_state      =State_idle;
    endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr_reg      <=0;
    else if (Current_state==State_idle)
        Add_wr_reg      <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
    if (Reset)
        Add_wr_gray         <=0;
    else
                begin
                Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset) begin
        Add_rd_gray_dl1         <=0;
                  Add_rd_gray_dl2         <=0;
                  end
    else begin
        Add_rd_gray_dl1         <=Add_rd_gray;
                  Add_rd_gray_dl2         <=Add_rd_gray_dl1;
         end
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_ungray       =0;
    else
                begin
                //Add_rd_ungray[`MAC_RX_FF_DEPTH-1]     =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];   
                Add_rd_ungray[`MAC_RX_FF_DEPTH-1]       =Add_rd_gray_dl2[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        //Add_rd_ungray[i]      =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; 
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl2[i];
                end
assign          Add_wr_pluse=Add_wr+1;
assign          Add_wr_pluse4=Add_wr+4;
assign          Add_wr_pluse3=Add_wr+3;
assign          Add_wr_pluse2=Add_wr+2;
 
 
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Full    <=0;
    else if (Add_wr_pluse==Add_rd_ungray)
        Full    <=1;
    else
        Full    <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Almost_full     <=0;
        else if (Add_wr_pluse4==Add_rd_ungray||
                 Add_wr_pluse3==Add_rd_ungray||
                 Add_wr_pluse2==Add_rd_ungray||
                 Add_wr_pluse==Add_rd_ungray
                 )
                Almost_full     <=1;
        else
                Almost_full     <=0;
 
assign          Fifo_full =Almost_full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr  <=0;
    else if (Current_state==State_err_end)
        Add_wr  <=Add_wr_reg;
    else if (Wr_en&&!Full)
        Add_wr  <=Add_wr +1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump_tmp <=1;
        else
            Add_wr_jump_tmp <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp_pl1 <=0;
        else
            Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump <=1;
        else if (Add_wr_jump_tmp_pl1)
            Add_wr_jump <=0;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_en_dl1    <=0;
    else
        Fifo_data_en_dl1    <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_dl1   <=0;
    else
        Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte3     <=0;
    else if (Current_state==State_byte3&&Fifo_data_en_dl1)
        Fifo_data_byte3     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte2     <=0;
    else if (Current_state==State_byte2&&Fifo_data_en_dl1)
        Fifo_data_byte2     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte1     <=0;
    else if (Current_state==State_byte1&&Fifo_data_en_dl1)
        Fifo_data_byte1     <=Fifo_data_dl1;
 
always @ (* )
    case (Current_state)
        State_be0:
            Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
        State_be1:
            Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
        State_be2:
            Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
        State_be3:
            Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
        default:
            Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
    endcase
 
always @ (*)
    if (Current_state==State_be0||Current_state==State_be1||
       Current_state==State_be2||Current_state==State_be3||
      (Current_state==State_byte0&&Fifo_data_en))
        Wr_en_tmp   =1;
    else
        Wr_en_tmp   =0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Din_tmp_reg <=0;
    else if(Wr_en_tmp)
        Din_tmp_reg <=Din_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Wr_en_ptr   <=0;
    else if(Current_state==State_idle)
        Wr_en_ptr   <=0;
    else if(Wr_en_tmp)
        Wr_en_ptr   <=1;
 
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Wr_en           <=0;
        Din             <=0;
        end
    else if(RX_APPEND_CRC)
        begin
        Wr_en           <=Wr_en_tmp;
        Din             <=Din_tmp;
        end
    else
        begin
        Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
        Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
        end
 
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add_tmp   <=0;
    else if (Current_state==State_be0||Current_state==State_be1||
             Current_state==State_be2||Current_state==State_be3)
        Packet_number_add_tmp   <=1;
    else
        Packet_number_add_tmp   <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_tmp_dl1   <=0;
        Packet_number_add_tmp_dl2   <=0;
        end
    else
        begin
        Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
        Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
        end
 
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.       
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles       
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add   <=0;
    else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
        Packet_number_add   <=1;
    else
        Packet_number_add   <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Current_state_SYS   <=SYS_idle;
    else
        Current_state_SYS   <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
    case (Current_state_SYS)
        SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
                Next_state_SYS  =SYS_read;
                    else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
                        Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_read:
            if (Dout[35])
                Next_state_SYS  =SYS_wait_end;
            else if (!Rx_mac_rd)
                Next_state_SYS  =SYS_pause;
            else if (Empty)
                Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_pause:
            if (Rx_mac_rd)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        FF_emtpy_err:
            if (!Empty)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;
        default:
                Next_state_SYS  =SYS_idle;
    endcase
 
 
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_dl1   <=0;
        Packet_number_add_dl2   <=0;
        end
    else
        begin
        Packet_number_add_dl1   <=Packet_number_add;
        Packet_number_add_dl2   <=Packet_number_add_dl1;
        end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
    if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
        Packet_number_sub       =1;
    else
        Packet_number_sub       =0;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Packet_number_inFF      <=0;
    else if (Packet_number_add_edge&&!Packet_number_sub)
        Packet_number_inFF      <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
        Packet_number_inFF      <=Packet_number_inFF - 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Fifo_data_count     <=0;
    else
        Fifo_data_count     <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_Hwmark_pl        <=0;
        Rx_Lwmark_pl        <=0;
        end
    else
        begin
        Rx_Hwmark_pl        <=Rx_Hwmark;
        Rx_Lwmark_pl        <=Rx_Lwmark;
        end
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
        Rx_mac_ra   <=1;
 
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd      <=0;
    else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
        Add_rd      <=Add_rd + 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd_pl1  <=0;
    else
        Add_rd_pl1  <=Add_rd;
 
always @(Add_rd_pl1,Add_rd)
    if (Add_rd_pl1==Add_rd)
        Addr_freshed_ptr      =0;
    else
        Addr_freshed_ptr      =1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
    if (Reset)
        Add_rd_gray         <=0;
    else
                begin
                Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
//
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset) begin
        Add_wr_gray_dl1     <=0;
                  Add_wr_gray_dl2     <=0;
                  end
    else begin
        Add_wr_gray_dl1     <=Add_wr_gray;
                  Add_wr_gray_dl2     <=Add_wr_gray_dl1;
         end
 
//Jeff added second synchronizer
reg Add_wr_jump_rd_pl2;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset) begin
        Add_wr_jump_rd_pl1  <=0;
                  Add_wr_jump_rd_pl2  <=0; end
    else begin
        Add_wr_jump_rd_pl1  <=Add_wr_jump;
                  Add_wr_jump_rd_pl2  <= Add_wr_jump_rd_pl1;
                  end
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_ungray       =0;
    //else if (!Add_wr_jump_rd_pl1)       
         else if (!Add_wr_jump_rd_pl2)
                begin
                //Add_wr_ungray[`MAC_RX_FF_DEPTH-1]     =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];   
                Add_wr_ungray[`MAC_RX_FF_DEPTH-1]       =Add_wr_gray_dl2[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        //Add_wr_ungray[i]      =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; 
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl2[i];
                end
//empty signal gen  
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Empty   <=1;
    else if (Add_rd==Add_wr_ungray)
        Empty   <=1;
    else
        Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Dout_dl1    <=0;
    else
        Dout_dl1    <=Dout;
 
assign  Rx_mac_data     =Dout_dl1[31:0];
assign  Rx_mac_BE       =Dout_dl1[33:32];
assign  Rx_mac_eop      =Dout_dl1[35];
 
//aligned to Addr_rd 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa_tmp   <=0;
    else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
        Rx_mac_pa_tmp   <=1;
    else
        Rx_mac_pa_tmp   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa   <=0;
    else
        Rx_mac_pa   <=Rx_mac_pa_tmp;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_sop_tmp      <=0;
    else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
        Rx_mac_sop_tmp      <=1;
    else
        Rx_mac_sop_tmp      <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_mac_sop_tmp_dl1  <=0;
        Rx_mac_sop          <=0;
        end
    else
        begin
        Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
        Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
        end
 
 
 
//******************************************************************************
 
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a         (Din        ),
.wren_a         (Wr_en      ),
.address_a      (Add_wr     ),
.address_b      (Add_rd     ),
.clock_a        (Clk_MAC    ),
.clock_b        (Clk_SYS    ),
.q_b            (Dout       ));
 
endmodule

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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_rx_FF.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.6 2008/08/17 11:41:30 maverickist`
43			`// no message`
44			`//`
45			`// Revision 1.5 2006/06/25 04:58:56 maverickist`
46			`// no message`
47			`//`
48			`// Revision 1.4 2006/05/28 05:09:20 maverickist`
49			`// no message`
50			`//`
51			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
52			`// verification is complete.`
53			`//`
54			`// Revision 1.3 2005/12/16 06:44:16 Administrator`
55			`// replaced tab with space.`
56			`// passed 9.6k length frame test.`
57			`//`
58			`// Revision 1.2 2005/12/13 12:15:37 Administrator`
59			`// no message`
60			`//`
61			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
62			`// no message`
63			`//`
64			`//I'm afraid that the synchronization chain is not good enough`
65			`//add addr_rd_gray_dl2`
66
67			`module MAC_rx_FF (`
68			`Reset ,`
69			`Clk_MAC ,`
70			`Clk_SYS ,`
71			`//MAC_rx_ctrl interface`
72			`Fifo_data ,`
73			`Fifo_data_en ,`
74			`Fifo_full ,`
75			`Fifo_data_err ,`
76			`Fifo_data_end ,`
77			`//CPU`
78			`Rx_Hwmark,`
79			`Rx_Lwmark,`
80			`RX_APPEND_CRC,`
81			`//user interface`
82			`Rx_mac_ra ,`
83			`Rx_mac_rd ,`
84			`Rx_mac_data ,`
85			`Rx_mac_BE ,`
86			`Rx_mac_sop ,`
87			`Rx_mac_pa,`
88			`Rx_mac_eop`
89			`);`
90			`input Reset ;`
91			`input Clk_MAC ;`
92			`input Clk_SYS ;`
93			`//MAC_rx_ctrl interface`
94			`input [7:0] Fifo_data ;`
95			`input Fifo_data_en ;`
96			`output Fifo_full ;`
97			`input Fifo_data_err ;`
98			`input Fifo_data_end ;`
99			`//CPU`
100			`input RX_APPEND_CRC ;`
101			`input [4:0] Rx_Hwmark ;`
102			`input [4:0] Rx_Lwmark ;`
103			`//user interface`
104			`output Rx_mac_ra ;//`
105			`input Rx_mac_rd ;`
106			`output [31:0] Rx_mac_data ;`
107			`output [1:0] Rx_mac_BE ;`
108			`output Rx_mac_pa ;`
109			`output Rx_mac_sop ;`
110			`output Rx_mac_eop ;`
111
112			`//******************************************************************************`
113			`//internal signals`
114			`//******************************************************************************`
115			`parameter State_byte3 =4'd0;`
116			`parameter State_byte2 =4'd1;`
117			`parameter State_byte1 =4'd2;`
118			`parameter State_byte0 =4'd3;`
119			`parameter State_be0 =4'd4;`
120			`parameter State_be3 =4'd5;`
121			`parameter State_be2 =4'd6;`
122			`parameter State_be1 =4'd7;`
123			`parameter State_err_end =4'd8;`
124			`parameter State_idle =4'd9;`
125
126			`parameter SYS_read =3'd0;`
127			`parameter SYS_pause =3'd1;`
128			`parameter SYS_wait_end =3'd2;`
129			`parameter SYS_idle =3'd3;`
130			`parameter FF_emtpy_err =3'd4;`
131
132			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
133			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
134			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
135			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
136			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl2;
137			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
138
139			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
140			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
141			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
142			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
143			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl2;
144			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
145			`reg [35:0] Din;`
146			`reg [35:0] Din_tmp;`
147			`reg [35:0] Din_tmp_reg;`
148			`wire[35:0] Dout;`
149			`reg Wr_en;`
150			`reg Wr_en_tmp;`
151			`reg Wr_en_ptr;`
152			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
153			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
154			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
155			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
156			`reg Full;`
157			`reg Almost_full;`
158			`reg Empty /* synthesis syn_keep=1 */;`
159			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
160			`reg [3:0] Next_state;`
161			`reg [7:0] Fifo_data_byte0;`
162			`reg [7:0] Fifo_data_byte1;`
163			`reg [7:0] Fifo_data_byte2;`
164			`reg [7:0] Fifo_data_byte3;`
165			`reg Fifo_data_en_dl1;`
166			`reg [7:0] Fifo_data_dl1;`
167			`reg Rx_mac_sop_tmp ;`
168			`reg Rx_mac_sop ;`
169			`reg Rx_mac_ra ;`
170			`reg Rx_mac_pa ;`
171
172
173
174			`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
175			`reg [2:0] Next_state_SYS ;`
176			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
177			`reg Packet_number_sub ;`
178			`wire Packet_number_add_edge;`
179			`reg Packet_number_add_dl1;`
180			`reg Packet_number_add_dl2;`
181			`reg Packet_number_add ;`
182			`reg Packet_number_add_tmp ;`
183			`reg Packet_number_add_tmp_dl1;`
184			`reg Packet_number_add_tmp_dl2;`
185
186			`reg Rx_mac_sop_tmp_dl1;`
187			`reg [35:0] Dout_dl1;`
188			`reg [4:0] Fifo_data_count;`
189			`reg Rx_mac_pa_tmp ;`
190			`reg Add_wr_jump_tmp ;`
191			`reg Add_wr_jump_tmp_pl1 ;`
192			`reg Add_wr_jump ;`
193			`reg Add_wr_jump_rd_pl1 ;`
194			`reg [4:0] Rx_Hwmark_pl ;`
195			`reg [4:0] Rx_Lwmark_pl ;`
196			`reg Addr_freshed_ptr ;`
197			`integer i ;`
198			`//******************************************************************************`
199			`//domain Clk_MAC,write data to dprom.a-port for write`
200			`//******************************************************************************`
201			`always @ (posedge Clk_MAC or posedge Reset)`
202			`if (Reset)`
203			`Current_state <=State_idle;`
204			`else`
205			`Current_state <=Next_state;`
206
207			`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
208			`case (Current_state)`
209			`State_idle:`
210			`if (Fifo_data_en)`
211			`Next_state =State_byte3;`
212			`else`
213			`Next_state =Current_state;`
214			`State_byte3:`
215			`if (Fifo_data_en)`
216			`Next_state =State_byte2;`
217			`else if (Fifo_data_err)`
218			`Next_state =State_err_end;`
219			`else if (Fifo_data_end)`
220			`Next_state =State_be1;`
221			`else`
222			`Next_state =Current_state;`
223			`State_byte2:`
224			`if (Fifo_data_en)`
225			`Next_state =State_byte1;`
226			`else if (Fifo_data_err)`
227			`Next_state =State_err_end;`
228			`else if (Fifo_data_end)`
229			`Next_state =State_be2;`
230			`else`
231			`Next_state =Current_state;`
232			`State_byte1:`
233			`if (Fifo_data_en)`
234			`Next_state =State_byte0;`
235			`else if (Fifo_data_err)`
236			`Next_state =State_err_end;`
237			`else if (Fifo_data_end)`
238			`Next_state =State_be3;`
239			`else`
240			`Next_state =Current_state;`
241			`State_byte0:`
242			`if (Fifo_data_en)`
243			`Next_state =State_byte3;`
244			`else if (Fifo_data_err)`
245			`Next_state =State_err_end;`
246			`else if (Fifo_data_end)`
247			`Next_state =State_be0;`
248			`else`
249			`Next_state =Current_state;`
250			`State_be1:`
251			`Next_state =State_idle;`
252			`State_be2:`
253			`Next_state =State_idle;`
254			`State_be3:`
255			`Next_state =State_idle;`
256			`State_be0:`
257			`Next_state =State_idle;`
258			`State_err_end:`
259			`Next_state =State_idle;`
260			`default:`
261			`Next_state =State_idle;`
262			`endcase`
263
264			`//`
265			`always @ (posedge Clk_MAC or posedge Reset)`
266			`if (Reset)`
267			`Add_wr_reg <=0;`
268			`else if (Current_state==State_idle)`
269			`Add_wr_reg <=Add_wr;`
270
271			`//`
272
273
274			`always @ (posedge Reset or posedge Clk_MAC)`
275			`if (Reset)`
276			`Add_wr_gray <=0;`
277			`else`
278			`begin`
279			Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
280			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
281			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
282			`end`
283
284			`//`
285
286			`always @ (posedge Clk_MAC or posedge Reset)`
287			`if (Reset) begin`
288			`Add_rd_gray_dl1 <=0;`
289			`Add_rd_gray_dl2 <=0;`
290			`end`
291			`else begin`
292			`Add_rd_gray_dl1 <=Add_rd_gray;`
293			`Add_rd_gray_dl2 <=Add_rd_gray_dl1;`
294			`end`
295
296			`always @ (posedge Clk_MAC or posedge Reset)`
297			`if (Reset)`
298			`Add_rd_ungray =0;`
299			`else`
300			`begin`
301			//Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
302			Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl2[`MAC_RX_FF_DEPTH-1];
303			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
304			`//Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
305			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl2[i];`
306			`end`
307			`assign Add_wr_pluse=Add_wr+1;`
308			`assign Add_wr_pluse4=Add_wr+4;`
309			`assign Add_wr_pluse3=Add_wr+3;`
310			`assign Add_wr_pluse2=Add_wr+2;`
311
312
313
314			`always @ (posedge Clk_MAC or posedge Reset)`
315			`if (Reset)`
316			`Full <=0;`
317			`else if (Add_wr_pluse==Add_rd_ungray)`
318			`Full <=1;`
319			`else`
320			`Full <=0;`
321
322			`always @ (posedge Clk_MAC or posedge Reset)`
323			`if (Reset)`
324			`Almost_full <=0;`
325			`else if (Add_wr_pluse4==Add_rd_ungray\|\|`
326			`Add_wr_pluse3==Add_rd_ungray\|\|`
327			`Add_wr_pluse2==Add_rd_ungray\|\|`
328			`Add_wr_pluse==Add_rd_ungray`
329			`)`
330			`Almost_full <=1;`
331			`else`
332			`Almost_full <=0;`
333
334			`assign Fifo_full =Almost_full;`
335
336			`//`
337			`always @ (posedge Clk_MAC or posedge Reset)`
338			`if (Reset)`
339			`Add_wr <=0;`
340			`else if (Current_state==State_err_end)`
341			`Add_wr <=Add_wr_reg;`
342			`else if (Wr_en&&!Full)`
343			`Add_wr <=Add_wr +1;`
344
345			`always @ (posedge Clk_MAC or posedge Reset)`
346			`if (Reset)`
347			`Add_wr_jump_tmp <=0;`
348			`else if (Current_state==State_err_end)`
349			`Add_wr_jump_tmp <=1;`
350			`else`
351			`Add_wr_jump_tmp <=0;`
352
353			`always @ (posedge Clk_MAC or posedge Reset)`
354			`if (Reset)`
355			`Add_wr_jump_tmp_pl1 <=0;`
356			`else`
357			`Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;`
358
359			`always @ (posedge Clk_MAC or posedge Reset)`
360			`if (Reset)`
361			`Add_wr_jump <=0;`
362			`else if (Current_state==State_err_end)`
363			`Add_wr_jump <=1;`
364			`else if (Add_wr_jump_tmp_pl1)`
365			`Add_wr_jump <=0;`
366
367			`//`
368			`always @ (posedge Clk_MAC or posedge Reset)`
369			`if (Reset)`
370			`Fifo_data_en_dl1 <=0;`
371			`else`
372			`Fifo_data_en_dl1 <=Fifo_data_en;`
373
374			`always @ (posedge Clk_MAC or posedge Reset)`
375			`if (Reset)`
376			`Fifo_data_dl1 <=0;`
377			`else`
378			`Fifo_data_dl1 <=Fifo_data;`
379
380			`always @ (posedge Clk_MAC or posedge Reset)`
381			`if (Reset)`
382			`Fifo_data_byte3 <=0;`
383			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
384			`Fifo_data_byte3 <=Fifo_data_dl1;`
385
386			`always @ (posedge Clk_MAC or posedge Reset)`
387			`if (Reset)`
388			`Fifo_data_byte2 <=0;`
389			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
390			`Fifo_data_byte2 <=Fifo_data_dl1;`
391
392			`always @ (posedge Clk_MAC or posedge Reset)`
393			`if (Reset)`
394			`Fifo_data_byte1 <=0;`
395			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
396			`Fifo_data_byte1 <=Fifo_data_dl1;`
397
398			`always @ (* )`
399			`case (Current_state)`
400			`State_be0:`
401			`Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
402			`State_be1:`
403			`Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};`
404			`State_be2:`
405			`Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
406			`State_be3:`
407			`Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
408			`default:`
409			`Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
410			`endcase`
411
412			`always @ (*)`
413			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
414			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
415			`(Current_state==State_byte0&&Fifo_data_en))`
416			`Wr_en_tmp =1;`
417			`else`
418			`Wr_en_tmp =0;`
419
420			`always @ (posedge Clk_MAC or posedge Reset)`
421			`if (Reset)`
422			`Din_tmp_reg <=0;`
423			`else if(Wr_en_tmp)`
424			`Din_tmp_reg <=Din_tmp;`
425
426			`always @ (posedge Clk_MAC or posedge Reset)`
427			`if (Reset)`
428			`Wr_en_ptr <=0;`
429			`else if(Current_state==State_idle)`
430			`Wr_en_ptr <=0;`
431			`else if(Wr_en_tmp)`
432			`Wr_en_ptr <=1;`
433
434			`//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS`
435			`always @ (posedge Clk_MAC or posedge Reset)`
436			`if (Reset)`
437			`begin`
438			`Wr_en <=0;`
439			`Din <=0;`
440			`end`
441			`else if(RX_APPEND_CRC)`
442			`begin`
443			`Wr_en <=Wr_en_tmp;`
444			`Din <=Din_tmp;`
445			`end`
446			`else`
447			`begin`
448			`Wr_en <=Wr_en_tmp&&Wr_en_ptr;`
449			`Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};`
450			`end`
451
452			`//this signal for read side to handle the packet number in fifo`
453			`always @ (posedge Clk_MAC or posedge Reset)`
454			`if (Reset)`
455			`Packet_number_add_tmp <=0;`
456			`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
457			`Current_state==State_be2\|\|Current_state==State_be3)`
458			`Packet_number_add_tmp <=1;`
459			`else`
460			`Packet_number_add_tmp <=0;`
461
462			`always @ (posedge Clk_MAC or posedge Reset)`
463			`if (Reset)`
464			`begin`
465			`Packet_number_add_tmp_dl1 <=0;`
466			`Packet_number_add_tmp_dl2 <=0;`
467			`end`
468			`else`
469			`begin`
470			`Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;`
471			`Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;`
472			`end`
473
474			`//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.`
475			`//expand to two cycles long almost=16 ns`
476			`//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles`
477			`always @ (posedge Clk_MAC or posedge Reset)`
478			`if (Reset)`
479			`Packet_number_add <=0;`
480			`else if (Packet_number_add_tmp_dl1\|\|Packet_number_add_tmp_dl2)`
481			`Packet_number_add <=1;`
482			`else`
483			`Packet_number_add <=0;`
484
485
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508			`//******************************************************************************`
509			`//domain Clk_SYS,read data from dprom.b-port for read`
510			`//******************************************************************************`
511
512
513			`always @ (posedge Clk_SYS or posedge Reset)`
514			`if (Reset)`
515			`Current_state_SYS <=SYS_idle;`
516			`else`
517			`Current_state_SYS <=Next_state_SYS;`
518
519			`always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)`
520			`case (Current_state_SYS)`
521			`SYS_idle:`
522			`if (Rx_mac_rd&&Rx_mac_ra&&!Empty)`
523			`Next_state_SYS =SYS_read;`
524			`else if(Rx_mac_rd&&Rx_mac_ra&&Empty)`
525			`Next_state_SYS =FF_emtpy_err;`
526			`else`
527			`Next_state_SYS =Current_state_SYS;`
528			`SYS_read:`
529			`if (Dout[35])`
530			`Next_state_SYS =SYS_wait_end;`
531			`else if (!Rx_mac_rd)`
532			`Next_state_SYS =SYS_pause;`
533			`else if (Empty)`
534			`Next_state_SYS =FF_emtpy_err;`
535			`else`
536			`Next_state_SYS =Current_state_SYS;`
537			`SYS_pause:`
538			`if (Rx_mac_rd)`
539			`Next_state_SYS =SYS_read;`
540			`else`
541			`Next_state_SYS =Current_state_SYS;`
542			`FF_emtpy_err:`
543			`if (!Empty)`
544			`Next_state_SYS =SYS_read;`
545			`else`
546			`Next_state_SYS =Current_state_SYS;`
547			`SYS_wait_end:`
548			`if (!Rx_mac_rd)`
549			`Next_state_SYS =SYS_idle;`
550			`else`
551			`Next_state_SYS =Current_state_SYS;`
552			`default:`
553			`Next_state_SYS =SYS_idle;`
554			`endcase`
555
556
557			`//gen Rx_mac_ra`
558			`always @ (posedge Clk_SYS or posedge Reset)`
559			`if (Reset)`
560			`begin`
561			`Packet_number_add_dl1 <=0;`
562			`Packet_number_add_dl2 <=0;`
563			`end`
564			`else`
565			`begin`
566			`Packet_number_add_dl1 <=Packet_number_add;`
567			`Packet_number_add_dl2 <=Packet_number_add_dl1;`
568			`end`
569			`assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;`
570
571			`always @ (Current_state_SYS or Next_state_SYS)`
572			`if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)`
573			`Packet_number_sub =1;`
574			`else`
575			`Packet_number_sub =0;`
576
577			`always @ (posedge Clk_SYS or posedge Reset)`
578			`if (Reset)`
579			`Packet_number_inFF <=0;`
580			`else if (Packet_number_add_edge&&!Packet_number_sub)`
581			`Packet_number_inFF <=Packet_number_inFF + 1;`
582			`else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)`
583			`Packet_number_inFF <=Packet_number_inFF - 1;`
584
585			`always @ (posedge Clk_SYS or posedge Reset)`
586			`if (Reset)`
587			`Fifo_data_count <=0;`
588			`else`
589			Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
590
591			`always @ (posedge Clk_SYS or posedge Reset)`
592			`if (Reset)`
593			`begin`
594			`Rx_Hwmark_pl <=0;`
595			`Rx_Lwmark_pl <=0;`
596			`end`
597			`else`
598			`begin`
599			`Rx_Hwmark_pl <=Rx_Hwmark;`
600			`Rx_Lwmark_pl <=Rx_Lwmark;`
601			`end`
602
603			`always @ (posedge Clk_SYS or posedge Reset)`
604			`if (Reset)`
605			`Rx_mac_ra <=0;`
606			`else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)`
607			`Rx_mac_ra <=0;`
608			`else if (Packet_number_inFF>=1\|\|Fifo_data_count>=Rx_Hwmark_pl)`
609			`Rx_mac_ra <=1;`
610
611
612			`//control Add_rd signal;`
613			`always @ (posedge Clk_SYS or posedge Reset)`
614			`if (Reset)`
615			`Add_rd <=0;`
616			`else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))`
617			`Add_rd <=Add_rd + 1;`
618
619			`always @ (posedge Clk_SYS or posedge Reset)`
620			`if (Reset)`
621			`Add_rd_pl1 <=0;`
622			`else`
623			`Add_rd_pl1 <=Add_rd;`
624
625			`always @(Add_rd_pl1,Add_rd)`
626			`if (Add_rd_pl1==Add_rd)`
627			`Addr_freshed_ptr =0;`
628			`else`
629			`Addr_freshed_ptr =1;`
630
631			`//`
632			`always @ (posedge Reset or posedge Clk_SYS)`
633			`if (Reset)`
634			`Add_rd_gray <=0;`
635			`else`
636			`begin`
637			Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
638			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
639			`Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];`
640			`end`
641			`//`
642
643			`always @ (posedge Clk_SYS or posedge Reset)`
644			`if (Reset) begin`
645			`Add_wr_gray_dl1 <=0;`
646			`Add_wr_gray_dl2 <=0;`
647			`end`
648			`else begin`
649			`Add_wr_gray_dl1 <=Add_wr_gray;`
650			`Add_wr_gray_dl2 <=Add_wr_gray_dl1;`
651			`end`
652
653			`//Jeff added second synchronizer`
654			`reg Add_wr_jump_rd_pl2;`
655
656			`always @ (posedge Clk_SYS or posedge Reset)`
657			`if (Reset) begin`
658			`Add_wr_jump_rd_pl1 <=0;`
659			`Add_wr_jump_rd_pl2 <=0; end`
660			`else begin`
661			`Add_wr_jump_rd_pl1 <=Add_wr_jump;`
662			`Add_wr_jump_rd_pl2 <= Add_wr_jump_rd_pl1;`
663			`end`
664
665			`always @ (posedge Clk_SYS or posedge Reset)`
666			`if (Reset)`
667			`Add_wr_ungray =0;`
668			`//else if (!Add_wr_jump_rd_pl1)`
669			`else if (!Add_wr_jump_rd_pl2)`
670			`begin`
671			//Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
672			Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl2[`MAC_RX_FF_DEPTH-1];
673			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
674			`//Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];`
675			`Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl2[i];`
676			`end`
677			`//empty signal gen`
678			`always @ (posedge Clk_SYS or posedge Reset)`
679			`if (Reset)`
680			`Empty <=1;`
681			`else if (Add_rd==Add_wr_ungray)`
682			`Empty <=1;`
683			`else`
684			`Empty <=0;`
685
686
687
688			`always @ (posedge Clk_SYS or posedge Reset)`
689			`if (Reset)`
690			`Dout_dl1 <=0;`
691			`else`
692			`Dout_dl1 <=Dout;`
693
694			`assign Rx_mac_data =Dout_dl1[31:0];`
695			`assign Rx_mac_BE =Dout_dl1[33:32];`
696			`assign Rx_mac_eop =Dout_dl1[35];`
697
698			`//aligned to Addr_rd`
699			`always @ (posedge Clk_SYS or posedge Reset)`
700			`if (Reset)`
701			`Rx_mac_pa_tmp <=0;`
702			`else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))`
703			`Rx_mac_pa_tmp <=1;`
704			`else`
705			`Rx_mac_pa_tmp <=0;`
706
707
708
709			`always @ (posedge Clk_SYS or posedge Reset)`
710			`if (Reset)`
711			`Rx_mac_pa <=0;`
712			`else`
713			`Rx_mac_pa <=Rx_mac_pa_tmp;`
714
715
716
717			`always @ (posedge Clk_SYS or posedge Reset)`
718			`if (Reset)`
719			`Rx_mac_sop_tmp <=0;`
720			`else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)`
721			`Rx_mac_sop_tmp <=1;`
722			`else`
723			`Rx_mac_sop_tmp <=0;`
724
725
726
727			`always @ (posedge Clk_SYS or posedge Reset)`
728			`if (Reset)`
729			`begin`
730			`Rx_mac_sop_tmp_dl1 <=0;`
731			`Rx_mac_sop <=0;`
732			`end`
733			`else`
734			`begin`
735			`Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;`
736			`Rx_mac_sop <=Rx_mac_sop_tmp_dl1;`
737			`end`
738
739
740
741			`//******************************************************************************`
742
743			duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
744			`.data_a (Din ),`
745			`.wren_a (Wr_en ),`
746			`.address_a (Add_wr ),`
747			`.address_b (Add_rd ),`
748			`.clock_a (Clk_MAC ),`
749			`.clock_b (Clk_SYS ),`
750			`.q_b (Dout ));`
751
752			`endmodule`