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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
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//
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module MAC_rx_FF (
Reset       ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface
Fifo_data       ,
Fifo_data_en    ,
Fifo_full       ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface
Rx_mac_ra   ,
Rx_mac_rd   ,
Rx_mac_data ,
Rx_mac_BE   ,
Rx_mac_sop  ,
Rx_mac_pa,
Rx_mac_eop
);
input           Reset       ;
input           Clk_MAC     ;
input           Clk_SYS     ;
                //MAC_rx_ctrl interface
input   [7:0]   Fifo_data       ;
input           Fifo_data_en    ;
output          Fifo_full       ;
input           Fifo_data_err   ;
input           Fifo_data_end   ;
                //CPU
input           RX_APPEND_CRC       ;
input   [4:0]   Rx_Hwmark           ;
input   [4:0]   Rx_Lwmark           ;
                //user interface
output          Rx_mac_ra   ;//
input           Rx_mac_rd   ;
output  [31:0]  Rx_mac_data ;
output  [1:0]   Rx_mac_BE   ;
output          Rx_mac_pa   ;
output          Rx_mac_sop  ;
output          Rx_mac_eop  ;
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter       State_byte3     =4'd0;
parameter       State_byte2     =4'd1;
parameter       State_byte1     =4'd2;
parameter       State_byte0     =4'd3;
parameter       State_be0       =4'd4;
parameter       State_be3       =4'd5;
parameter       State_be2       =4'd6;
parameter       State_be1       =4'd7;
parameter       State_err_end   =4'd8;
parameter       State_idle      =4'd9;
 
parameter       SYS_read        =3'd0;
parameter       SYS_pause       =3'd1;
parameter       SYS_wait_end    =3'd2;
parameter       SYS_idle        =3'd3;
parameter       FF_emtpy_err    =3'd4;
 
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_ungray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_gray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_wr_reg;
 
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_pl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_gray;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0]       Add_rd_ungray;
reg [35:0]      Din;
reg [35:0]      Din_tmp;
reg [35:0]      Din_tmp_reg;
wire[35:0]      Dout;
reg             Wr_en;
reg             Wr_en_tmp;
reg             Wr_en_ptr;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse4;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse3;
wire[`MAC_RX_FF_DEPTH-1:0]       Add_wr_pluse2;
reg             Full;
reg             Almost_full;
reg             Empty /* synthesis syn_keep=1 */;
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [7:0]       Fifo_data_byte0;
reg [7:0]       Fifo_data_byte1;
reg [7:0]       Fifo_data_byte2;
reg [7:0]       Fifo_data_byte3;
reg             Fifo_data_en_dl1;
reg [7:0]       Fifo_data_dl1;
reg             Rx_mac_sop_tmp  ;
reg             Rx_mac_sop  ;
reg             Rx_mac_ra   ;
reg             Rx_mac_pa   ;
 
 
 
reg [2:0]       Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0]       Next_state_SYS ;
reg [5:0]       Packet_number_inFF /* synthesis syn_keep=1 */;
reg             Packet_number_sub ;
wire            Packet_number_add_edge;
reg             Packet_number_add_dl1;
reg             Packet_number_add_dl2;
reg             Packet_number_add ;
reg             Packet_number_add_tmp    ;
reg             Packet_number_add_tmp_dl1;
reg             Packet_number_add_tmp_dl2;
 
reg             Rx_mac_sop_tmp_dl1;
reg [35:0]      Dout_dl1;
reg [4:0]       Fifo_data_count;
reg             Rx_mac_pa_tmp       ;
reg             Add_wr_jump_tmp     ;
reg             Add_wr_jump_tmp_pl1 ;
reg             Add_wr_jump         ;
reg             Add_wr_jump_rd_pl1  ;
reg [4:0]       Rx_Hwmark_pl        ;
reg [4:0]       Rx_Lwmark_pl        ;
reg             Addr_freshed_ptr    ;
integer         i                   ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
    case (Current_state)
        State_idle:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else
                    Next_state  =Current_state;
        State_byte3:
                if (Fifo_data_en)
                    Next_state  =State_byte2;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be1;
                else
                    Next_state  =Current_state;
        State_byte2:
                if (Fifo_data_en)
                    Next_state  =State_byte1;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be2;
                else
                    Next_state  =Current_state;
        State_byte1:
                if (Fifo_data_en)
                    Next_state  =State_byte0;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be3;
                else
                    Next_state  =Current_state;
        State_byte0:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be0;
                else
                    Next_state  =Current_state;
        State_be1:
                Next_state      =State_idle;
        State_be2:
                Next_state      =State_idle;
        State_be3:
                Next_state      =State_idle;
        State_be0:
                Next_state      =State_idle;
        State_err_end:
                Next_state      =State_idle;
        default:
                Next_state      =State_idle;
    endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr_reg      <=0;
    else if (Current_state==State_idle)
        Add_wr_reg      <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
    if (Reset)
        Add_wr_gray         <=0;
    else
                begin
                Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_gray_dl1         <=0;
    else
        Add_rd_gray_dl1         <=Add_rd_gray;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_ungray       =0;
    else
                begin
                Add_rd_ungray[`MAC_RX_FF_DEPTH-1]       =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
                end
assign          Add_wr_pluse=Add_wr+1;
assign          Add_wr_pluse4=Add_wr+4;
assign          Add_wr_pluse3=Add_wr+3;
assign          Add_wr_pluse2=Add_wr+2;
 
 
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Full    <=0;
    else if (Add_wr_pluse==Add_rd_ungray)
        Full    <=1;
    else
        Full    <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Almost_full     <=0;
        else if (Add_wr_pluse4==Add_rd_ungray||
                 Add_wr_pluse3==Add_rd_ungray||
                 Add_wr_pluse2==Add_rd_ungray||
                 Add_wr_pluse==Add_rd_ungray
                 )
                Almost_full     <=1;
        else
                Almost_full     <=0;
 
assign          Fifo_full =Almost_full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr  <=0;
    else if (Current_state==State_err_end)
        Add_wr  <=Add_wr_reg;
    else if (Wr_en&&!Full)
        Add_wr  <=Add_wr +1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump_tmp <=1;
        else
            Add_wr_jump_tmp <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp_pl1 <=0;
        else
            Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump <=1;
        else if (Add_wr_jump_tmp_pl1)
            Add_wr_jump <=0;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_en_dl1    <=0;
    else
        Fifo_data_en_dl1    <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_dl1   <=0;
    else
        Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte3     <=0;
    else if (Current_state==State_byte3&&Fifo_data_en_dl1)
        Fifo_data_byte3     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte2     <=0;
    else if (Current_state==State_byte2&&Fifo_data_en_dl1)
        Fifo_data_byte2     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte1     <=0;
    else if (Current_state==State_byte1&&Fifo_data_en_dl1)
        Fifo_data_byte1     <=Fifo_data_dl1;
 
always @ (* )
    case (Current_state)
        State_be0:
            Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
        State_be1:
            Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
        State_be2:
            Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
        State_be3:
            Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
        default:
            Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
    endcase
 
always @ (*)
    if (Current_state==State_be0||Current_state==State_be1||
       Current_state==State_be2||Current_state==State_be3||
      (Current_state==State_byte0&&Fifo_data_en))
        Wr_en_tmp   =1;
    else
        Wr_en_tmp   =0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Din_tmp_reg <=0;
    else if(Wr_en_tmp)
        Din_tmp_reg <=Din_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Wr_en_ptr   <=0;
    else if(Current_state==State_idle)
        Wr_en_ptr   <=0;
    else if(Wr_en_tmp)
        Wr_en_ptr   <=1;
 
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Wr_en           <=0;
        Din             <=0;
        end
    else if(RX_APPEND_CRC)
        begin
        Wr_en           <=Wr_en_tmp;
        Din             <=Din_tmp;
        end
    else
        begin
        Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
        Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
        end
 
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add_tmp   <=0;
    else if (Current_state==State_be0||Current_state==State_be1||
             Current_state==State_be2||Current_state==State_be3)
        Packet_number_add_tmp   <=1;
    else
        Packet_number_add_tmp   <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_tmp_dl1   <=0;
        Packet_number_add_tmp_dl2   <=0;
        end
    else
        begin
        Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
        Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
        end
 
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add   <=0;
    else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
        Packet_number_add   <=1;
    else
        Packet_number_add   <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Current_state_SYS   <=SYS_idle;
    else
        Current_state_SYS   <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
    case (Current_state_SYS)
        SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
                Next_state_SYS  =SYS_read;
                    else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
                        Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_read:
            if (Dout[35])
                Next_state_SYS  =SYS_wait_end;
            else if (!Rx_mac_rd)
                Next_state_SYS  =SYS_pause;
            else if (Empty)
                Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_pause:
            if (Rx_mac_rd)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        FF_emtpy_err:
            if (!Empty)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;
        default:
                Next_state_SYS  =SYS_idle;
    endcase
 
 
//gen Rx_mac_ra
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_dl1   <=0;
        Packet_number_add_dl2   <=0;
        end
    else
        begin
        Packet_number_add_dl1   <=Packet_number_add;
        Packet_number_add_dl2   <=Packet_number_add_dl1;
        end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
    if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
        Packet_number_sub       =1;
    else
        Packet_number_sub       =0;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Packet_number_inFF      <=0;
    else if (Packet_number_add_edge&&!Packet_number_sub)
        Packet_number_inFF      <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
        Packet_number_inFF      <=Packet_number_inFF - 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Fifo_data_count     <=0;
    else
        Fifo_data_count     <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_Hwmark_pl        <=0;
        Rx_Lwmark_pl        <=0;
        end
    else
        begin
        Rx_Hwmark_pl        <=Rx_Hwmark;
        Rx_Lwmark_pl        <=Rx_Lwmark;
        end
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
        Rx_mac_ra   <=1;
 
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd      <=0;
    else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
        Add_rd      <=Add_rd + 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd_pl1  <=0;
    else
        Add_rd_pl1  <=Add_rd;
 
always @(Add_rd_pl1,Add_rd)
    if (Add_rd_pl1==Add_rd)
        Addr_freshed_ptr      =0;
    else
        Addr_freshed_ptr      =1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
    if (Reset)
        Add_rd_gray         <=0;
    else
                begin
                Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
//
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_gray_dl1     <=0;
    else
        Add_wr_gray_dl1     <=Add_wr_gray;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_jump_rd_pl1  <=0;
    else
        Add_wr_jump_rd_pl1  <=Add_wr_jump;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_ungray       =0;
    else if (!Add_wr_jump_rd_pl1)
                begin
                Add_wr_ungray[`MAC_RX_FF_DEPTH-1]       =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
                end
//empty signal gen
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Empty   <=1;
    else if (Add_rd==Add_wr_ungray)
        Empty   <=1;
    else
        Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Dout_dl1    <=0;
    else
        Dout_dl1    <=Dout;
 
assign  Rx_mac_data     =Dout_dl1[31:0];
assign  Rx_mac_BE       =Dout_dl1[33:32];
assign  Rx_mac_eop      =Dout_dl1[35];
 
//aligned to Addr_rd
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa_tmp   <=0;
    else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
        Rx_mac_pa_tmp   <=1;
    else
        Rx_mac_pa_tmp   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa   <=0;
    else
        Rx_mac_pa   <=Rx_mac_pa_tmp;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_sop_tmp      <=0;
    else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
        Rx_mac_sop_tmp      <=1;
    else
        Rx_mac_sop_tmp      <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_mac_sop_tmp_dl1  <=0;
        Rx_mac_sop          <=0;
        end
    else
        begin
        Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
        Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
        end
 
 
 
//******************************************************************************
 
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a         (Din        ),
.wren_a         (Wr_en      ),
.address_a      (Add_wr     ),
.address_b      (Add_rd     ),
.clock_a        (Clk_MAC    ),
.clock_b        (Clk_SYS    ),
.q_b            (Dout       ));
 
endmodule

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1	26	jefflieu	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.6 2008/08/17 11:41:30 maverickist`
43			`// no message`
44			`//`
45			`// Revision 1.5 2006/06/25 04:58:56 maverickist`
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47			`//`
48			`// Revision 1.4 2006/05/28 05:09:20 maverickist`
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50			`//`
51			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
52			`// verification is complete.`
53			`//`
54			`// Revision 1.3 2005/12/16 06:44:16 Administrator`
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56			`// passed 9.6k length frame test.`
57			`//`
58			`// Revision 1.2 2005/12/13 12:15:37 Administrator`
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60			`//`
61			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
62			`// no message`
63			`//`
64
65			`module MAC_rx_FF (`
66			`Reset ,`
67			`Clk_MAC ,`
68			`Clk_SYS ,`
69			`//MAC_rx_ctrl interface`
70			`Fifo_data ,`
71			`Fifo_data_en ,`
72			`Fifo_full ,`
73			`Fifo_data_err ,`
74			`Fifo_data_end ,`
75			`//CPU`
76			`Rx_Hwmark,`
77			`Rx_Lwmark,`
78			`RX_APPEND_CRC,`
79			`//user interface`
80			`Rx_mac_ra ,`
81			`Rx_mac_rd ,`
82			`Rx_mac_data ,`
83			`Rx_mac_BE ,`
84			`Rx_mac_sop ,`
85			`Rx_mac_pa,`
86			`Rx_mac_eop`
87			`);`
88			`input Reset ;`
89			`input Clk_MAC ;`
90			`input Clk_SYS ;`
91			`//MAC_rx_ctrl interface`
92			`input [7:0] Fifo_data ;`
93			`input Fifo_data_en ;`
94			`output Fifo_full ;`
95			`input Fifo_data_err ;`
96			`input Fifo_data_end ;`
97			`//CPU`
98			`input RX_APPEND_CRC ;`
99			`input [4:0] Rx_Hwmark ;`
100			`input [4:0] Rx_Lwmark ;`
101			`//user interface`
102			`output Rx_mac_ra ;//`
103			`input Rx_mac_rd ;`
104			`output [31:0] Rx_mac_data ;`
105			`output [1:0] Rx_mac_BE ;`
106			`output Rx_mac_pa ;`
107			`output Rx_mac_sop ;`
108			`output Rx_mac_eop ;`
109
110			`//******************************************************************************`
111			`//internal signals`
112			`//******************************************************************************`
113			`parameter State_byte3 =4'd0;`
114			`parameter State_byte2 =4'd1;`
115			`parameter State_byte1 =4'd2;`
116			`parameter State_byte0 =4'd3;`
117			`parameter State_be0 =4'd4;`
118			`parameter State_be3 =4'd5;`
119			`parameter State_be2 =4'd6;`
120			`parameter State_be1 =4'd7;`
121			`parameter State_err_end =4'd8;`
122			`parameter State_idle =4'd9;`
123
124			`parameter SYS_read =3'd0;`
125			`parameter SYS_pause =3'd1;`
126			`parameter SYS_wait_end =3'd2;`
127			`parameter SYS_idle =3'd3;`
128			`parameter FF_emtpy_err =3'd4;`
129
130			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
131			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
132			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
133			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
134			reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
135
136			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
137			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
138			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
139			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
140			reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
141			`reg [35:0] Din;`
142			`reg [35:0] Din_tmp;`
143			`reg [35:0] Din_tmp_reg;`
144			`wire[35:0] Dout;`
145			`reg Wr_en;`
146			`reg Wr_en_tmp;`
147			`reg Wr_en_ptr;`
148			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
149			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
150			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
151			wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
152			`reg Full;`
153			`reg Almost_full;`
154			`reg Empty /* synthesis syn_keep=1 */;`
155			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
156			`reg [3:0] Next_state;`
157			`reg [7:0] Fifo_data_byte0;`
158			`reg [7:0] Fifo_data_byte1;`
159			`reg [7:0] Fifo_data_byte2;`
160			`reg [7:0] Fifo_data_byte3;`
161			`reg Fifo_data_en_dl1;`
162			`reg [7:0] Fifo_data_dl1;`
163			`reg Rx_mac_sop_tmp ;`
164			`reg Rx_mac_sop ;`
165			`reg Rx_mac_ra ;`
166			`reg Rx_mac_pa ;`
167
168
169
170			`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
171			`reg [2:0] Next_state_SYS ;`
172			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
173			`reg Packet_number_sub ;`
174			`wire Packet_number_add_edge;`
175			`reg Packet_number_add_dl1;`
176			`reg Packet_number_add_dl2;`
177			`reg Packet_number_add ;`
178			`reg Packet_number_add_tmp ;`
179			`reg Packet_number_add_tmp_dl1;`
180			`reg Packet_number_add_tmp_dl2;`
181
182			`reg Rx_mac_sop_tmp_dl1;`
183			`reg [35:0] Dout_dl1;`
184			`reg [4:0] Fifo_data_count;`
185			`reg Rx_mac_pa_tmp ;`
186			`reg Add_wr_jump_tmp ;`
187			`reg Add_wr_jump_tmp_pl1 ;`
188			`reg Add_wr_jump ;`
189			`reg Add_wr_jump_rd_pl1 ;`
190			`reg [4:0] Rx_Hwmark_pl ;`
191			`reg [4:0] Rx_Lwmark_pl ;`
192			`reg Addr_freshed_ptr ;`
193			`integer i ;`
194			`//******************************************************************************`
195			`//domain Clk_MAC,write data to dprom.a-port for write`
196			`//******************************************************************************`
197			`always @ (posedge Clk_MAC or posedge Reset)`
198			`if (Reset)`
199			`Current_state <=State_idle;`
200			`else`
201			`Current_state <=Next_state;`
202
203			`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
204			`case (Current_state)`
205			`State_idle:`
206			`if (Fifo_data_en)`
207			`Next_state =State_byte3;`
208			`else`
209			`Next_state =Current_state;`
210			`State_byte3:`
211			`if (Fifo_data_en)`
212			`Next_state =State_byte2;`
213			`else if (Fifo_data_err)`
214			`Next_state =State_err_end;`
215			`else if (Fifo_data_end)`
216			`Next_state =State_be1;`
217			`else`
218			`Next_state =Current_state;`
219			`State_byte2:`
220			`if (Fifo_data_en)`
221			`Next_state =State_byte1;`
222			`else if (Fifo_data_err)`
223			`Next_state =State_err_end;`
224			`else if (Fifo_data_end)`
225			`Next_state =State_be2;`
226			`else`
227			`Next_state =Current_state;`
228			`State_byte1:`
229			`if (Fifo_data_en)`
230			`Next_state =State_byte0;`
231			`else if (Fifo_data_err)`
232			`Next_state =State_err_end;`
233			`else if (Fifo_data_end)`
234			`Next_state =State_be3;`
235			`else`
236			`Next_state =Current_state;`
237			`State_byte0:`
238			`if (Fifo_data_en)`
239			`Next_state =State_byte3;`
240			`else if (Fifo_data_err)`
241			`Next_state =State_err_end;`
242			`else if (Fifo_data_end)`
243			`Next_state =State_be0;`
244			`else`
245			`Next_state =Current_state;`
246			`State_be1:`
247			`Next_state =State_idle;`
248			`State_be2:`
249			`Next_state =State_idle;`
250			`State_be3:`
251			`Next_state =State_idle;`
252			`State_be0:`
253			`Next_state =State_idle;`
254			`State_err_end:`
255			`Next_state =State_idle;`
256			`default:`
257			`Next_state =State_idle;`
258			`endcase`
259
260			`//`
261			`always @ (posedge Clk_MAC or posedge Reset)`
262			`if (Reset)`
263			`Add_wr_reg <=0;`
264			`else if (Current_state==State_idle)`
265			`Add_wr_reg <=Add_wr;`
266
267			`//`
268
269
270			`always @ (posedge Reset or posedge Clk_MAC)`
271			`if (Reset)`
272			`Add_wr_gray <=0;`
273			`else`
274			`begin`
275			Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
276			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
277			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
278			`end`
279
280			`//`
281
282			`always @ (posedge Clk_MAC or posedge Reset)`
283			`if (Reset)`
284			`Add_rd_gray_dl1 <=0;`
285			`else`
286			`Add_rd_gray_dl1 <=Add_rd_gray;`
287
288			`always @ (posedge Clk_MAC or posedge Reset)`
289			`if (Reset)`
290			`Add_rd_ungray =0;`
291			`else`
292			`begin`
293			Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
294			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
295			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
296			`end`
297			`assign Add_wr_pluse=Add_wr+1;`
298			`assign Add_wr_pluse4=Add_wr+4;`
299			`assign Add_wr_pluse3=Add_wr+3;`
300			`assign Add_wr_pluse2=Add_wr+2;`
301
302
303
304			`always @ (posedge Clk_MAC or posedge Reset)`
305			`if (Reset)`
306			`Full <=0;`
307			`else if (Add_wr_pluse==Add_rd_ungray)`
308			`Full <=1;`
309			`else`
310			`Full <=0;`
311
312			`always @ (posedge Clk_MAC or posedge Reset)`
313			`if (Reset)`
314			`Almost_full <=0;`
315			`else if (Add_wr_pluse4==Add_rd_ungray\|\|`
316			`Add_wr_pluse3==Add_rd_ungray\|\|`
317			`Add_wr_pluse2==Add_rd_ungray\|\|`
318			`Add_wr_pluse==Add_rd_ungray`
319			`)`
320			`Almost_full <=1;`
321			`else`
322			`Almost_full <=0;`
323
324			`assign Fifo_full =Almost_full;`
325
326			`//`
327			`always @ (posedge Clk_MAC or posedge Reset)`
328			`if (Reset)`
329			`Add_wr <=0;`
330			`else if (Current_state==State_err_end)`
331			`Add_wr <=Add_wr_reg;`
332			`else if (Wr_en&&!Full)`
333			`Add_wr <=Add_wr +1;`
334
335			`always @ (posedge Clk_MAC or posedge Reset)`
336			`if (Reset)`
337			`Add_wr_jump_tmp <=0;`
338			`else if (Current_state==State_err_end)`
339			`Add_wr_jump_tmp <=1;`
340			`else`
341			`Add_wr_jump_tmp <=0;`
342
343			`always @ (posedge Clk_MAC or posedge Reset)`
344			`if (Reset)`
345			`Add_wr_jump_tmp_pl1 <=0;`
346			`else`
347			`Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;`
348
349			`always @ (posedge Clk_MAC or posedge Reset)`
350			`if (Reset)`
351			`Add_wr_jump <=0;`
352			`else if (Current_state==State_err_end)`
353			`Add_wr_jump <=1;`
354			`else if (Add_wr_jump_tmp_pl1)`
355			`Add_wr_jump <=0;`
356
357			`//`
358			`always @ (posedge Clk_MAC or posedge Reset)`
359			`if (Reset)`
360			`Fifo_data_en_dl1 <=0;`
361			`else`
362			`Fifo_data_en_dl1 <=Fifo_data_en;`
363
364			`always @ (posedge Clk_MAC or posedge Reset)`
365			`if (Reset)`
366			`Fifo_data_dl1 <=0;`
367			`else`
368			`Fifo_data_dl1 <=Fifo_data;`
369
370			`always @ (posedge Clk_MAC or posedge Reset)`
371			`if (Reset)`
372			`Fifo_data_byte3 <=0;`
373			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
374			`Fifo_data_byte3 <=Fifo_data_dl1;`
375
376			`always @ (posedge Clk_MAC or posedge Reset)`
377			`if (Reset)`
378			`Fifo_data_byte2 <=0;`
379			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
380			`Fifo_data_byte2 <=Fifo_data_dl1;`
381
382			`always @ (posedge Clk_MAC or posedge Reset)`
383			`if (Reset)`
384			`Fifo_data_byte1 <=0;`
385			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
386			`Fifo_data_byte1 <=Fifo_data_dl1;`
387
388			`always @ (* )`
389			`case (Current_state)`
390			`State_be0:`
391			`Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
392			`State_be1:`
393			`Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};`
394			`State_be2:`
395			`Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
396			`State_be3:`
397			`Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
398			`default:`
399			`Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
400			`endcase`
401
402			`always @ (*)`
403			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
404			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
405			`(Current_state==State_byte0&&Fifo_data_en))`
406			`Wr_en_tmp =1;`
407			`else`
408			`Wr_en_tmp =0;`
409
410			`always @ (posedge Clk_MAC or posedge Reset)`
411			`if (Reset)`
412			`Din_tmp_reg <=0;`
413			`else if(Wr_en_tmp)`
414			`Din_tmp_reg <=Din_tmp;`
415
416			`always @ (posedge Clk_MAC or posedge Reset)`
417			`if (Reset)`
418			`Wr_en_ptr <=0;`
419			`else if(Current_state==State_idle)`
420			`Wr_en_ptr <=0;`
421			`else if(Wr_en_tmp)`
422			`Wr_en_ptr <=1;`
423
424			`//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS`
425			`always @ (posedge Clk_MAC or posedge Reset)`
426			`if (Reset)`
427			`begin`
428			`Wr_en <=0;`
429			`Din <=0;`
430			`end`
431			`else if(RX_APPEND_CRC)`
432			`begin`
433			`Wr_en <=Wr_en_tmp;`
434			`Din <=Din_tmp;`
435			`end`
436			`else`
437			`begin`
438			`Wr_en <=Wr_en_tmp&&Wr_en_ptr;`
439			`Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};`
440			`end`
441
442			`//this signal for read side to handle the packet number in fifo`
443			`always @ (posedge Clk_MAC or posedge Reset)`
444			`if (Reset)`
445			`Packet_number_add_tmp <=0;`
446			`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
447			`Current_state==State_be2\|\|Current_state==State_be3)`
448			`Packet_number_add_tmp <=1;`
449			`else`
450			`Packet_number_add_tmp <=0;`
451
452			`always @ (posedge Clk_MAC or posedge Reset)`
453			`if (Reset)`
454			`begin`
455			`Packet_number_add_tmp_dl1 <=0;`
456			`Packet_number_add_tmp_dl2 <=0;`
457			`end`
458			`else`
459			`begin`
460			`Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;`
461			`Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;`
462			`end`
463
464			`//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.`
465			`//expand to two cycles long almost=16 ns`
466			`//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles`
467			`always @ (posedge Clk_MAC or posedge Reset)`
468			`if (Reset)`
469			`Packet_number_add <=0;`
470			`else if (Packet_number_add_tmp_dl1\|\|Packet_number_add_tmp_dl2)`
471			`Packet_number_add <=1;`
472			`else`
473			`Packet_number_add <=0;`
474
475
476
477
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479
480
481
482
483
484
485
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487
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489
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496
497
498			`//******************************************************************************`
499			`//domain Clk_SYS,read data from dprom.b-port for read`
500			`//******************************************************************************`
501
502
503			`always @ (posedge Clk_SYS or posedge Reset)`
504			`if (Reset)`
505			`Current_state_SYS <=SYS_idle;`
506			`else`
507			`Current_state_SYS <=Next_state_SYS;`
508
509			`always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)`
510			`case (Current_state_SYS)`
511			`SYS_idle:`
512			`if (Rx_mac_rd&&Rx_mac_ra&&!Empty)`
513			`Next_state_SYS =SYS_read;`
514			`else if(Rx_mac_rd&&Rx_mac_ra&&Empty)`
515			`Next_state_SYS =FF_emtpy_err;`
516			`else`
517			`Next_state_SYS =Current_state_SYS;`
518			`SYS_read:`
519			`if (Dout[35])`
520			`Next_state_SYS =SYS_wait_end;`
521			`else if (!Rx_mac_rd)`
522			`Next_state_SYS =SYS_pause;`
523			`else if (Empty)`
524			`Next_state_SYS =FF_emtpy_err;`
525			`else`
526			`Next_state_SYS =Current_state_SYS;`
527			`SYS_pause:`
528			`if (Rx_mac_rd)`
529			`Next_state_SYS =SYS_read;`
530			`else`
531			`Next_state_SYS =Current_state_SYS;`
532			`FF_emtpy_err:`
533			`if (!Empty)`
534			`Next_state_SYS =SYS_read;`
535			`else`
536			`Next_state_SYS =Current_state_SYS;`
537			`SYS_wait_end:`
538			`if (!Rx_mac_rd)`
539			`Next_state_SYS =SYS_idle;`
540			`else`
541			`Next_state_SYS =Current_state_SYS;`
542			`default:`
543			`Next_state_SYS =SYS_idle;`
544			`endcase`
545
546
547			`//gen Rx_mac_ra`
548			`always @ (posedge Clk_SYS or posedge Reset)`
549			`if (Reset)`
550			`begin`
551			`Packet_number_add_dl1 <=0;`
552			`Packet_number_add_dl2 <=0;`
553			`end`
554			`else`
555			`begin`
556			`Packet_number_add_dl1 <=Packet_number_add;`
557			`Packet_number_add_dl2 <=Packet_number_add_dl1;`
558			`end`
559			`assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;`
560
561			`always @ (Current_state_SYS or Next_state_SYS)`
562			`if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)`
563			`Packet_number_sub =1;`
564			`else`
565			`Packet_number_sub =0;`
566
567			`always @ (posedge Clk_SYS or posedge Reset)`
568			`if (Reset)`
569			`Packet_number_inFF <=0;`
570			`else if (Packet_number_add_edge&&!Packet_number_sub)`
571			`Packet_number_inFF <=Packet_number_inFF + 1;`
572			`else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)`
573			`Packet_number_inFF <=Packet_number_inFF - 1;`
574
575			`always @ (posedge Clk_SYS or posedge Reset)`
576			`if (Reset)`
577			`Fifo_data_count <=0;`
578			`else`
579			Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
580
581			`always @ (posedge Clk_SYS or posedge Reset)`
582			`if (Reset)`
583			`begin`
584			`Rx_Hwmark_pl <=0;`
585			`Rx_Lwmark_pl <=0;`
586			`end`
587			`else`
588			`begin`
589			`Rx_Hwmark_pl <=Rx_Hwmark;`
590			`Rx_Lwmark_pl <=Rx_Lwmark;`
591			`end`
592
593			`always @ (posedge Clk_SYS or posedge Reset)`
594			`if (Reset)`
595			`Rx_mac_ra <=0;`
596			`else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)`
597			`Rx_mac_ra <=0;`
598			`else if (Packet_number_inFF>=1\|\|Fifo_data_count>=Rx_Hwmark_pl)`
599			`Rx_mac_ra <=1;`
600
601
602			`//control Add_rd signal;`
603			`always @ (posedge Clk_SYS or posedge Reset)`
604			`if (Reset)`
605			`Add_rd <=0;`
606			`else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))`
607			`Add_rd <=Add_rd + 1;`
608
609			`always @ (posedge Clk_SYS or posedge Reset)`
610			`if (Reset)`
611			`Add_rd_pl1 <=0;`
612			`else`
613			`Add_rd_pl1 <=Add_rd;`
614
615			`always @(Add_rd_pl1,Add_rd)`
616			`if (Add_rd_pl1==Add_rd)`
617			`Addr_freshed_ptr =0;`
618			`else`
619			`Addr_freshed_ptr =1;`
620
621			`//`
622			`always @ (posedge Reset or posedge Clk_SYS)`
623			`if (Reset)`
624			`Add_rd_gray <=0;`
625			`else`
626			`begin`
627			Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
628			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
629			`Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];`
630			`end`
631			`//`
632
633			`always @ (posedge Clk_SYS or posedge Reset)`
634			`if (Reset)`
635			`Add_wr_gray_dl1 <=0;`
636			`else`
637			`Add_wr_gray_dl1 <=Add_wr_gray;`
638
639			`always @ (posedge Clk_SYS or posedge Reset)`
640			`if (Reset)`
641			`Add_wr_jump_rd_pl1 <=0;`
642			`else`
643			`Add_wr_jump_rd_pl1 <=Add_wr_jump;`
644
645			`always @ (posedge Clk_SYS or posedge Reset)`
646			`if (Reset)`
647			`Add_wr_ungray =0;`
648			`else if (!Add_wr_jump_rd_pl1)`
649			`begin`
650			Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
651			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
652			`Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];`
653			`end`
654			`//empty signal gen`
655			`always @ (posedge Clk_SYS or posedge Reset)`
656			`if (Reset)`
657			`Empty <=1;`
658			`else if (Add_rd==Add_wr_ungray)`
659			`Empty <=1;`
660			`else`
661			`Empty <=0;`
662
663
664
665			`always @ (posedge Clk_SYS or posedge Reset)`
666			`if (Reset)`
667			`Dout_dl1 <=0;`
668			`else`
669			`Dout_dl1 <=Dout;`
670
671			`assign Rx_mac_data =Dout_dl1[31:0];`
672			`assign Rx_mac_BE =Dout_dl1[33:32];`
673			`assign Rx_mac_eop =Dout_dl1[35];`
674
675			`//aligned to Addr_rd`
676			`always @ (posedge Clk_SYS or posedge Reset)`
677			`if (Reset)`
678			`Rx_mac_pa_tmp <=0;`
679			`else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))`
680			`Rx_mac_pa_tmp <=1;`
681			`else`
682			`Rx_mac_pa_tmp <=0;`
683
684
685
686			`always @ (posedge Clk_SYS or posedge Reset)`
687			`if (Reset)`
688			`Rx_mac_pa <=0;`
689			`else`
690			`Rx_mac_pa <=Rx_mac_pa_tmp;`
691
692
693
694			`always @ (posedge Clk_SYS or posedge Reset)`
695			`if (Reset)`
696			`Rx_mac_sop_tmp <=0;`
697			`else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)`
698			`Rx_mac_sop_tmp <=1;`
699			`else`
700			`Rx_mac_sop_tmp <=0;`
701
702
703
704			`always @ (posedge Clk_SYS or posedge Reset)`
705			`if (Reset)`
706			`begin`
707			`Rx_mac_sop_tmp_dl1 <=0;`
708			`Rx_mac_sop <=0;`
709			`end`
710			`else`
711			`begin`
712			`Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;`
713			`Rx_mac_sop <=Rx_mac_sop_tmp_dl1;`
714			`end`
715
716
717
718			`//******************************************************************************`
719
720			duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
721			`.data_a (Din ),`
722			`.wren_a (Wr_en ),`
723			`.address_a (Add_wr ),`
724			`.address_b (Add_rd ),`
725			`.clock_a (Clk_MAC ),`
726			`.clock_b (Clk_SYS ),`
727			`.q_b (Dout ));`
728
729			`endmodule`